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21. 发明授权

US07037803B2 Manufacture of semiconductor device having STI and semiconductor device manufactured 有权
标题翻译：制造具有STI和半导体器件的半导体器件的制造
公开(公告)号：US07037803B2
公开(公告)日：2006-05-02
申请号：US10721870
申请日：2003-11-26
申请人： Kengo Inoue , Toshifumi Mori , Ryou Nakamura , Hiroyuki Ohta , Takashi Saiki
发明人： Kengo Inoue , Toshifumi Mori , Ryou Nakamura , Hiroyuki Ohta , Takashi Saiki
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/823871 , H01L21/823878
摘要： A semiconductor device manufacture method has the steps of: (a) forming a polishing stopper layer over a semiconductor substrate; (b) etching the semiconductor substrate to form a trench; (c) forming a first liner insulating layer of silicon oxide over the surface of the trench; (d) forming a second liner insulating layer of silicon nitride over the first liner insulating layer, the second liner insulating layer having a thickness of at least 20 nm or at most 8 nm; (e1) depositing a third liner insulating layer of silicon oxide over the second liner insulating layer by plasma CVD at a first bias; and (e2) depositing an isolation layer of silicon oxide by plasma CVD at a second bias higher than the first bias, the isolation layer burying a recess defined by the third liner insulating layer.
摘要翻译：半导体器件制造方法具有以下步骤：（a）在半导体衬底上形成抛光阻挡层; （b）蚀刻半导体衬底以形成沟槽; （c）在所述沟槽的表面上形成氧化硅的第一衬垫绝缘层; （d）在所述第一衬垫绝缘层上形成氮化硅的第二衬垫绝缘层，所述第二衬垫绝缘层的厚度为至少20nm或至多8nm; （e1）在第一偏压下通过等离子体CVD沉积第二衬里绝缘层上的第三衬垫绝缘层氧化硅; 和（e2）以高于第一偏压的第二偏压通过等离子体CVD沉积氧化硅隔离层，隔离层埋设由第三衬里绝缘层限定的凹部。

22. 发明授权

US07009279B2 Semiconductor device configured for suppressed germanium diffusion from a germanium-doped regions and a method for fabrication thereof 失效
标题翻译：配置用于抑制从锗掺杂区域扩散锗的半导体器件及其制造方法
公开(公告)号：US07009279B2
公开(公告)日：2006-03-07
申请号：US10845290
申请日：2004-05-12
申请人： Shingo Nasu , Tomio Iwasaki , Hiroyuki Ohta , Yukihiro Kumagai , Shuji Ikeda
发明人： Shingo Nasu , Tomio Iwasaki , Hiroyuki Ohta , Yukihiro Kumagai , Shuji Ikeda
IPC分类号： H01L31/117
CPC分类号： H01L29/167 , H01L21/2807 , H01L29/1004 , H01L29/1054 , H01L29/4966 , H01L29/7378
摘要： In semiconductor devices, a semiconductor device is provided which is high in reliability while suppressing changes in characteristics such as threshold voltages. In a semiconductor device which has a gate dielectric film above a semiconductor substrate and also has above the gate dielectric film a gate electrode film made of silicon germanium chosen as its main constituent material, or alternatively in a semiconductor device which has beneath the gate dielectric film a channel made of silicon as its main constituent material and which has below the channel a channel underlayer film made of silicon germanium as its main constituent material, a specifically chosen dopant, such as cobalt (Co) or carbon (C) or nitrogen (N), is added to the gate electrode and the channel underlayer film, for use as the unit for suppressing diffusion of germanium in the gate electrode or in the channel underlayer film.
摘要翻译：在半导体器件中，提供了一种在抑制诸如阈值电压的特性变化的同时高可靠性的半导体器件。在半导体器件中，在半导体衬底上方具有栅极电介质膜，并且还具有栅极电介质膜上方的由选择为主要构成材料的硅锗制成的栅电极膜，或者替代地在栅极电介质膜下方的半导体器件由硅作为其主要构成材料的通道，并且在通道下方具有由硅锗作为其主要构成材料的沟道下层膜，特别选择的掺杂剂，例如钴（Co）或碳（C）或氮（N ）添加到栅极电极和沟道下层膜中，用作抑制栅极电极或沟道下层膜中锗扩散的单元。

23. 发明授权

US06960832B2 Semiconductor device and its production process 失效
标题翻译：半导体器件及其生产工艺
公开(公告)号：US06960832B2
公开(公告)日：2005-11-01
申请号：US10761333
申请日：2004-01-22
申请人： Hiromi Shimazu , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Shuji Ikeda
发明人： Hiromi Shimazu , Tomio Iwasaki , Hiroyuki Ohta , Hideo Miura , Shuji Ikeda
IPC分类号： H01L21/285 , H01L21/336 , H01L21/768 , H01L23/12 , H01L21/00
CPC分类号： H01L29/665 , H01L21/28518 , H01L21/76877
摘要： In a semiconductor device having a cobalt silicide film, at least nickel or iron is contained in the cobalt silicide film for preventing the rise of resistance incidental to thinning of the film.
摘要翻译：在具有钴硅化物膜的半导体器件中，钴硅化物膜中至少含有镍或铁，以防止附着于薄膜变薄的电阻上升。

24. 发明申请

US20050236679A1 Semiconductor device, and method and apparatus for manufacturing the same 有权
公开(公告)号：US20050236679A1
公开(公告)日：2005-10-27
申请号：US11147212
申请日：2005-06-08
申请人： Mitsuaki Hori , Hiroyuki Ohta , Katsuaki Ookoshi
发明人： Mitsuaki Hori , Hiroyuki Ohta , Katsuaki Ookoshi
IPC分类号： C23C16/00 , C23C16/02 , C23C16/34 , H01L21/28 , H01L21/314 , H01L21/318 , H01L21/8234 , H01L29/51 , H01L29/76 , H01L29/78
CPC分类号： H01L21/022 , C23C16/0272 , C23C16/345 , H01L21/02115 , H01L21/28185 , H01L21/28202 , H01L21/3145 , H01L21/3185 , H01L29/513 , H01L29/518
摘要： A SiO2 film is formed on a semiconductor substrate. Then, a SiN film is formed on the SiO2 film. In this event bis (tertiary butyl amino) silane and NH3 are used as a material gas, and the film forming temperature is set to 600° C. or lower.

25. 发明授权

US06856021B1 Semiconductor device having aluminum alloy conductors 失效
标题翻译：具有铝合金导体的半导体器件
公开(公告)号：US06856021B1
公开(公告)日：2005-02-15
申请号：US09648455
申请日：2000-08-28
申请人： Tomio Iwasaki , Hideo Miura , Takashi Nakajima , Hiroyuki Ohta , Shinji Nishihara , Masashi Sahara
发明人： Tomio Iwasaki , Hideo Miura , Takashi Nakajima , Hiroyuki Ohta , Shinji Nishihara , Masashi Sahara
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/532
CPC分类号： H01L21/76844 , H01L21/32051 , H01L21/76843 , H01L21/7685 , H01L23/53219 , H01L23/53223 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided which includes a semiconductor substrate, metal conductors formed on a side of a main face of the substrate, which metal conductors contain aluminum as a main constituent thereof, and copper as an additive element, the metal conductors being made to contain such an element as to suppress the precipitation of copper or being made to have such a film adjacent to the metal conductor as to suppress the precipitation of copper or being made to have such a film adjacent to the metal conductor as to suppress the precipitation of copper.
摘要翻译：提供了一种半导体器件，其包括半导体衬底，形成在衬底的主面一侧的金属导体，该金属导体以铝为主要成分，铜作为添加元素，金属导体被制成含有抑制铜的析出或使金属导体附近具有这样的膜的元素，以抑制铜的沉淀，或者使该膜与金属导体相邻，以抑制铜的析出。

26. 发明申请

US20050024811A1 Semiconductor device with adhesion-improvement capacitor and process for producing the device 失效
标题翻译：具有粘附改善电容器的半导体器件及其制造方法
公开(公告)号：US20050024811A1
公开(公告)日：2005-02-03
申请号：US10923002
申请日：2004-08-23
申请人： Hiroshi Moriya , Tomio Iwasaki , Hiroyuki Ohta , Shinpei Iijima , Isamu Asano , Yuzuru Ohji , Yoshitaka Nakamura
发明人： Hiroshi Moriya , Tomio Iwasaki , Hiroyuki Ohta , Shinpei Iijima , Isamu Asano , Yuzuru Ohji , Yoshitaka Nakamura
IPC分类号： H01L27/10 , H01L21/02 , H01L21/8242 , H01L27/108 , H01G4/008
CPC分类号： H01L28/60 , H01L27/10814 , H01L28/55
摘要： A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.
摘要翻译：一种配备有信息存储电容器的半导体器件，包括第一电容器电极，氧化物膜，第二电容器电极和以硅为主要构成元素的绝缘膜，其中，第一和第二电容器电极中的至少一个包含作为主要构成元素选自铑，钌，铱，锇和铂中的至少一种元素，并且作为添加元素，选自钯，镍，钴和钛中的至少一种元素，电容器电极和绝缘膜之间的粘附性优异。

27. 发明授权

US06566149B1 Method for manufacturing substrate for inspecting semiconductor device 失效
标题翻译：用于检查半导体器件的衬底的制造方法
公开(公告)号：US06566149B1
公开(公告)日：2003-05-20
申请号：US09787250
申请日：2001-03-16
申请人： Masatoshi Kanamaru , Atsushi Hosogane , Yoshihige Endou , Ryuji Kouno , Hideo Miura , Shinji Tanaka , Hiroyuki Ohta , Akihiko Ariga , Naoto Ban , Hideyuki Aoki
发明人： Masatoshi Kanamaru , Atsushi Hosogane , Yoshihige Endou , Ryuji Kouno , Hideo Miura , Shinji Tanaka , Hiroyuki Ohta , Akihiko Ariga , Naoto Ban , Hideyuki Aoki
IPC分类号： G01R3126
CPC分类号： G01R3/00
摘要： For an inspection tray, a silicon substrate including a beam or a diaphragm, a probe and wiring is used. To highly accurately position a chip to be inspected, a second substrate for alignment is disposed on the substrate. To position the probe having wiring disposed on the first substrate and the electrode pad of the chip to be inspected, a projection or a groove is formed in each of both substrates. Preferably, the projection or groove should be formed by silicon anisotorpic etching to have a (111) crystal surface. As another machining method, dry etching can be used for machining the positioning projection or groove. By using an inductively coupled plasma-reactive ion etching (ICP-RIE) device for the dry etching, a vertical column or groove can be easily machined.
摘要翻译：对于检查托盘，使用包括梁或隔膜，探针和布线的硅基板。为了高精度地定位待检查的芯片，在基板上设置用于对准的第二基板。为了定位具有设置在第一基板上的布线的探针和要检查的芯片的电极焊盘，在两个基板中的每一个中形成突起或凹槽。优选地，突起或凹槽应由硅各向异性蚀刻形成以具有（111）晶体表面。作为另一种加工方法，可以使用干蚀刻来加工定位突起或凹槽。通过使用用于干蚀刻的电感耦合等离子体反应离子蚀刻（ICP-RIE）装置，可以容易地加工垂直的柱或槽。

28. 发明授权

US06544884B2 Semiconductor device and method of fabricating same 失效
公开(公告)号：US06544884B2
公开(公告)日：2003-04-08
申请号：US10022525
申请日：2001-12-20
申请人： Hiroyuki Ohta , Hideo Miura , Kazushige Sato , Takeshi Kimura , Hiyoo Masuda
发明人： Hiroyuki Ohta , Hideo Miura , Kazushige Sato , Takeshi Kimura , Hiyoo Masuda
IPC分类号： H01L214763
CPC分类号： H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device capable of operating at a high speed or of having many functions. In this device, delamination of buried electrodes is prevented and thus high reliability is offered. The depth A of contact holes, the minimum linewidth R of a lower metallization layer, and the thickness B of the lower metallization layer satisfy relations given by (0.605/R)0.5

29. 发明授权

US06468845B1 Semiconductor apparatus having conductive thin films and manufacturing apparatus therefor 失效
标题翻译：具有导电薄膜的半导体装置及其制造装置
公开(公告)号：US06468845B1
公开(公告)日：2002-10-22
申请号：US09536642
申请日：2000-03-28
申请人： Takashi Nakajima , Hideo Miura , Hiroyuki Ohta , Noriaki Okamoto
发明人： Takashi Nakajima , Hideo Miura , Hiroyuki Ohta , Noriaki Okamoto
IPC分类号： H01L2184
CPC分类号： H01L21/28097 , H01L21/28035 , H01L21/28518 , H01L21/28525 , H01L21/32053 , H01L21/76838 , H01L21/76877 , H01L21/823437 , H01L23/485 , H01L23/53257 , H01L23/53271 , H01L28/40 , H01L29/4925 , H01L29/4975 , H01L2924/0002 , Y10T117/10 , Y10T117/1004 , H01L2924/00
摘要： In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.
摘要翻译：例如，通过氧化硅膜5在半导体衬底4上的氧化硅膜5上形成电极2时，栅电极2被构成为多个多晶硅层6的层叠结构。栅极部分通过制造具有沉积非晶层的工艺的薄膜的方法和使该非晶材料结晶（再结晶）的方法形成电极2。在这种情况下，非晶层的沉积被分开多次进行，使得一次沉积的非晶层的厚度不大于根据根据下式确定的临界应力值规定的厚度在每个非晶层的沉积过程完成之后，非晶材料结晶，重复沉积非晶层的过程和结晶非晶材料的过程，由此多晶层6的层压结构具有必要的获得膜厚度。利用上述结构，可以防止半导体器件的电特性的恶化和层之间的剥离等缺陷的发生，层中的裂纹等，并且可以获得通过多晶材料的层叠，具有所需膜厚度的小晶粒尺寸的多晶层。

30. 发明授权

US06337517B1 Semiconductor device and method of fabricating same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06337517B1
公开(公告)日：2002-01-08
申请号：US09151590
申请日：1998-09-11
申请人： Hiroyuki Ohta , Hideo Miura , Kazushige Sato , Takeshi Kimura , Hiroo Masuda
发明人： Hiroyuki Ohta , Hideo Miura , Kazushige Sato , Takeshi Kimura , Hiroo Masuda
IPC分类号： H01L2348
CPC分类号： H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device capable of operating at a high speed or of having many functions. In this device, delamination of buried electrodes is prevented and thus high reliability is offered. The depth A of contact holes, the minimum linewidth R of a lower metallization layer, and the thickness B of the lower metallization layer satisfy relations given by (0.605/R)0.5
摘要翻译：能够高速运转或具有许多功能的半导体装置。在该装置中，防止了埋入电极的分层，从而提供了高可靠性。接触孔的深度A，下部金属化层的最小线宽R和下部金属化层的厚度B满足关系式

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