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21. 发明授权

US6040619A Semiconductor device including antireflective etch stop layer 失效
标题翻译：半导体器件包括抗反射蚀刻停止层
公开(公告)号：US6040619A
公开(公告)日：2000-03-21
申请号：US937774
申请日：1997-09-25
申请人： Fei Wang , David K. Foote , Myron R. Cagan , Subhash Gupta
发明人： Fei Wang , David K. Foote , Myron R. Cagan , Subhash Gupta
IPC分类号： H01L21/28 , H01L21/027 , H01L21/312 , H01L21/314 , H01L21/318 , H01L21/336 , H01L21/768 , H01L21/8244 , H01L23/522 , H01L27/11 , H01L29/78 , H01L23/58 , H01L21/316 , H01L23/48
CPC分类号： H01L21/0276 , H01L21/3121 , H01L21/3144 , H01L21/3145 , H01L21/76802 , H01L21/76834 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002
摘要： A microelectronic device such as a Metal-Oxide-Semiconductor (MOS) transistor is formed on a semiconductor substrate. A tungsten damascene interconnect for the device is formed using an etch stop layer of silicon nitride, silicon oxynitride or silicon oxime having a high silicon content of approximately 40% to 50% by weight. The etch stop layer has high etch selectivity relative to overlying insulator materials such as silicon dioxide, tetraethylorthosilicate (TEOS) glass and borophosphosilicate glass (BPSG). The etch stop layer also has a high index of refraction and is anti-reflective, thereby improving critical dimension control during photolithographic imaging.
摘要翻译：在半导体衬底上形成诸如金属氧化物半导体（MOS）晶体管的微电子器件。用于器件的钨镶嵌互连使用具有大约40％至50％重量比的高硅含量的氮化硅，氮氧化硅或硅肟的蚀刻停止层形成。蚀刻停止层相对于上覆绝缘体材料如二氧化硅，原硅酸四乙酯（TEOS）玻璃和硼磷硅酸盐玻璃（BPSG）具有高蚀刻选择性。蚀刻停止层还具有高折射率并且是抗反射性的，从而改善光刻成像期间的临界尺寸控制。

22. 发明授权

US06528390B2 Process for fabricating a non-volatile memory device 有权
公开(公告)号：US06528390B2
公开(公告)日：2003-03-04
申请号：US09798667
申请日：2001-03-02
申请人： Hideki Komori , David K. Foote , Fei Wang , Bharath Rangarajan
发明人： Hideki Komori , David K. Foote , Fei Wang , Bharath Rangarajan
IPC分类号： H01L2176
CPC分类号： H01L21/76213
摘要： A method for fabricating a semiconductor structure includes growing regions of oxide on a first structure, to form bit-line regions; wherein said semiconductor structure includes a semiconducting substrate, a patterned ONO layer on said substrate, wherein said patterned ONO layer comprises regions of ONO and exposed regions of said semiconducting substrate, a patterned hard mask layer on said regions of ONO, and a patterned photoresist layer on said patterned hard mask layer.

23. 发明授权

US06410388B1 Process for optimizing pocket implant profile by RTA implant annealing for a non-volatile semiconductor device 有权
标题翻译：用于通过用于非易失性半导体器件的RTA注入退火优化口袋注入轮廓的工艺
公开(公告)号：US06410388B1
公开(公告)日：2002-06-25
申请号：US09620480
申请日：2000-07-20
申请人： George Jonathan Kluth , Stephen K. Park , Arvind Halliyal , David K. Foote
发明人： George Jonathan Kluth , Stephen K. Park , Arvind Halliyal , David K. Foote
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A process for fabricating a memory cell in a two-bit EEPROM device, includes forming an ONO layer overlying a semiconductor substrate, depositing a resist mask overlying the ONO layer, patterning the resist mask, implanting the semiconductor substrate with a p-type dopant, wherein the resist mask is used as an ion implant mask, and annealing the semiconductor substrate before implanting the semiconductor substrate with an n-type dopant. In one preferred embodiment, the annealing of the semiconductor substrate laterally diffuses the p-type dopants to form pocket regions on either side of the EEPROM device.
摘要翻译：一种用于在2位EEPROM器件中制造存储单元的工艺，包括形成覆盖半导体衬底的ONO层，沉积覆盖在ONO层上的抗蚀剂掩模，图案化抗蚀剂掩模，用p型掺杂剂注入半导体衬底，其中抗蚀剂掩模用作离子注入掩模，并且在用n型掺杂剂注入半导体衬底之前退火半导体衬底。在一个优选实施例中，半导体衬底的退火横向扩散p型掺杂剂以在EEPROM器件的任一侧上形成袋区。

24. 发明授权

US06365320B1 Process for forming anti-reflective film for semiconductor fabrication using extremely short wavelength deep ultraviolet photolithography 有权
标题翻译：使用极短波长深紫外光刻法形成用于半导体制造的抗反射膜的方法
公开(公告)号：US06365320B1
公开(公告)日：2002-04-02
申请号：US09233849
申请日：1999-01-19
申请人： David K. Foote , Subhash Gupta
发明人： David K. Foote , Subhash Gupta
IPC分类号： G03C1725
CPC分类号： H01L21/0276 , H01L21/3121 , H01L21/3144 , H01L21/3145 , H01L21/76802 , H01L21/76895 , H01L23/5226 , H01L2924/0002 , Y10S430/151 , H01L2924/00
摘要： An anti-reflective film for deep ultraviolet (DUV) photolithograghy includes silicon oxime having the formula Si(1−x+y+z)NxOy:H2, wherein x, y, and z represent the atomic percentage of nitrogen, oxygen, and hydrogen, respectively. The film is characterized by a substantial lack of bonding between silicon atoms and oxygen atoms, and has a thickness of less than approximately 600 Å which is selected to produce destructive interference between incident and reflected light at a selected DUV wavelength.
摘要翻译：用于深紫外（DUV）光刻的抗反射膜包括具有式Si（1-x + y + z）N x O y：H 2的硅肟，其中x，y和z表示氮，氧和氢的原子百分比，分别。该膜的特征在于硅原子和氧原子之间的键合相当大，并且具有小于约600的厚度，其被选择为在选定的DUV波长处产生入射光和反射光之间的相消干涉。

25. 发明授权

US06297143B1 Process for forming a bit-line in a MONOS device 有权
标题翻译：在MONOS设备中形成位线的过程
公开(公告)号：US06297143B1
公开(公告)日：2001-10-02
申请号：US09426743
申请日：1999-10-25
申请人： David K. Foote , Bharath Rangarajan , Fei Wang , Steven K. Park
发明人： David K. Foote , Bharath Rangarajan , Fei Wang , Steven K. Park
IPC分类号： H01L214763
CPC分类号： H01L27/11568 , H01L27/11517
摘要： A process for fabricating a MONOS device having a buried bit-line includes providing a semiconductor substrate and forming a mask layer overlying the semiconductor substrate. Thereafter, an etch process is performed to form a trench in the semiconductor substrate. Next, the mask layer is removed and the trench in the semiconductor substrate is filled with a silicon oxide layer. To form a bit-line oxide layer, a planarization process is utilized to planarize the silicon oxide layer and form a planar surface continuous with an upper surface of the semiconductor substrate.
摘要翻译：用于制造具有掩埋位线的MONOS器件的工艺包括提供半导体衬底并形成覆盖半导体衬底的掩模层。此后，进行蚀刻处理以在半导体衬底中形成沟槽。接下来，去除掩模层，并且用氧化硅层填充半导体衬底中的沟槽。为了形成位线氧化层，利用平面化工艺来平坦化氧化硅层并形成与半导体衬底的上表面连续的平面。

26. 发明授权

US06290202B1 Apparatus for molding thin resin sheets 有权
标题翻译：用于模制薄树脂片的装置
公开(公告)号：US06290202B1
公开(公告)日：2001-09-18
申请号：US09496440
申请日：2000-02-02
申请人： Kurt P. Rindoks , David K. Foote
发明人： Kurt P. Rindoks , David K. Foote
IPC分类号： B29C5138
CPC分类号： B29C33/0088 , B29C33/0011 , B29C33/28 , B29C35/02 , B29C39/06 , B29C39/265 , B29C39/38 , Y10S425/201
摘要： A mold (10) for molding thin resin sheets includes a center mold plate (12) and two side mold plates (14, 16) disposed on opposite sides of the center mold plate. The mold plates are oriented generally vertically and parallel to each other, and the side mold plates are narrowly spaced from the center mold plate to define a pair of generally vertical mold cavities (18, 20) on either side of the center mold plate. The side mold plates may optionally include recesses (51) in their generally planar mold surfaces (38, 40) adjacent at least one longitudinal edge of the plate, for molding thin resin sheets with integral edge flanges. The mold includes spacer strips (46, 47) for spacing the side mold plates a precise distance from the center mold plate and parallel thereto. The mold thus permits molding of thin resin sheets having precisely controlled uniform thickness.
摘要翻译：用于模制薄树脂片的模具（10）包括设置在中心模板的相对侧上的中心模板（12）和两个侧模板（14,16）。模板通常垂直并且彼此平行，并且侧模板与中心模板间隔开狭窄，以在中心模板的任一侧上限定一对大致垂直的模腔（18,20）。侧模板可以可选地在其与板的至少一个纵向边缘相邻的大致平面的模具表面（38,40）中包括凹部（51），用于模制具有整体边缘凸缘的薄树脂板。模具包括间隔条（46,47），用于将侧模板与中心模板隔开并与其平行的距离。因此，模具可以模制具有精确控制均匀厚度的薄树脂片材。

27. 发明授权

US06168993A Process for fabricating a semiconductor device having a graded junction 有权
标题翻译：具有渐变结的半导体器件的制造方法
公开(公告)号：US06168993A
公开(公告)日：2001-01-02
申请号：US09487922
申请日：2000-01-19
申请人： David K. Foote , Bharath Rangarajan , George Kluth , Fei Wang
发明人： David K. Foote , Bharath Rangarajan , George Kluth , Fei Wang
IPC分类号： H01L218247
CPC分类号： H01L29/66825
摘要： A process for fabricating a semiconductor device includes the step of processing a patterned resist layer to vary the lateral dimensions of the patterned resist layer while forming doped regions in a semiconductor substrate. A graded junction profile is formed by creating a patterned resist layer having a first substantially vertical edge surface. A doping process is carried out to form a first doped region in the semiconductor substrate having a junction profile substantially continuous with the first substantially vertical edge surface. The patterned resist layer is processed to form a second substantially vertical edge surface, which is laterally displaced from the first substantially vertical edge surface. A doping process is carried out to form a second doped region having a junction profile that is substantially continuous with the second substantially vertical edge surface. The junction profiles of the first and second doped regions form a graded junction within the semiconductor substrate. The process can be repeated to form a wide variety of graded junction profiles within a semiconductor substrate.
摘要翻译：制造半导体器件的方法包括处理图案化的抗蚀剂层以改变图案化的抗蚀剂层的横向尺寸同时在半导体衬底中形成掺杂区域的步骤。通过产生具有第一基本上垂直的边缘表面的图案化抗蚀剂层来形成分级结型材。执行掺杂工艺以在半导体衬底中形成具有与第一基本上垂直的边缘表面基本连续的接合轮廓的第一掺杂区域。图案化的抗蚀剂层被加工成形成第二基本上垂直的边缘表面，其从第一基本上垂直的边缘表面横向移位。进行掺杂工艺以形成具有与第二基本上垂直的边缘表面基本连续的接合轮廓的第二掺杂区域。第一和第二掺杂区的结型材在半导体衬底内形成渐变结。可以重复该过程以在半导体衬底内形成多种渐变连接轮廓。

28. 发明申请

US20140034610A1 APPARATUS AND METHODS FOR HANDLING WORKPIECES OF DIFFERENT SIZES 有权
标题翻译：用于处理不同尺寸的工件的装置和方法
公开(公告)号：US20140034610A1
公开(公告)日：2014-02-06
申请号：US13567507
申请日：2012-08-06
申请人： James P. Fazio , David K. Foote , James D. Getty
发明人： James P. Fazio , David K. Foote , James D. Getty
IPC分类号： H05H1/24 , B44C1/22
CPC分类号： H01L21/67742 , C23C16/458 , C23C16/4582 , C23C16/4583 , C23C16/4585 , H01L21/67745 , H01L21/67748 , H01L21/67751 , H01L21/68735 , H01L21/68771
摘要： Apparatus and methods for plasma processing workpieces of different diameters. The apparatus includes a lift plate having an outer perimeter, an opening inside of the outer perimeter, and a gap extending between the opening and the outer perimeter. The lift plate includes annular rims of different inner diameters and that are configured to respectively support the first and second workpieces.
摘要翻译：用于等离子体处理不同直径工件的装置和方法。该装置包括具有外周边的提升板，外周边的内部的开口以及在开口和外周之间延伸的间隙。提升板包括不同内径的环形轮辋，并且构造成分别支撑第一和第二工件。

29. 发明申请

US20110000882A1 APPARATUS AND METHODS FOR SUPPORTING WORKPIECES DURING PLASMA PROCESSING 有权
标题翻译：用于在等离子体处理过程中支持工件的装置和方法
公开(公告)号：US20110000882A1
公开(公告)日：2011-01-06
申请号：US12496369
申请日：2009-07-01
申请人： David K. Foote , James D. Getty
发明人： David K. Foote , James D. Getty
IPC分类号： C23F1/00
CPC分类号： G11B5/855 , H01J37/32431
摘要： Apparatus and methods for simultaneously supporting multiple workpieces inside a processing space of a plasma processing system for simultaneous two-sided plasma processing. The apparatus may be a fixture having a carrier plate configured to be supported inside the processing space and a plurality of first openings extending through the thickness of the carrier plate. The carrier plate is configured to contact each of the workpieces over an annular region at an outer peripheral edge so that the first and second sides of each of the workpieces is exposed to the plasma through a respective one of said plurality of first openings.
摘要翻译：用于同时支撑等离子体处理系统的处理空间内的多个工件的装置和方法，用于同时进行双面等离子体处理。该装置可以是具有被配置为被支撑在处理空间内的承载板和穿过承载板的厚度延伸的多个第一开口的固定装置。承载板构造成在外周边缘的环形区域上接触每个工件，使得每个工件的第一和第二侧面通过所述多个第一开口中的相应一个暴露于等离子体。

30. 发明授权

US06406960B1 Process for fabricating an ONO structure having a silicon-rich silicon nitride layer 有权
标题翻译：制造具有富硅氮化硅层的ONO结构的方法
公开(公告)号：US06406960B1
公开(公告)日：2002-06-18
申请号：US09433041
申请日：1999-10-25
申请人： Dawn M. Hopper , David K. Foote , Bharath Rangarajan , Arvind Halliyal
发明人： Dawn M. Hopper , David K. Foote , Bharath Rangarajan , Arvind Halliyal
IPC分类号： H01L218247
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42332 , Y10S438/954
摘要： A process for fabricating an ONO layer in a non-volatile memory device including the steps of forming a first silicon oxide layer, a silicon-rich silicon nitride layer and a second silicon oxide layer. The silicon-rich silicon nitride layer is formed by either a PECVD process, an LPCVD, or an RTCVD process. The silicon-rich silicon nitride layer effectively holds electrical charge making the ONO layer particularly useful as a floating gate electrode in a two-bit EEPROM device.
摘要翻译：一种用于在非易失性存储器件中制造ONO层的工艺，包括形成第一氧化硅层，富硅氮化硅层和第二氧化硅层的步骤。富硅氮化硅层通过PECVD工艺，LPCVD或RTCVD工艺形成。富含硅的氮化硅层有效地保持电荷，使得ONO层在二位EEPROM器件中作为浮栅电极特别有用。

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