专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06235587B1 Method of manufacturing a semiconductor device with reduced arc loss in peripheral circuitry region 有权
标题翻译：在外围电路区域制造具有减少的电弧损耗的半导体器件的方法
公开(公告)号：US06235587B1
公开(公告)日：2001-05-22
申请号：US09417131
申请日：1999-10-13
申请人： Tommy C. Hsaio , Mark T. Ramsbey , Yu Sun
发明人： Tommy C. Hsaio , Mark T. Ramsbey , Yu Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11526 , H01L27/11534 , H01L27/11543 , Y10S438/951
摘要： Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by reducing ARC loss during photoresist stripping associated with plural mask formation in the core memory cell region during patterning and ion implantations. Embodiments include sequentially etching the stacked gate electrode structure in the core memory cell region, photoresist stripping and etching to form the gate electrode structure in the peripheral circuitry region. Subsequently, plural maskings and ion implantations are implemented in the core memory cell region with attendant photoresist strippings.
摘要翻译：半导体器件的外围电路区域中的栅电极结构的改进的尺寸精度通过在图案化和离子注入期间减小与芯存储器单元区域中的多个掩模形成相关的光致抗蚀剂剥离期间的ARC损耗来实现。实施例包括在芯存储单元区域中依次蚀刻堆叠的栅极电极结构，光刻胶剥离和蚀刻以在外围电路区域中形成栅电极结构。随后，在核存储单元区域中实现多个掩模和离子注入，并附带光刻胶剥离。

22. 发明授权

US06197635B1 Method of manufacturing a semiconductor device with reduced masking and without ARC loss in peripheral circuitry region 有权
标题翻译：制造半导体器件的方法，该半导体器件在外围电路区域中具有减小的掩蔽并且没有ARC损耗
公开(公告)号：US06197635B1
公开(公告)日：2001-03-06
申请号：US09417130
申请日：1999-10-13
申请人： Tommy C. Hsaio , Mark T. Ramsbey , Yu Sun
发明人： Tommy C. Hsaio , Mark T. Ramsbey , Yu Sun
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by avoiding ARC loss during photoresist stripping associated with plural maskings in the core memory cell region during patterning and ion implantations. Processing is simplified by employing the same mask in the memory cell region for patterning the stacked gate electrode structure and for ion implanting the shallow source/drain extensions. Embodiments include initially etching to form the gate electrode structure in the peripheral circuitry region. Subsequently, processing in the core memory cell region is conducted by etching the stacked gate electrode structure and ion implanting to form the source/drains with attendant stripping of photoresist layers.
摘要翻译：半导体器件的外围电路区域中的栅电极结构的改进的尺寸精度通过在图案化和离子注入期间避免与芯存储器单元区域中的多个掩模相关联的光致抗蚀剂剥离期间的ARC损耗来实现。通过在存储单元区域中采用相同的掩模来简化处理，用于图案化堆叠的栅电极结构和用于离子注入浅源/漏扩展。实施例包括初始蚀刻以在外围电路区域中形成栅电极结构。随后，通过蚀刻堆叠的栅极电极结构和离子注入来进行核心存储单元区域中的处理，以形成具有光刻胶层的伴随剥离的源极/漏极。

23. 发明授权

US6001713A Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device 有权
标题翻译：在非易失性半导体存储器件中的浮栅和互聚电介质层中形成富氮区的方法
公开(公告)号：US6001713A
公开(公告)日：1999-12-14
申请号：US154074
申请日：1998-09-16
申请人： Mark T. Ramsbey , Vei-Han Chan , Sameer Haddad , Chi Chang , Yu Sun , Raymond Yu
发明人： Mark T. Ramsbey , Vei-Han Chan , Sameer Haddad , Chi Chang , Yu Sun , Raymond Yu
IPC分类号： H01L21/28 , H01L21/265
CPC分类号： H01L21/28273
摘要： Methods are provided for significantly reducing electron trapping in semiconductor devices having a floating gate and an overlying dielectric layer. The methods form a nitrogen-rich region within the floating gate near the interface to an overlying dielectric layer. The methods include selectively introducing nitrogen into the floating gate prior to forming the overlying dielectric layer. This forms an initial nitrogen concentration profile within the floating gate. An initial portion of the overlying dielectric layer is then formed of a high temperature oxide (HTO). The temperature within the floating gate is purposely raised to an adequately high temperature to cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards the interface with the overlying dielectric layer and an interface with an underlying layer. Consequently, the floating gate is left with a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The first nitrogen-rich region has been found to reduce electron trapping within the floating gate, which could lead to false programming of the floating gate. Unlike a conventional thermally grown oxide film, the high temperature oxide film within the interpoly dielectric layer advantageously prevents the surface of the floating gate from becoming too granular. As such, the resulting interpoly dielectric layer, which typically includes several films, can be formed more evenly.
摘要翻译：提供了用于显着减少具有浮置栅极和上覆电介质层的半导体器件中的电子俘获的方法。该方法在与上覆电介质层的界面附近的浮栅内形成富氮区。所述方法包括在形成上覆电介质层之前将氮气选择性地引入浮栅。这在浮动栅极内形成初始氮浓度分布。然后由上覆电介质层的初始部分由高温氧化物（HTO）形成。浮置栅极内的温度有意地升高到足够高的温度，以使得初始氮浓度分布由于大部分氮向与上覆介质层的界面的迁移以及与下层的界面而改变。因此，浮置栅极在与上覆电介质层的界面附近的第一富氮区域和与下层的界面附近的第二富氮区域留下。已经发现第一个富氮区域减少了浮动栅极内的电子俘获，这可能导致浮动栅极的错误编程。与传统的热生长氧化膜不同，多聚电介质层内的高温氧化膜有利地防止浮栅的表面变得太细。因此，可以更均匀地形成通常包括几个膜的所得到的互间介电层。

24. 发明授权

US5933730A Method of spacer formation and source protection after self-aligned source is formed and a device provided by such a method 失效
标题翻译：形成自对准源之后的间隔物形成和源保护的方法以及通过这种方法提供的装置
公开(公告)号：US5933730A
公开(公告)日：1999-08-03
申请号：US813562
申请日：1997-03-07
申请人： Yu Sun , Chi Chang , Mark T. Ramsbey
发明人： Yu Sun , Chi Chang , Mark T. Ramsbey
IPC分类号： H01L21/8247 , H01L27/105
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： The present invention provides a semiconductor device and a method for providing such a semiconductor device which allows a field oxide etch while minimizing the damage to the silicon. This method is particularly useful for smaller semiconductor devices, for example, such as a semiconductor device utilizing core source spacing less than 0.4 microns. A method according to the present invention for providing a semiconductor device comprises the steps of depositing a first spacer oxide layer over a core area and a peripheral area of a semiconductor device; etching the first spacer oxide layer at the source side of core cell area; depositing a second spacer oxide layer over the core area and the peripheral area, and etching the first and second spacer oxide layers over the peripheral area only.
摘要翻译：本发明提供了一种用于提供这种半导体器件的半导体器件和方法，其允许场氧化物蚀刻同时最小化对硅的损害。该方法对于较小的半导体器件特别有用，例如，诸如利用芯源间距小于0.4微米的半导体器件。根据本发明的用于提供半导体器件的方法包括以下步骤：在半导体器件的芯区域和周边区域上沉积第一间隔氧化物层; 在核心区域的源极处蚀刻第一间隔氧化物层; 在芯区域和外围区域上沉积第二间隔氧化物层，并且仅在周边区域上蚀刻第一和第二间隔氧化物层。

25. 发明授权

US06900085B2 ESD implant following spacer deposition 有权
标题翻译：间隔物沉积后的ESD植入
公开(公告)号：US06900085B2
公开(公告)日：2005-05-31
申请号：US09891885
申请日：2001-06-26
申请人： Mark T. Ramsbey , Michael Fliesler , Mark Randolph , Mimi Qian , Yu Sun
发明人： Mark T. Ramsbey , Michael Fliesler , Mark Randolph , Mimi Qian , Yu Sun
IPC分类号： H01L27/02 , H01L29/78 , H01L21/8234
CPC分类号： H01L29/7833 , H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： One aspect of the present invention provides a process for forming IC devices with ESD protection transistors. According to one aspect of the invention, an ESD protection transistor is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device.
摘要翻译：本发明的一个方面提供了一种用于形成具有ESD保护晶体管的IC器件的方法。根据本发明的一个方面，ESD保护晶体管具有轻掺杂，然后在形成间隔物之后，进行重掺杂。具有间隔物的重掺杂可以降低薄层电阻，增强晶体管的双极效应，降低晶体管的电容，并降低结击穿电压，而不会导致短沟道效应。因此，本发明提供了紧凑，高灵敏度和快速切换的ESD保护晶体管。间隔物可以与其他晶体管的间隔物同时形成，例如器件的外围区域中的其它晶体管。

26. 发明授权

US06645801B1 Salicided gate for virtual ground arrays 有权
标题翻译：用于虚拟地面阵列的闸门
公开(公告)号：US06645801B1
公开(公告)日：2003-11-11
申请号：US09968456
申请日：2001-10-01
申请人： Mark T. Ramsbey , Yu Sun , Chi Chang
发明人： Mark T. Ramsbey , Yu Sun , Chi Chang
IPC分类号： H01L218234
CPC分类号： H01L27/11568 , H01L21/76889 , H01L27/115
摘要： The present invention provides a process for saliciding the word lines in a virtual ground array flash memory device without saliciding the substrate between word lines. According to the invention, in a process for manufacturing virtual ground array flash memory devices, a salicide protect layer covers the substrate between word lines in the core region while the tops of the word lines are exposed. The salicide protect layer can be brought into the desired configuration by one or more of masking the substrate between word lines during an etching process, removing salicide protection material in the core by polishing, and forming a comparatively thick layer of salicide protection material in the core whereby the tendency of the salicide protect layer to follow the contour of the underlying structures is reduced. With the substrate between word lines protected by the salicide protect layer, the word lines are salicided. The process of the invention produces virtual ground array flash memory devices with salicided word lines, but without shorting between bit lines.
摘要翻译：本发明提供了一种在虚拟接地阵列闪存器件中对字线进行水印处理，而不会在字线之间对基片进行浸蚀。根据本发明，在虚拟接地阵列闪速存储器件的制造工艺中，当暴露出字线的顶部时，自对准保护层在芯部区域中的字线之间覆盖衬底。可以通过在蚀刻工艺期间在字线之间掩蔽衬底的一种或多种来将所述自对准保护层带入所需的构型，通过抛光去除芯中的自对准保护材料，以及在芯中形成比较厚的自对准保护材料层从而降低了防自杀剂保护层跟随下面结构轮廓的趋势。在由自对准保护层保护的字线之间的衬底上，字线被浸渍。本发明的方法产生具有带字线的虚拟接地阵列闪存器件，但是在位线之间没有短路。

27. 发明授权

US06509604B1 Nitridation barriers for nitridated tunnel oxide for circuitry for flash technology and for LOCOS/STI isolation 失效
标题翻译：用于闪存技术和LOCOS / STI隔离电路的氮化隧道氧化物的氮化屏障
公开(公告)号：US06509604B1
公开(公告)日：2003-01-21
申请号：US09491457
申请日：2000-01-26
申请人： Tuan Duc Pham , Mark T. Ramsbey , Yu Sun , Chi Chang
发明人： Tuan Duc Pham , Mark T. Ramsbey , Yu Sun , Chi Chang
IPC分类号： H01L29788
CPC分类号： H01L21/76202 , H01L21/76224 , H01L27/1052 , Y10S438/981
摘要： A semiconductor chip having a plurality of flash memory devices, shallow trench isolation in the periphery region, and LOCOS isolation in the core region. A hard mask is used first to create the shallow trench isolation. The LOCOS isolation is then created. Subsequent etching is used to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide barrier layer. A hard mask is used to prevent nitride contamination of the gate oxide layer.
摘要翻译：具有多个闪速存储器件的半导体芯片，周边区域中的浅沟槽隔离以及芯区域中的LOCOS隔离。首先使用硬掩模来创建浅沟槽隔离。然后创建LOCOS隔离。随后的蚀刻用于去除桁条。闪存能够使用浅沟槽隔离来限制侵占。闪存也可以具有氮化的隧道氧化物阻挡层。使用硬掩模来防止栅极氧化物层的氮化物污染。

28. 发明授权

US06475847B1 Method for forming a semiconductor device with self-aligned contacts using a liner oxide layer 有权
标题翻译：使用衬垫氧化物层形成具有自对准触点的半导体器件的方法
公开(公告)号：US06475847B1
公开(公告)日：2002-11-05
申请号：US10109526
申请日：2002-03-27
申请人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
发明人： Minh Van Ngo , Yu Sun , Fei Wang , Mark T. Ramsbey , Chi Chang , Angela T. Hui , Mark S. Chang
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L21/76829 , H01L21/76897 , H01L27/115 , H01L2924/3011
摘要： A method for shrinking a semiconductor device and minimizing auto-doping problem is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.
摘要翻译：公开了一种缩小半导体器件并最小化自动掺杂问题的方法。蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。衬垫氧化物层直接形成在衬底上并与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触，并且用作电介质层的自动掺杂势垒，以防止形成在衬底中的硼和磷电介质层自动掺入源和漏极。

29. 发明授权

US5966618A Method of forming dual field isolation structures 失效
标题翻译：形成双场隔离结构的方法
公开(公告)号：US5966618A
公开(公告)日：1999-10-12
申请号：US36288
申请日：1998-03-06
申请人： Yu Sun , Tuan D. Pham , Mark T. Ramsbey , Chi Chang
发明人： Yu Sun , Tuan D. Pham , Mark T. Ramsbey , Chi Chang
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762 , H01L27/08 , H01L27/105
CPC分类号： H01L21/76221 , H01L27/105
摘要： A method of providing thick and thin oxide structures reduces step changes between a core region and a peripheral region on an integrated circuit. Thin LOCOS structures are provided in a core region of a flash memory device, and thick LOCOS structures are provided in a peripheral region of the flash memory device. The device and process are not as susceptible to "race track" problems, "oxide" bump problems, and "stringer" problems. The process utilizes two separate nitride or hard mask layers.
摘要翻译：提供厚且薄的氧化物结构的方法减小了集成电路上的芯区域和周边区域之间的阶跃变化。在闪速存储器件的核心区域中提供了薄的LOCOS结构，并且在闪速存储器件的外围区域中提供了厚的LOCOS结构。设备和过程不容易受到“赛道”问题，“氧化物”碰撞问题和“纵梁”问题的影响。该方法利用两个分开的氮化物或硬掩模层。

30. 发明授权

US07432178B2 Bit line implant 有权
标题翻译：位线植入
公开(公告)号：US07432178B2
公开(公告)日：2008-10-07
申请号：US11254769
申请日：2005-10-21
申请人： Angela T. Hui , Jean Yang , Yu Sun , Mark T. Ramsbey , Weidong Qian
发明人： Angela T. Hui , Jean Yang , Yu Sun , Mark T. Ramsbey , Weidong Qian
IPC分类号： H01L21/04
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.
摘要翻译：公开了一种用于执行位线植入的方法。该方法包括在半导体器件的氧化物 - 氮化物 - 氧化物堆叠上形成一组结构。该组结构的每个结构包括多晶硅部分和硬掩模部分。该组结构的第一结构与该组结构的第二结构分开小于100纳米。该方法还包括使用第一结构和第二结构来隔离位线植入物的半导体器件的一部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式