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21. 发明申请

US20160315164A1 SEMICONDUCTOR DEVICES INCLUDING A RARE EARTH ELEMENT AND METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING A RARE EARTH ELEMENT 有权
标题翻译：包括稀土元素的半导体器件和形成包含稀土元素的半导体器件的方法
公开(公告)号：US20160315164A1
公开(公告)日：2016-10-27
申请号：US15048797
申请日：2016-02-19
申请人： Hyeok-jun Son , Wan-don Kim , Hoon-joo Na , Sang-jin Hyun , Yoon-tae Hwang , Jae-yeol Song
发明人： Hyeok-jun Son , Wan-don Kim , Hoon-joo Na , Sang-jin Hyun , Yoon-tae Hwang , Jae-yeol Song
IPC分类号： H01L29/49 , H01L29/423 , H01L29/51 , H01L29/78
CPC分类号： H01L29/4958 , H01L29/513 , H01L29/517 , H01L29/7851
摘要： Semiconductor devices are provided. A semiconductor device includes an insulating layer. The semiconductor device includes a rare earth element supply layer on the insulating layer. Moreover, the semiconductor device includes a metal layer that is on the rare earth element supply layer. The rare earth element supply layer is between the insulating layer and the metal layer. Methods of forming semiconductor devices are also provided.
摘要翻译：提供半导体器件。半导体器件包括绝缘层。半导体器件包括在绝缘层上的稀土元素供给层。此外，半导体器件包括在稀土元素供给层上的金属层。稀土元素供给层位于绝缘层与金属层之间。还提供了形成半导体器件的方法。

22. 发明授权

US07700454B2 Methods of forming integrated circuit electrodes and capacitors by wrinkling a layer that includes a high percentage of impurities 有权
标题翻译：通过起皱包含高比例杂质的层来形成集成电路电极和电容器的方法
公开(公告)号：US07700454B2
公开(公告)日：2010-04-20
申请号：US11462178
申请日：2006-08-03
申请人： Wan-don Kim , Jae-hyun Joo , Seok-jun Won , Jung-hee Chung , Jin-yong Kim , Suk-jin Chung
发明人： Wan-don Kim , Jae-hyun Joo , Seok-jun Won , Jung-hee Chung , Jin-yong Kim , Suk-jin Chung
IPC分类号： H01L21/20
CPC分类号： H01L28/84 , H01L27/1085
摘要： A method of fabricating a uniformly wrinkled capacitor lower electrode without the need to perform a high-temperature heat treatment and a method of fabricating a capacitor including the uniformly wrinkled capacitor lower electrode are provided. A first conductive layer is formed. Then, a second conductive layer including about 20% to about 50% of impurities is formed on the first conductive layer. Next, at least some of the impurities are exhausted from the second conductive layer by heat treating the second conductive layer. A surface of the second conductive layer is wrinkled due to the exhaustion of the impurities from the second conductive layer. A dielectric layer and an upper capacitor electrode may then be formed.
摘要翻译：提供一种制造均匀起皱的电容器下电极而不需要进行高温热处理的方法，以及制造包括均匀起皱的电容器下电极的电容器的方法。形成第一导电层。然后，在第一导电层上形成包含约20％至约50％的杂质的第二导电层。接下来，通过热处理第二导电层，至少一些杂质从第二导电层排出。由于来自第二导电层的杂质的耗尽，第二导电层的表面起皱。然后可以形成电介质层和上电容器电极。

23. 发明授权

US08859383B2 Method of fabricating semiconductor device having dielectric layer with improved electrical characteristics 有权
标题翻译：制造具有改善的电特性的具有电介质层的半导体器件的方法
公开(公告)号：US08859383B2
公开(公告)日：2014-10-14
申请号：US13424825
申请日：2012-03-20
申请人： Youn-soo Kim , Jae-hyoung Choi , Kyu-ho Cho , Wan-don Kim , Jae-soon Lim , Sang-yeol Kang
发明人： Youn-soo Kim , Jae-hyoung Choi , Kyu-ho Cho , Wan-don Kim , Jae-soon Lim , Sang-yeol Kang
IPC分类号： H01L21/20 , H01L49/02 , H01L21/02 , H01L21/316 , H01L21/318 , H01L27/108
CPC分类号： H01L28/56 , H01L21/02189 , H01L21/022 , H01L21/02244 , H01L21/02247 , H01L21/31683 , H01L21/318 , H01L27/1085 , H01L28/40 , H01L28/75
摘要： A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.
摘要翻译：一种半导体器件，具有具有改善的电特性和相关方法的电介质层，所述半导体器件包括顺序地设置在半导体衬底上的下金属层，电介质层和上金属层，以及设置在电介质层之间的插入层下金属层和上金属层中的至少一个，其中电介质层包括金属氧化物膜，并且插入层包括金属材料膜。

24. 发明申请

US20090072350A1 SEMICONDUCTOR DEVICES HAVING A CONTACT PLUG AND FABRICATION METHODS THEREOF 有权
标题翻译：具有接触插头的半导体器件及其制造方法
公开(公告)号：US20090072350A1
公开(公告)日：2009-03-19
申请号：US12270286
申请日：2008-11-13
申请人： Wan-don Kim , Jin-yong Kim , Yong-suk Tak , Jung-hee Chung , Ki-chul Kim , Oh-seong Kwon
发明人： Wan-don Kim , Jin-yong Kim , Yong-suk Tak , Jung-hee Chung , Ki-chul Kim , Oh-seong Kwon
IPC分类号： H01L29/92 , H01L21/20
CPC分类号： H01L28/91 , H01L27/10855 , H01L28/60
摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括形成在支撑层上并具有接触孔的绝缘层。第一接触塞形成在接触孔的内壁和底部上。第二接触插塞将接触孔埋入并形成在第一接触插塞上。导电层连接到第一接触插塞和第二接触插塞。形成在接触孔底部的第一接触塞的底部厚度比形成在接触孔的内壁上的第一接触塞的内壁厚度大。

25. 发明授权

US09793368B2 Semiconductor devices including a rare earth element and methods of forming semiconductor devices including a rare earth element 有权
公开(公告)号：US09793368B2
公开(公告)日：2017-10-17
申请号：US15048797
申请日：2016-02-19
申请人： Hyeok-jun Son , Wan-don Kim , Hoon-joo Na , Sang-jin Hyun , Yoon-tae Hwang , Jae-yeol Song
发明人： Hyeok-jun Son , Wan-don Kim , Hoon-joo Na , Sang-jin Hyun , Yoon-tae Hwang , Jae-yeol Song
IPC分类号： H01L29/49 , H01L29/78 , H01L29/51
CPC分类号： H01L29/4958 , H01L29/513 , H01L29/517 , H01L29/7851
摘要： Semiconductor devices are provided. A semiconductor device includes an insulating layer. The semiconductor device includes a rare earth element supply layer on the insulating layer. Moreover, the semiconductor device includes a metal layer that is on the rare earth element supply layer. The rare earth element supply layer is between the insulating layer and the metal layer. Methods of forming semiconductor devices are also provided.

26. 发明申请

US20160308012A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160308012A1
公开(公告)日：2016-10-20
申请号：US15059673
申请日：2016-03-03
申请人： Jae-yeol Song , Wan-don Kim , Sang-jin Hyun , Jin-wook Lee , Kee-sang Kwon , Ki-hyung Ko , Sung-woo Myung
发明人： Jae-yeol Song , Wan-don Kim , Sang-jin Hyun , Jin-wook Lee , Kee-sang Kwon , Ki-hyung Ko , Sung-woo Myung
IPC分类号： H01L29/423 , H01L27/088 , H01L29/78
CPC分类号： H01L29/42376 , H01L21/28088 , H01L21/823431 , H01L21/823456 , H01L27/0886 , H01L27/0924 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.
摘要翻译：在包括具有相对窄的宽度和相对较小的间距的栅极线的半导体器件和制造该半导体器件的方法中，所述半导体器件包括具有鳍式有源区的衬底，覆盖上表面的栅极绝缘层翅片型有源区的侧面以及覆盖翅片型有源区的上表面和两侧的鳍型有源区延伸并相交的栅极线，栅极线位于栅极绝缘层上其特征在于，所述栅极线的上表面的与所述栅极线的延伸方向垂直的截面的中心部分具有凹形。

27. 发明授权

US06500763B2 Method for manufacturing an electrode of a capacitor 失效
标题翻译：制造电容器电极的方法
公开(公告)号：US06500763B2
公开(公告)日：2002-12-31
申请号：US09735901
申请日：2000-12-14
申请人： Jin-won Kim , Sang-don Nam , Wan-don Kim , Kab-jin Nam
发明人： Jin-won Kim , Sang-don Nam , Wan-don Kim , Kab-jin Nam
IPC分类号： H01L21302
CPC分类号： H01L28/91 , H01L21/31111 , H01L21/31116 , H01L21/31122
摘要： A method for manufacturing an electrode of a capacitor used in a semiconductor device, wherein a support insulating layer, an etch stop layer including a tantalum oxide layer, and a mold sacrificial insulating layer are sequentially formed on a semiconductor substrate. The mold sacrificial insulating layer, the etch stop layer and the support insulating layer are sequentially patterned to form a three-dimensional mold for a storage node. A storage node layer is formed to cover the inner surface of the mold. Next, storage nodes for capacitors are formed by dividing the storage node layer. The residual mold sacrificial insulating layer is removed by selectively wet etching, using the tantalum oxide layer as an etch stopper.
摘要翻译：在半导体器件中制造用于电容器的电极的方法，其中在半导体衬底上依次形成支撑绝缘层，包括氧化钽层的蚀刻停止层和模具牺牲绝缘层。模具牺牲绝缘层，蚀刻停止层和支撑绝缘层被顺序地图案化以形成用于存储节点的三维模具。形成存储节点层以覆盖模具的内表面。接下来，通过划分存储节点层来形成用于电容器的存储节点。通过使用氧化钽层作为蚀刻停止器，通过选择性湿法蚀刻除去残余模具牺牲绝缘层。

28. 发明申请

US20120178254A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING DIELECTRIC LAYER WITH IMPROVED ELECTRICAL CHARACTERISTICS 有权
标题翻译：具有改进电气特性的具有电介质层的半导体器件的制造方法
公开(公告)号：US20120178254A1
公开(公告)日：2012-07-12
申请号：US13424825
申请日：2012-03-20
申请人： Youn-soo KIM , Jae-hyoung Choi , Kyu-ho Cho , Wan-don Kim , Jae-soon Lim , Sang-yeol Kang
发明人： Youn-soo KIM , Jae-hyoung Choi , Kyu-ho Cho , Wan-don Kim , Jae-soon Lim , Sang-yeol Kang
IPC分类号： H01L21/3205
CPC分类号： H01L28/56 , H01L21/02189 , H01L21/022 , H01L21/02244 , H01L21/02247 , H01L21/31683 , H01L21/318 , H01L27/1085 , H01L28/40 , H01L28/75
摘要： A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.
摘要翻译：一种半导体器件，具有具有改善的电特性和相关方法的电介质层，所述半导体器件包括顺序地设置在半导体衬底上的下金属层，电介质层和上金属层，以及设置在电介质层之间的插入层下金属层和上金属层中的至少一个，其中电介质层包括金属氧化物膜，并且插入层包括金属材料膜。

29. 发明授权

US07781819B2 Semiconductor devices having a contact plug and fabrication methods thereof 有权
标题翻译：具有接触塞的半导体器件及其制造方法
公开(公告)号：US07781819B2
公开(公告)日：2010-08-24
申请号：US12270286
申请日：2008-11-13
申请人： Wan-don Kim , Jin-yong Kim , Yong-suk Tak , Jung-hee Chung , Ki-chul Kim , Oh-seong Kwon
发明人： Wan-don Kim , Jin-yong Kim , Yong-suk Tak , Jung-hee Chung , Ki-chul Kim , Oh-seong Kwon
IPC分类号： H01L29/92
CPC分类号： H01L28/91 , H01L27/10855 , H01L28/60
摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole.
摘要翻译：提供半导体器件及其制造方法。半导体器件包括形成在支撑层上并具有接触孔的绝缘层。第一接触塞形成在接触孔的内壁和底部上。第二接触插塞将接触孔埋入并形成在第一接触插塞上。导电层连接到第一接触插塞和第二接触插塞。形成在接触孔底部的第一接触塞的底部厚度比形成在接触孔的内壁上的第一接触塞的内壁厚度大。

30. 发明申请

US20100200950A1 Semiconductor device having dielectric layer with improved electrical characteristics and associated methods 审中-公开
标题翻译：具有具有改善的电气特性和相关方法的介电层的半导体器件
公开(公告)号：US20100200950A1
公开(公告)日：2010-08-12
申请号：US12585030
申请日：2009-09-01
申请人： Youn-soo Kim , Jae-hyoung Choi , Kyu-ho Cho , Wan-don Kim , Jae-soon Lim , Sang-yeol Kang
发明人： Youn-soo Kim , Jae-hyoung Choi , Kyu-ho Cho , Wan-don Kim , Jae-soon Lim , Sang-yeol Kang
IPC分类号： H01L29/92
CPC分类号： H01L28/56 , H01L21/02189 , H01L21/022 , H01L21/02244 , H01L21/02247 , H01L21/31683 , H01L21/318 , H01L27/1085 , H01L28/40 , H01L28/75
摘要： A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.
摘要翻译：一种半导体器件，具有具有改善的电特性和相关方法的电介质层，所述半导体器件包括顺序地设置在半导体衬底上的下金属层，电介质层和上金属层，以及设置在电介质层之间的插入层下金属层和上金属层中的至少一个，其中电介质层包括金属氧化物膜，并且插入层包括金属材料膜。

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