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1. 发明授权

US07973352B2 Capacitors having composite dielectric layers containing crystallization inhibiting regions 有权
标题翻译：具有包含结晶抑制区域的复合电介质层的电容器
公开(公告)号：US07973352B2
公开(公告)日：2011-07-05
申请号：US12754713
申请日：2010-04-06
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
IPC分类号： H01L29/94
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
摘要翻译：集成电路电容器在其中具有复合电介质层。这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

2. 发明授权

US07723770B2 Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions 有权
标题翻译：集成电路电容器，其中包含结晶抑制区的复合介电层
公开(公告)号：US07723770B2
公开(公告)日：2010-05-25
申请号：US11210332
申请日：2005-08-24
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Young-sun Kim , Se-hoon Oh
IPC分类号： H01L27/108
CPC分类号： H01L29/92 , H01L27/10852 , H01L28/40
摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.
摘要翻译：集成电路电容器在其中具有复合电介质层。这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

3. 发明申请

US20100117194A1 METAL-INSULATOR-METAL CAPACITORS WITH A CHEMICAL BARRIER LAYER IN A LOWER ELECTRODE 审中-公开
标题翻译：金属绝缘体 - 金属电容器，在较低的电极中具有化学障碍层
公开(公告)号：US20100117194A1
公开(公告)日：2010-05-13
申请号：US12639184
申请日：2009-12-16
申请人： Eun-ae Chung , Jae-hyoung Choi , Jung-hee Chung , Young-sun Kim , Cha-young Yoo
发明人： Eun-ae Chung , Jae-hyoung Choi , Jung-hee Chung , Young-sun Kim , Cha-young Yoo
IPC分类号： H01L29/92 , H01G4/06 , H01G4/008
CPC分类号： H01L21/7687 , H01L27/10852 , H01L28/65 , H01L28/75
摘要： A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.
摘要翻译：金属绝缘体金属（MIM）电容器包括下电极，电介质层和上电极。下电极包括第一导电层，第一导电层上的化学阻挡层和化学阻挡层上的第二导电层。化学屏障层位于第一和第二导电层之间，并且是与第一和第二导电层不同的材料。介电层位于下电极上。上电极位于与下电极相对的电介质层上。第一和第二导电层可以具有相同的厚度。化学阻挡层可以比第一和第二导电层中的每一个薄。讨论相关方法。

4. 发明授权

US07422943B2 Semiconductor device capacitors with oxide-nitride layers and methods of fabricating such capacitors 有权
标题翻译：具有氧化物氮化物层的半导体器件电容器和制造这种电容器的方法
公开(公告)号：US07422943B2
公开(公告)日：2008-09-09
申请号：US11386660
申请日：2006-03-22
申请人： Jong-cheol Lee , Young-sun Kim , Jung-hee Chung , Jae-hyoung Choi , Se-hoon Oh , Hong-bum Park
发明人： Jong-cheol Lee , Young-sun Kim , Jung-hee Chung , Jae-hyoung Choi , Se-hoon Oh , Hong-bum Park
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/75
摘要： Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is oxidized and/or at least part of the dielectric layer is nitridized.
摘要翻译：提供具有包括下电极，电介质层和包括导电金属氮化物层和掺杂多晶硅锗层的上电极的上电极的电容器。导电金属氮化物层的至少一部分被氧化和/或至少部分介电层被氮化。

5. 发明授权

US07304367B2 Metal-insulator-metal capacitors including transition metal silicide films on doped polysilicon contact plugs 有权
标题翻译：金属绝缘体金属电容器，包括掺杂多晶硅接触插头上的过渡金属硅化物膜
公开(公告)号：US07304367B2
公开(公告)日：2007-12-04
申请号：US10870745
申请日：2004-06-17
申请人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Nam-myun Cho , Jeong-sik Choi , Se-hoon Oh , Dong-kyun Park
发明人： Jae-hyoung Choi , Jung-hee Chung , Cha-young Yoo , Nam-myun Cho , Jeong-sik Choi , Se-hoon Oh , Dong-kyun Park
IPC分类号： H01L29/00
CPC分类号： H01L28/91
摘要： A MIM capacitor can include a doped polysilicon contact plug in an interlayer insulating film. A lower electrode of the MIM capacitor includes a transition metal nitride film is on the doped polysilicon contact plug. A transition metal silicide film is between the doped polysilicon contact plug and the transition metal nitride film.
摘要翻译： MIM电容器可以包括层间绝缘膜中的掺杂多晶硅接触插塞。 MIM电容器的下电极包括在掺杂多晶硅接触插塞上的过渡金属氮化物膜。过渡金属硅化物膜位于掺杂多晶硅接触插塞和过渡金属氮化物膜之间。

6. 发明申请

US20070099379A1 Method of manufacturing a dielectric film in a capacitor 失效
标题翻译：制造电容器中的电介质膜的方法
公开(公告)号：US20070099379A1
公开(公告)日：2007-05-03
申请号：US11544760
申请日：2006-10-10
申请人： Jae-hyoung Choi , Sung-ho Kang , Jung-hee Chung , Seog-min Lee , Jong-bom Seo , Young-min Kim
发明人： Jae-hyoung Choi , Sung-ho Kang , Jung-hee Chung , Seog-min Lee , Jong-bom Seo , Young-min Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/0228 , C23C16/405 , C23C16/45527 , H01L21/02175 , H01L21/3141 , H01L21/31645 , H01L28/40
摘要： A method of manufacturing a dielectric layer for a capacitor including sequentially supplying and purging a first and a second precursor material for a first and a second predetermined amount of time, respectively, in an initial cycle, sequentially supplying and purging the first and the second precursor materials for a third predetermined amount of time, which is shorter than the first and/or second predetermined amount of time, in a post cycle, which follows the initial cycle, and repeating the initial and post cycles to form a dielectric layer having a predetermined thickness.
摘要翻译：一种电容器用电介质层的制造方法，其特征在于，在初始循环中分别顺序地供给和吹扫第一和第二前体材料，分别第一和第二预定量的时间，依次供给和净化所述第一和第二前体在后循环中第三预定时间量的材料，其比第一和/或第二预定量的时间短，其在初始循环之后，并且重复初始和后期循环以形成具有预定的厚度。

7. 发明授权

US07049232B2 Methods for forming ruthenium films with β-diketone containing ruthenium complexes and method for manufacturing metal-insulator-metal capacitor using the same 有权
公开(公告)号：US07049232B2
公开(公告)日：2006-05-23
申请号：US10657596
申请日：2003-09-08
申请人： Kwang-hee Lee , Cha-young Yoo , Han-jin Lim , Sung-tae Kim , Suk-jin Chung , Wan-don Kim , Jung-hee Chung , Jin-il Lee
发明人： Kwang-hee Lee , Cha-young Yoo , Han-jin Lim , Sung-tae Kim , Suk-jin Chung , Wan-don Kim , Jung-hee Chung , Jin-il Lee
IPC分类号： H01L21/44
CPC分类号： C23C16/18 , H01L21/28556 , H01L27/10852 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： Provided are 1) a method for forming a ruthenium film under a single process condition, whereby high adhesion of the ruthenium film to a lower layer is maintained, and 2) a method for manufacturing an metal-insulator-metal (MIM) capacitor using the ruthenium film forming method. The method for forming a ruthenium film includes supplying bis(isoheptane-2,4-dionato)norbornadiene ruthenium at a flow rate of 0.2–1 ccm and oxygen at a flow rate of 20–60 sccm, and depositing the ruthenium film at a temperature of 330–430° C. under a pressure of 0.5–5 Torr using chemical vapor deposition (CVD).

8. 发明申请

US20060099760A1 Storage capacitors for semiconductor devices and methods of forming the same 有权
标题翻译：用于半导体器件的存储电容器及其形成方法
公开(公告)号：US20060099760A1
公开(公告)日：2006-05-11
申请号：US11266520
申请日：2005-11-03
申请人： Rak-Hwan Kim , Young-Joo Cho , Sung-Tae Kim , In-Sun Park , Hyeon-Deok Lee , Hyun-Suk Lee , Jung-Hee Chung , Hyun-Young Kim , Hyun-Seok Lim
发明人： Rak-Hwan Kim , Young-Joo Cho , Sung-Tae Kim , In-Sun Park , Hyeon-Deok Lee , Hyun-Suk Lee , Jung-Hee Chung , Hyun-Young Kim , Hyun-Seok Lim
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/75
摘要： Methods of forming a storage capacitor include forming an interlayer insulation layer having an opening therethrough on a semiconductor substrate, forming a contact plug in the opening, forming a molding oxide layer on the interlayer insulation layer and the contact plug, selectively removing portions of the molding oxide layer to form a recess above the contact plug, forming a titanium layer on a bottom surface and side surfaces of the recess, forming a titanium nitride layer on the titanium layer, and forming a titanium oxide nitride layer on the titanium nitride layer. A storage capacitor includes a semiconductor substrate, an interlayer insulation layer having a contact plug therein on the substrate, and a storage electrode on the contact plug including a titanium silicide layer, a titanium nitride layer on the titanium silicide layer, and a titanium oxide nitride layer on the titanium nitride layer.
摘要翻译：形成存储电容器的方法包括在半导体衬底上形成具有开口的层间绝缘层，在开口中形成接触插塞，在层间绝缘层和接触插塞上形成模压氧化层，选择性地去除模制件的部分在接触塞上方形成凹部，在凹部的底面和侧面形成钛层，在钛层上形成氮化钛层，在氮化钛层上形成氮化钛层。存储电容器包括半导体衬底，在衬底上具有接触插塞的层间绝缘层，以及包括钛硅化物层的接触插塞上的存储电极，硅化钛层上的氮化钛层和氧化钛氮化物层在氮化钛层上。

9. 发明授权

US06995071B2 Methods of forming MIM type capacitor structures using low temperature plasma processing 有权
标题翻译：使用低温等离子体处理形成MIM型电容器结构的方法
公开(公告)号：US06995071B2
公开(公告)日：2006-02-07
申请号：US10830214
申请日：2004-04-22
申请人： Se-hoon Oh , Jung-hee Chung , Jae-hyoung Choi , Jeong-sik Choi , Sung-tae Kim , Cha-young Yoo
发明人： Se-hoon Oh , Jung-hee Chung , Jae-hyoung Choi , Jeong-sik Choi , Sung-tae Kim , Cha-young Yoo
IPC分类号： H10L21/8242
CPC分类号： H01L27/10852 , C23C16/405 , C23C16/56 , H01L21/02181 , H01L21/0228 , H01L21/0234 , H01L21/02356 , H01L21/31645 , H01L27/10817 , H01L27/10855 , H01L28/91 , Y10S438/957
摘要： Methods of forming metal-insulator-metal type capacitors in integrated circuit memory devices can include crystallizing an HfO2 dielectric layer on a lower electrode of a capacitor structure in a low temperature plasma treatment at a temperature in range between about 250 degrees Centigrade and about 450 degrees Centigrade. An upper electrode can be formed on the HfO2 dielectric layer.
摘要翻译：在集成电路存储器件中形成金属 - 绝缘体 - 金属型电容器的方法可以包括在低温等离子体处理中在电容器结构的下部电极上结晶HfO 2/2电介质层，温度范围为约250摄氏度和约450摄氏度。上电极可以形成在HfO 2 2电介质层上。

10. 发明授权

US08481398B2 Method of forming semiconductor device having a capacitor 有权
标题翻译：形成具有电容器的半导体器件的方法
公开(公告)号：US08481398B2
公开(公告)日：2013-07-09
申请号：US12659548
申请日：2010-03-12
申请人： Seung-Sik Chung , Jung-Hee Chung , Young-Jin Kim , Seok-Woo Nam , Han-Jin Lim , Kyoung-Ryul Yoon
发明人： Seung-Sik Chung , Jung-Hee Chung , Young-Jin Kim , Seok-Woo Nam , Han-Jin Lim , Kyoung-Ryul Yoon
IPC分类号： H01L21/20
CPC分类号： H01L27/10852 , H01L27/10814 , H01L28/91
摘要： A method of forming a semiconductor device includes forming a lower electrode layer on a substrate, forming a surface oxide layer on the lower electrode layer, partially removing the lower electrode layer to form a lower electrode, removing the surface oxide layer to expose the lower electrode, forming a capacitor dielectric layer on the lower electrode, and forming an upper electrode on the capacitor dielectric layer.
摘要翻译：形成半导体器件的方法包括在衬底上形成下电极层，在下电极层上形成表面氧化层，部分地去除下电极层以形成下电极，去除表面氧化层以暴露下电极在下电极上形成电容器电介质层，并在电容器介电层上形成上电极。

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