专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20060131743A1 Changing chip function based on fuse states 有权
标题翻译：基于保险丝状态改变芯片功能
公开(公告)号：US20060131743A1
公开(公告)日：2006-06-22
申请号：US11016220
申请日：2004-12-17
申请人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
发明人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
IPC分类号： H01L23/48
CPC分类号： G06F21/71
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
摘要翻译：提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。可以基于存储在诸如电可编程融合（eFUSES）的非易失性存储元件中的值来提供操作和/或访问。

22. 发明申请

US20060108662A1 AN ELECTRICALLY PROGRAMMABLE FUSE FOR SILICON-ON-INSULATOR (SOI) TECHNOLOGY 有权
标题翻译：一种用于硅绝缘体（SOI）技术的电可编程保险丝
公开(公告)号：US20060108662A1
公开(公告)日：2006-05-25
申请号：US10904681
申请日：2004-11-23
申请人： Chandrasekharan Kothandaraman , Edward Maciejewski
发明人： Chandrasekharan Kothandaraman , Edward Maciejewski
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is preferably a material that minimizes stresses on the crystalline body, such as an oxide. The body may be doped, and may also include a silicide layer on the upper surface. This fuse structure may be successfully programmed over a wide range of programming voltages and time.
摘要翻译：描述了一种熔丝结构及其形成方法，其中熔丝的主体由绝缘体上的结晶半导体本体形成，绝缘体优选由绝缘体上硅晶片，被填充电介质环绕。填充电介质优选是使结晶体（例如氧化物）上的应力最小化的材料。主体可以被掺杂，并且还可以在上表面上包括硅化物层。这种熔丝结构可以在广泛的编程电压和时间范围内成功编程。

23. 发明申请

US20050167728A1 Single-poly 2-transistor based fuse element 失效
标题翻译：单聚二极管保险丝元件
公开(公告)号：US20050167728A1
公开(公告)日：2005-08-04
申请号：US10769101
申请日：2004-01-29
申请人： Chandrasekharan Kothandaraman , Danny Shum
发明人： Chandrasekharan Kothandaraman , Danny Shum
IPC分类号： G11C16/04 , G11C29/00 , H01L21/336 , H01L23/525 , H01L27/115 , H01L29/788 , H01L29/76
CPC分类号： H01L27/115 , G11C16/0433 , G11C29/789 , G11C2216/10 , H01L23/5256 , H01L29/66825 , H01L29/7885 , H01L2924/0002 , H01L2924/00
摘要： An electrically programmable transistor fuse having a double-gate arrangement disposed in a single layer of polysilicon in which a first gate is disposed overlapping a portion of a source region and a second gate is insulated from the first gate and disposed overlapping a portion of a drain region. The first gate includes a terminal for receiving an externally applied control signal and the second gate is capacitively couple to the drain region in which a coupling device is included for increasing the capacitive coupling of the second gate and the drain region for enabling reduction in fuse programming voltage.
摘要翻译：具有设置在单层多晶硅中的双栅极布置的电可编程晶体管熔丝，其中第一栅极被布置成与源极区域的一部分重叠并且第二栅极与第一栅极绝缘，并且与漏极的一部分重叠地区。第一栅极包括用于接收外部施加的控制信号的端子，并且第二栅极电容耦合到其中包括耦合装置的漏极区域，以增加第二栅极和漏极区域的电容耦合，以便能够减少熔丝编程电压。

24. 发明授权

US06828652B2 Fuse structure for semiconductor device 有权
标题翻译：半导体器件的保险丝结构
公开(公告)号：US06828652B2
公开(公告)日：2004-12-07
申请号：US10140592
申请日：2002-05-07
申请人： Chandrasekharan Kothandaraman
发明人： Chandrasekharan Kothandaraman
IPC分类号： H01L2900
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure (30) formed in a semiconductor device is provided. The fuse structure (30) includes a layer of fuse material (32), a first contact (40), and a second contact (42). The first contact (40) has a first edge (54). At least a portion of the first edge (54) abuts the fuse material layer (32). The second contact (42) has a second edge (55). At least a portion of the second edge (55) abuts the fuse material layer (32). The first edge (54) faces the second edge (55). The first edge (54) is separated from the second edge (55) by a spaced distance (58). A conductive portion of the fuse material layer (32) electrically connects between the first edge (54) and the second edge (55) within the spaced distance (58). The abutting portion of the first edge (54) has a first length. The abutting portion of the second edge (55) has a second length. The first length is greater than the second length.
摘要翻译：提供形成在半导体器件中的熔丝结构（30）。熔丝结构（30）包括一层熔丝材料（32），一个第一触点（40）和一个第二触点（42）。第一触点（40）具有第一边缘（54）。第一边缘（54）的至少一部分邻接熔丝材料层（32）。第二触点（42）具有第二边缘（55）。第二边缘（55）的至少一部分邻接熔丝材料层（32）。第一边缘（54）面向第二边缘（55）。第一边缘（54）与第二边缘（55）分开一段距离（58）。熔丝材料层（32）的导电部分在间隔距离（58）内在第一边缘（54）和第二边缘（55）之间电连接。第一边缘（54）的邻接部分具有第一长度。第二边缘（55）的邻接部分具有第二长度。第一长度大于第二长度。

25. 发明授权

US06432760B1 Method and structure to reduce the damage associated with programming electrical fuses 失效
标题翻译：减少与电气保险丝编程相关的损害的方法和结构
公开(公告)号：US06432760B1
公开(公告)日：2002-08-13
申请号：US09751475
申请日：2000-12-28
申请人： Chandrasekharan Kothandaraman , Michael Stetter , Sundar K. Iyer
发明人： Chandrasekharan Kothandaraman , Michael Stetter , Sundar K. Iyer
IPC分类号： H01L218238
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An improved fuse structure in an integrated circuit (IC) structure is made by forming a gate stack comprised of layers of polysilicon and a silicide. Subsequent to the formation of the silicide layer, an etch stop silicon nitride layer is deposited over the silicide layer. The silicon nitride layer is patterned to expose the silicide layer. A soft passivation layer is deposited over the exposed silicide layer. The soft passivation layer has a low thermal conductivity which confines energy in the silicide layer, minimizing the current needed to program the fuse. The inherent ductility of the soft passivation layer prevents the generation of cracks in the surrounding layers.
摘要翻译：通过形成由多晶硅层和硅化物层构成的栅极堆叠来形成集成电路（IC）结构中的改进的熔丝结构。在形成硅化物层之后，在硅化物层上沉积蚀刻停止氮化硅层。图案化氮化硅层以暴露硅化物层。在钝化的硅化物层上沉积软钝化层。软钝化层具有低热导率，其将能量限制在硅化物层中，使得对熔丝编程所需的电流最小化。软钝化层的固有延展性防止周围层产生裂纹。

26. 发明申请

US20130285694A1 THROUGH-SILICON-VIA WITH SACRIFICIAL DIELECTRIC LINE 有权
标题翻译：通过硅胶与绝缘电介质线
公开(公告)号：US20130285694A1
公开(公告)日：2013-10-31
申请号：US13457692
申请日：2012-04-27
申请人： Troy L. Graves-Abe , Benjamin A. Himmel , Chandrasekharan Kothandaraman , Norman W. Robson
发明人： Troy L. Graves-Abe , Benjamin A. Himmel , Chandrasekharan Kothandaraman , Norman W. Robson
IPC分类号： G01R31/26 , H01L21/28 , H01L21/66 , H01L23/48
CPC分类号： H01L22/14 , G01R31/2853 , H01L21/76898 , H01L2924/00 , H01L2924/0002
摘要： A TSV structure, method of making the TSV structure and methods of testing the TSV structure. The structure including: a trench extending from a top surface of a semiconductor substrate to a bottom surface of the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region.
摘要翻译： TSV结构，制造TSV结构的方法和TSV结构测试方法。该结构包括：从半导体衬底的顶表面延伸到半导体衬底的底表面的沟槽，沟槽围绕半导体衬底的芯区; 在沟槽的所有侧壁上的电介质衬垫; 以及电导体填充沟槽中的所有剩余空间，电介质衬垫将电导体与半导体衬底和芯区域电隔离。

27. 发明授权

US08384145B2 Non-volatile memory device using hot-carrier injection 有权
标题翻译：使用热载流子注入的非易失性存储器件
公开(公告)号：US08384145B2
公开(公告)日：2013-02-26
申请号：US12692923
申请日：2010-01-25
申请人： Roger Allen Booth, Jr. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei
发明人： Roger Allen Booth, Jr. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei
IPC分类号： H01L29/76
CPC分类号： H01L29/7923 , H01L29/66833
摘要： Each of a hot-carrier non-volatile memory device and a method for fabricating the hot carrier non-volatile memory device is predicated upon a semiconductor structure and related method that includes a metal oxide semiconductor field effect transistor structure. The semiconductor structure and related method include at least one of: (1) a spacer that comprises a dielectric material having a dielectric constant greater than 7 (for enhanced hot carrier derived charge capture and retention); and (2) a drain region that comprises a semiconductor material that has a narrower bandgap than a bandgap of a semiconductor material from which is comprised a channel region (for enhanced impact ionization and charged carrier generation).
摘要翻译：热载体非易失性存储器件和用于制造热载体非易失性存储器件的方法中的每一种都取决于包括金属氧化物半导体场效应晶体管结构的半导体结构和相关方法。半导体结构和相关方法包括以下中的至少一个：（1）包括介电常数大于7的介电材料的间隔物（用于增强热载体导电的电荷捕获和保留）; 和（2）包括半导体材料的漏极区，该半导体材料具有比半导体材料的带隙窄的带隙，其包括沟道区（用于增强的冲击电离和带电载流子的生成）。

28. 发明授权

US08299570B2 Efuse containing sige stack 有权
标题翻译： Efuse包含sige堆栈
公开(公告)号：US08299570B2
公开(公告)日：2012-10-30
申请号：US13189016
申请日：2011-07-22
申请人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
发明人： Deok-Kee Kim , Dureseti Chidambarrao , William K. Henson , Chandrasekharan Kothandaraman
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.
摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

29. 发明授权

US08283202B2 Single mask adder phase change memory element 有权
标题翻译：单掩模加法器相变存储元件
公开(公告)号：US08283202B2
公开(公告)日：2012-10-09
申请号：US12549997
申请日：2009-08-28
申请人： Matthew J. Breitwisch , Chandrasekharan Kothandaraman , Chung H. Lam
发明人： Matthew J. Breitwisch , Chandrasekharan Kothandaraman , Chung H. Lam
IPC分类号： H01L45/00
CPC分类号： H01L45/148 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/143 , H01L45/144 , H01L45/1683
摘要： A method of fabricating a phase change memory element within a semiconductor structure includes etching an opening to an upper surface of a bottom electrode, the opening being formed of a height equal to a height of a metal region at a same layer within the semiconductor structure, depositing phase change material within the opening, recessing the phase change material within the opening, and forming a top electrode on the recessed phase change material.
摘要翻译：在半导体结构内制造相变存储元件的方法包括蚀刻到底部电极的上表面的开口，该开口由等于半导体结构内同一层的金属区域的高度的高度形成，在开口内沉积相变材料，使开关内的相变材料凹陷，并在凹陷相变材料上形成顶部电极。

30. 发明授权

US07982285B2 Antifuse structure having an integrated heating element 有权
标题翻译：防腐结构具有集成的加热元件
公开(公告)号：US07982285B2
公开(公告)日：2011-07-19
申请号：US11970750
申请日：2008-01-08
申请人： Byeongju Park , Subramanian S. Iyer , Chandrasekharan Kothandaraman
发明人： Byeongju Park , Subramanian S. Iyer , Chandrasekharan Kothandaraman
IPC分类号： H01L23/52
CPC分类号： H01L23/5252 , G11C17/165 , G11C2229/763 , H01L27/11206 , H01L2924/0002 , H01L2924/3011 , Y10S257/928 , H01L2924/00
摘要： The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.
摘要翻译：本发明提供了具有集成加热元件的反熔丝结构及其编程方法，反熔丝结构包括第一和第二导体以及形成在导体之间的电介质层，其中一个或两个导体用作传统的反熔丝导体和作为用于在编程期间直接加热反熔丝介电层的加热元件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式