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1. 发明授权

US08975910B2 Through-silicon-via with sacrificial dielectric line 有权
标题翻译：带有牺牲介质线的硅通孔
公开(公告)号：US08975910B2
公开(公告)日：2015-03-10
申请号：US13457692
申请日：2012-04-27
申请人： Troy L. Graves-Abe , Benjamin A. Himmel , Chandrasekharan Kothandaraman , Norman W. Robson
发明人： Troy L. Graves-Abe , Benjamin A. Himmel , Chandrasekharan Kothandaraman , Norman W. Robson
IPC分类号： G01R31/26 , H01L21/28 , H01L21/768 , H01L21/66 , G01R31/28
CPC分类号： H01L22/14 , G01R31/2853 , H01L21/76898 , H01L2924/00 , H01L2924/0002
摘要： A TSV structure, method of making the TSV structure and methods of testing the TSV structure. The structure including: a trench extending from a top surface of a semiconductor substrate to a bottom surface of the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region.
摘要翻译： TSV结构，制造TSV结构的方法和TSV结构测试方法。该结构包括：从半导体衬底的顶表面延伸到半导体衬底的底表面的沟槽，沟槽围绕半导体衬底的芯区; 在沟槽的所有侧壁上的电介质衬垫; 以及电导体填充沟槽中的所有剩余空间，电介质衬垫将电导体与半导体衬底和芯区域电隔离。

2. 发明申请

US20130285694A1 THROUGH-SILICON-VIA WITH SACRIFICIAL DIELECTRIC LINE 有权
标题翻译：通过硅胶与绝缘电介质线
公开(公告)号：US20130285694A1
公开(公告)日：2013-10-31
申请号：US13457692
申请日：2012-04-27
申请人： Troy L. Graves-Abe , Benjamin A. Himmel , Chandrasekharan Kothandaraman , Norman W. Robson
发明人： Troy L. Graves-Abe , Benjamin A. Himmel , Chandrasekharan Kothandaraman , Norman W. Robson
IPC分类号： G01R31/26 , H01L21/28 , H01L21/66 , H01L23/48
CPC分类号： H01L22/14 , G01R31/2853 , H01L21/76898 , H01L2924/00 , H01L2924/0002
摘要： A TSV structure, method of making the TSV structure and methods of testing the TSV structure. The structure including: a trench extending from a top surface of a semiconductor substrate to a bottom surface of the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region.
摘要翻译： TSV结构，制造TSV结构的方法和TSV结构测试方法。该结构包括：从半导体衬底的顶表面延伸到半导体衬底的底表面的沟槽，沟槽围绕半导体衬底的芯区; 在沟槽的所有侧壁上的电介质衬垫; 以及电导体填充沟槽中的所有剩余空间，电介质衬垫将电导体与半导体衬底和芯区域电隔离。

3. 发明申请

US20130334691A1 SIDEWALLS OF ELECTROPLATED COPPER INTERCONNECTS 有权
标题翻译：电镀铜互连的边界
公开(公告)号：US20130334691A1
公开(公告)日：2013-12-19
申请号：US13525823
申请日：2012-06-18
申请人： Mukta G. Farooq , John A. Fitzsimmons , Troy L. Graves-Abe
发明人： Mukta G. Farooq , John A. Fitzsimmons , Troy L. Graves-Abe
IPC分类号： H01L23/52 , H01L21/283
CPC分类号： H05K3/423 , H01L21/76844 , H01L21/76846 , H01L21/76858 , H01L21/76898 , H01L23/481 , H01L23/53209 , H01L23/53214 , H01L23/53238 , H01L23/53242 , H01L23/53257 , H01L2924/0002 , Y10T428/12764 , H01L2924/00
摘要： A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material. The structure including a first intermetallic compound separating the diffusion barrier from the conductive material, the first intermetallic compound comprises an alloying material and the conductive material, and is mechanically bound to the conductive material, the alloying material is at least one of the materials selected from the group of chromium, tin, nickel, magnesium, cobalt, aluminum, manganese, titanium, zirconium, indium, palladium, and silver; and a first high friction interface located between the diffusion barrier and the first intermetallic compound and parallel to the sidewall of the opening, wherein the first high friction interface results in a mechanical bond between the diffusion barrier and the first intermetallic compound.
摘要翻译：一种形成在开口中的结构，其具有由非金属材料限定的基本上垂直的侧壁，并且具有由导电垫限定的基本上水平的底部，该结构包括覆盖侧壁的扩散阻挡层和由导电材料构成的填充物。所述结构包括将所述扩散阻挡物与所述导电材料分离的第一金属间化合物，所述第一金属间化合物包括合金材料和所述导电材料，并且机械地结合到所述导电材料上，所述合金材料是选自以下的至少一种材料：铬，锡，镍，镁，钴，铝，锰，钛，锆，铟，钯和银的组合; 以及位于所述扩散阻挡层和所述第一金属间化合物之间且平行于所述开口的侧壁的第一高摩擦界面，其中所述第一高摩擦界面导致所述扩散阻挡层和所述第一金属间化合物之间的机械结合。

4. 发明授权

US08546961B2 Alignment marks to enable 3D integration 有权
标题翻译：对齐标记以实现3D集成
公开(公告)号：US08546961B2
公开(公告)日：2013-10-01
申请号：US12987202
申请日：2011-01-10
申请人： Mukta G. Farooq , Troy L. Graves-Abe , Robert Hannon , Emily R. Kinser , William F. Landers , Kevin S. Petrarca , Richard P. Volant , Kevin R. Winstel
发明人： Mukta G. Farooq , Troy L. Graves-Abe , Robert Hannon , Emily R. Kinser , William F. Landers , Kevin S. Petrarca , Richard P. Volant , Kevin R. Winstel
IPC分类号： H01L23/544 , H01L21/02
CPC分类号： H01L21/76898 , H01L21/8221 , H01L23/544 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2223/54426 , H01L2224/29187 , H01L2224/2919 , H01L2224/32145 , H01L2224/8385 , H01L2224/83896 , H01L2224/9202 , H01L2224/94 , H01L2225/06541 , H01L2225/06593 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2224/83
摘要： Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.
摘要翻译：公开了包括对准标记的结构和在三维（3D）结构中形成对准标记的方法）。该方法包括在第一半导体衬底的第一表面中形成孔; 将第一半导体衬底的第一表面接合到第二半导体衬底的第一表面; 在第一半导体衬底的第二表面上使第一半导体薄化以提供孔和第一半导体衬底之间的光学对比度; 以及使用所述孔将所述第一半导体衬底的所述第二表面上的特征对准为至少一个对准标记。

5. 发明授权

US08476168B2 Non-conformal hardmask deposition for through silicon etch 有权
标题翻译：用于通过硅蚀刻的非保形硬掩模沉积
公开(公告)号：US08476168B2
公开(公告)日：2013-07-02
申请号：US13014114
申请日：2011-01-26
申请人： Troy L. Graves-Abe , Mukta G Farooq
发明人： Troy L. Graves-Abe , Mukta G Farooq
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L21/76898
摘要： The present invention provides a method to form deep features in a stacked semiconductor structure. Deposition of a non-conformal hardmask onto a patterned topography can form a hardmask to protect all but recessed areas with minimal integration steps. The invention enables etching deep features, even through multiple BEOL layers, without multiple additional process steps.
摘要翻译：本发明提供一种在堆叠半导体结构中形成深层特征的方法。将非保形硬掩模沉积到图案化地形上可以形成硬掩模，以最小的集成步骤来保护所有凹陷区域。本发明即使通过多个BEOL层也能够蚀刻深层特征，而不需要多个额外的工艺步骤。

6. 发明申请

US20120175789A1 ALIGNMENT MARKS TO ENABLE 3D INTEGRATION 有权
标题翻译：对齐标记可以实现3D集成
公开(公告)号：US20120175789A1
公开(公告)日：2012-07-12
申请号：US12987202
申请日：2011-01-10
申请人： Mukta G. Farooq , Troy L. Graves-Abe , Robert Hannon , Emily R. Kinser , William F. Landers , Kevin S. Patrarca , Richard P. Volant , Kevin R. Winstel
发明人： Mukta G. Farooq , Troy L. Graves-Abe , Robert Hannon , Emily R. Kinser , William F. Landers , Kevin S. Patrarca , Richard P. Volant , Kevin R. Winstel
IPC分类号： H01L23/544 , H01L21/02
CPC分类号： H01L21/76898 , H01L21/8221 , H01L23/544 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2223/54426 , H01L2224/29187 , H01L2224/2919 , H01L2224/32145 , H01L2224/8385 , H01L2224/83896 , H01L2224/9202 , H01L2224/94 , H01L2225/06541 , H01L2225/06593 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2224/83
摘要： Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.
摘要翻译：公开了包括对准标记的结构和在三维（3D）结构中形成对准标记的方法）。该方法包括在第一半导体衬底的第一表面中形成孔; 将第一半导体衬底的第一表面接合到第二半导体衬底的第一表面; 在第一半导体衬底的第二表面上使第一半导体薄化以提供孔和第一半导体衬底之间的光学对比度; 以及使用所述孔将所述第一半导体衬底的所述第二表面上的特征对准为至少一个对准标记。

7. 发明申请

US20130260556A1 BOTTOM-UP PLATING OF THROUGH-SUBSTRATE VIAS 有权
公开(公告)号：US20130260556A1
公开(公告)日：2013-10-03
申请号：US13431343
申请日：2012-03-27
申请人： Mukta G. Farooq , John A. Fitzsimmons , Troy L. Graves-Abe
发明人： Mukta G. Farooq , John A. Fitzsimmons , Troy L. Graves-Abe
IPC分类号： H01L21/288 , H01L21/683
CPC分类号： H01L21/76898 , H01L21/6835 , H01L21/6836 , H01L21/76879 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2221/68359 , H01L2224/03462 , H01L2224/03622 , H01L2224/0401 , H01L2224/05556 , H01L2224/05572 , H01L2224/05611 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/05671 , H01L2224/11 , H01L2224/13025 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/94 , Y10T29/41 , H01L2924/00012 , H01L2924/00014 , H01L2224/03 , H01L2924/014
摘要： According to one embodiment of the present invention, a method of plating a TSV hole in a substrate is provided. The TSV hole may include an open end terminating at a conductive pad, a stack of wiring levels, and a plurality of chip interconnects. The method of plating a TSV may include attaching a handler to the plurality of chip interconnects, the handler having a conductive layer in electrical contact with the plurality of chip interconnects; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive layer to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including the conductive layer, the plurality of chip interconnects, the stack of wiring levels and the conductive pad.

8. 发明申请

US20120190204A1 NON-CONFORMAL HARDMASK DEPOSITION FOR THROUGH SILICON ETCH 有权
标题翻译：不合格的硬质合金沉积通过硅蚀刻
公开(公告)号：US20120190204A1
公开(公告)日：2012-07-26
申请号：US13014114
申请日：2011-01-26
申请人： Troy L. Graves-Abe , Mukta G. Farooq
发明人： Troy L. Graves-Abe , Mukta G. Farooq
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L21/76898
摘要： The present invention provides a method to form deep features in a stacked semiconductor structure. Deposition of a non-conformal hardmask onto a patterned topography can form a hardmask to protect all but recessed areas with minimal integration steps. The invention enables etching deep features, even through multiple BEOL layers, without multiple additional process steps.
摘要翻译：本发明提供一种在堆叠半导体结构中形成深层特征的方法。将非保形硬掩模沉积到图案化地形上可以形成硬掩模，以最小的集成步骤来保护所有凹陷区域。本发明即使通过多个BEOL层也能够蚀刻深层特征，而不需要多个额外的工艺步骤。

9. 发明授权

US09214435B2 Via structure for three-dimensional circuit integration 有权
标题翻译： Via结构用于三维电路集成
公开(公告)号：US09214435B2
公开(公告)日：2015-12-15
申请号：US13476056
申请日：2012-05-21
申请人： Mukta G. Farooq , Troy L. Graves-Abe , Spyridon Skordas , Kevin R. Winstel
发明人： Mukta G. Farooq , Troy L. Graves-Abe , Spyridon Skordas , Kevin R. Winstel
IPC分类号： H01L21/768 , H01L23/00 , H01L23/48 , H01L25/065 , H01L23/538 , H01L27/06
CPC分类号： H01L24/09 , H01L21/76898 , H01L23/481 , H01L23/5386 , H01L24/80 , H01L24/82 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L27/0688 , H01L2224/02205 , H01L2224/08145 , H01L2224/0905 , H01L2224/80896 , H01L2224/82031 , H01L2224/82101 , H01L2224/9202 , H01L2224/94 , H01L2225/06544 , H01L2924/0002 , H01L2924/14 , H01L2924/3701 , H01L2924/00 , H01L2224/80
摘要： Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.
摘要翻译：公开了结合三维积分的电路及其制造方法。一个电路包括底层和多个上层。底层包括连接到底层中的功能部件的底部着陆垫。此外，上层堆叠在底层上方。每个上层包括相应的上层板，其连接到各个上层中的各个功能部件。着陆焊盘通过单个导电通孔耦合，并且在底层和上层的堆叠中对准，使得每个着陆焊盘从堆叠中的相邻层中的任何一个着陆焊盘偏移至少一个预定金额。

10. 发明授权

US08956973B2 Bottom-up plating of through-substrate vias 有权
标题翻译：贯穿基板通孔的自底向上电镀
公开(公告)号：US08956973B2
公开(公告)日：2015-02-17
申请号：US13431343
申请日：2012-03-27
申请人： Mukta G. Farooq , John A. Fitzsimmons , Troy L. Graves-Abe
发明人： Mukta G. Farooq , John A. Fitzsimmons , Troy L. Graves-Abe
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L21/6835 , H01L21/6836 , H01L21/76879 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2221/68359 , H01L2224/03462 , H01L2224/03622 , H01L2224/0401 , H01L2224/05556 , H01L2224/05572 , H01L2224/05611 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/05671 , H01L2224/11 , H01L2224/13025 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/94 , Y10T29/41 , H01L2924/00012 , H01L2924/00014 , H01L2224/03 , H01L2924/014
摘要： According to one embodiment of the present invention, a method of plating a TSV hole in a substrate is provided. The TSV hole may include an open end terminating at a conductive pad, a stack of wiring levels, and a plurality of chip interconnects. The method of plating a TSV may include attaching a handler to the plurality of chip interconnects, the handler having a conductive layer in electrical contact with the plurality of chip interconnects; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive layer to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including the conductive layer, the plurality of chip interconnects, the stack of wiring levels and the conductive pad.
摘要翻译：根据本发明的一个实施例，提供了一种在衬底中电镀TSV孔的方法。 TSV孔可以包括终止于导电焊盘的开口端，布线层的堆叠以及多个芯片互连。电镀TSV的方法可以包括将处理器附接到多个芯片互连件，处理器具有与多个芯片互连电接触的导电层; 将包括导电垫的TSV孔的封闭端暴露于电解质溶液中; 以及沿着从所述导电层到所述导电焊盘的电路径施加电势，从而导致来自所述电解质溶液的导电材料沉积在所述导电焊盘和所述TSV孔内，所述电路包括所述导电层，所述多个芯片互连，布线层叠和导电焊盘。

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