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1. 发明申请

US20110101496A1 FOUR-TERMINAL ANTIFUSE STRUCTURE HAVING INTEGRATED HEATING ELEMENTS FOR A PROGRAMMABLE CIRCUIT 有权
标题翻译：具有可编程电路的集成加热元件的四端抗结构
公开(公告)号：US20110101496A1
公开(公告)日：2011-05-05
申请号：US13004129
申请日：2011-01-11
申请人： Byeongju Park , Subramanian S. Iyer , Chandrasekharan Kothandaraman
发明人： Byeongju Park , Subramanian S. Iyer , Chandrasekharan Kothandaraman
IPC分类号： H01L23/525 , H01L21/326
CPC分类号： H01L23/5252 , G11C17/165 , G11C2229/763 , H01L27/11206 , H01L2924/0002 , H01L2924/3011 , Y10S257/928 , H01L2924/00
摘要： The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.
摘要翻译：本发明提供了具有集成加热元件的反熔丝结构及其编程方法，反熔丝结构包括第一和第二导体以及形成在导体之间的电介质层，其中一个或两个导体用作传统的反熔丝导体和作为用于在编程期间直接加热反熔丝介电层的加热元件。

2. 发明授权

US07323761B2 Antifuse structure having an integrated heating element 有权
标题翻译：防腐结构具有集成的加热元件
公开(公告)号：US07323761B2
公开(公告)日：2008-01-29
申请号：US10988132
申请日：2004-11-12
申请人： Byeongju Park , Subramanian S. Iyer , Chandrasekheran Kothandaraman
发明人： Byeongju Park , Subramanian S. Iyer , Chandrasekheran Kothandaraman
IPC分类号： H01L23/52
CPC分类号： H01L23/5252 , G11C17/165 , G11C2229/763 , H01L27/11206 , H01L2924/0002 , H01L2924/3011 , Y10S257/928 , H01L2924/00
摘要： The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.
摘要翻译：本发明提供了具有集成加热元件的反熔丝结构及其编程方法，反熔丝结构包括第一和第二导体以及形成在导体之间的电介质层，其中一个或两个导体用作传统的反熔丝导体和作为用于在编程期间直接加热反熔丝介电层的加热元件。

3. 发明授权

US07276771B2 Diode and method for manufacturing the same 有权
公开(公告)号：US07276771B2
公开(公告)日：2007-10-02
申请号：US11473886
申请日：2006-06-23
申请人： Tatsuhiko Fujihira , Yasushi Miyasaka
发明人： Tatsuhiko Fujihira , Yasushi Miyasaka
IPC分类号： H01L27/095 , H01L29/47 , H01L29/812 , H01L31/07
CPC分类号： H01L29/66136 , H01L29/0619 , H01L29/0692 , H01L29/36 , H01L29/417 , H01L29/66143 , H01L29/8611 , H01L29/872 , Y10S257/928
摘要： A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least 1/100 of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.

4. 发明申请

US20070035024A1 Semiconductor device having an improved wiring or electrode structure 有权
标题翻译：具有改进的布线或电极结构的半导体器件
公开(公告)号：US20070035024A1
公开(公告)日：2007-02-15
申请号：US11410194
申请日：2006-04-25
申请人： Toshihiko Shiga , Hitoshi Nakamura , Junji Tanimura
发明人： Toshihiko Shiga , Hitoshi Nakamura , Junji Tanimura
IPC分类号： H01L23/48
CPC分类号： H01L21/28575 , H01L29/452 , Y10S257/928
摘要： An ohmic electrode is formed by stacking a lower Ti layer, a diffusion preventing layer, an upper Ti layer, and a metallic (Au) layer on a p-type GaAs layer. The diffusion preventing layer includes tantalum (Ta) or niobium (Nb). Thus, interdiffusion of Ga and As in the p-type GaAs layer and Au in the metallic layer can be prevented, and variation in resistivity of the ohmic electrode in a high-temperature, high-humidity environment can be suppressed.
摘要翻译：通过在p型GaAs层上堆叠下Ti层，扩散防止层，上Ti层和金属（Au）层来形成欧姆电极。扩散防止层包括钽（Ta）或铌（Nb）。因此，可以防止金属层中的p型GaAs层和Au中的Ga和As的相互扩散，并且可以抑制在高温，高湿度环境中的欧姆电极的电阻率的变化。

5. 发明申请

US20050282356A1 Semiconductor layer structure and method of making the same 有权
标题翻译：半导体层结构及制作方法
公开(公告)号：US20050282356A1
公开(公告)日：2005-12-22
申请号：US11092499
申请日：2005-03-29
申请人： Sang-Yun Lee
发明人： Sang-Yun Lee
IPC分类号： H01L21/20 , H01L21/30 , H01L21/336 , H01L21/46 , H01L21/58 , H01L23/48 , H01L27/108 , H01L27/148
CPC分类号： H01L21/2007 , H01L21/6835 , H01L21/84 , H01L24/29 , H01L24/83 , H01L27/0688 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/11 , H01L27/11551 , H01L29/66666 , H01L29/7827 , H01L2221/6835 , H01L2224/291 , H01L2224/8385 , H01L2924/01005 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/01049 , H01L2924/01056 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01093 , H01L2924/07802 , H01L2924/12036 , H01L2924/1301 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , Y10S257/928 , H01L2924/00
摘要： A method of forming a circuit includes providing a first substrate; positioning an interconnect region on a surface of the first substrate; providing a second substrate; positioning a device structure on a surface of the second substrate, the device structure including a stack of at least three doped semiconductor material layers; and bonding the device structure to the interconnect region.
摘要翻译：一种形成电路的方法包括提供第一衬底; 将互连区域定位在所述第一基板的表面上; 提供第二基板; 将器件结构定位在第二衬底的表面上，器件结构包括至少三个掺杂半导体材料层的堆叠; 以及将所述器件结构接合到所述互连区域。

6. 发明申请

US20050029622A1 Antifuse structure and method of use 失效
标题翻译：防腐结构及使用方法
公开(公告)号：US20050029622A1
公开(公告)日：2005-02-10
申请号：US10931714
申请日：2004-09-01
申请人： Kenneth Marr , Shubneesh Batra
发明人： Kenneth Marr , Shubneesh Batra
IPC分类号： H01L23/525 , H01L29/00 , H01L21/44
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , Y10S257/928 , H01L2924/00
摘要： An antifuse structure and method of use are disclosed. According to one embodiment of the present invention a first programming voltage is coupled to a well of a first conductivity type in a substrate of a second conductivity type in an antifuse. A second programming voltage is coupled to a conductive terminal of the second conductivity type in the antifuse to create a current path through an insulator between the conductive terminal and the well to program the antifuse. The first programming voltage may be coupled to an ohmic contact in the well in the antifuse.
摘要翻译：公开了反熔丝结构和使用方法。根据本发明的一个实施例，第一编程电压在反熔丝中耦合到第二导电类型的衬底中的第一导电类型的阱。第二编程电压在反熔丝中耦合到第二导电类型的导电端子，以产生通过导电端子和阱之间的绝缘体的电流路径，以对反熔丝进行编程。第一编程电压可以耦合到反熔丝中的阱中的欧姆接触。

7. 发明授权

US06770950B2 Non-volatile semiconductor memory structure 失效
标题翻译：非易失性半导体存储器结构
公开(公告)号：US06770950B2
公开(公告)日：2004-08-03
申请号：US10099801
申请日：2002-03-13
申请人： Ching-Song Yang , Shih-Jye Shen , Ching-Hsiang Hsu
发明人： Ching-Song Yang , Shih-Jye Shen , Ching-Hsiang Hsu
IPC分类号： H01L2900
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521 , H01L29/7885 , H01L29/792 , Y10S257/928
摘要： A non-volatile semiconductor memory cell structure and method of manufacture. The method includes the steps of forming a shallow first-type well layer, a second-type well layer and a deep first-type well layer over a substrate, forming stack gates over the shallow first-type well layer and finally forming source terminals and drain terminals. The source terminals penetrate through the shallow first-type well layer and connect with the second-type well layer. The drain terminals are close to the surface of the shallow first-type well layer. Both the source terminals and the drain terminals contain second type dopants.
摘要翻译：非挥发性半导体存储单元结构及其制造方法。该方法包括以下步骤：在衬底上形成浅的第一类型阱层，第二类型阱层和深度第一类型阱层，在浅的第一类型阱层上形成堆叠栅极，最后形成源极端子; 漏极端子。源极穿透浅的第一类型阱层并与第二类型阱层连接。漏极端子靠近浅第一型阱层的表面。源极端子和漏极端子都包含第二种掺杂剂。

8. 发明申请

US20030030120A1 Diode and method for manufacturing the same 有权
标题翻译：二极管及其制造方法
公开(公告)号：US20030030120A1
公开(公告)日：2003-02-13
申请号：US10262699
申请日：2002-10-02
申请人： Fuji Electric Co., Ltd.
发明人： Tatsuhiko Fujihira , Yasushi Miyasaka
IPC分类号： H01L027/095
CPC分类号： H01L29/66136 , H01L29/0619 , H01L29/0692 , H01L29/36 , H01L29/417 , H01L29/66143 , H01L29/8611 , H01L29/872 , Y10S257/928
摘要： A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least {fraction (1/100)} of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.
摘要翻译：提供一种二极管，其包括第一导电型阴极层，放置在阴极区上并具有比阴极层低的浓度的第一导电型漂移层，大致呈环状的第二导电型环状区域形成在漂移层中的第二导电型阳极区域，形成在位于环形区域内部的漂移层中的第二导电型阳极区域，与阴极层接触形成的阴极电极以及与该阳极区域接触形成的阳极电极，其中最低第二导电型阳极区域的电阻率至少为漂移层电阻率的1/100，阳极区域的厚度小于环形区域的扩散深度。

9. 发明申请

US20020004264A1 Method for fabricating a simplified CMOS polysilicon thin film transistor and resulting structure 失效
标题翻译：制造简化的CMOS多晶硅薄膜晶体管及其结构的方法
公开(公告)号：US20020004264A1
公开(公告)日：2002-01-10
申请号：US09941200
申请日：2001-08-28
发明人： Salman Akram
IPC分类号： H01L021/00 , H01L021/84 , H01L021/8238
CPC分类号： H01L27/127 , H01L27/1214 , Y10S257/928
摘要： A method of forming a MOS device using doped and activated n-type and p-type polysilicon layers includes forming a first doped and activated polysilicon area (either n-type and p-type) on a substrate. An isolation material layer is formed abutting the first activated area. A second doped and activated polysilicon area of opposite conductivity type from the first activated area is formed adjacent to the isolation material layer. The second activated opposite area has a height that does not exceed that of the first doped and activated polysilicon layer. Further processing may be effected to complete the MOS device. The method of the present invention eliminates ion implantation and annealing steps used in previously existing methods.
摘要翻译：使用掺杂和活化的n型和p型多晶硅层形成MOS器件的方法包括在衬底上形成第一掺杂和活化的多晶硅区域（n型和p型）。形成邻接第一激活区域的隔离材料层。与隔离材料层相邻地形成有与第一激活区域相反的导电类型的第二掺杂和活化多晶硅区域。第二激活的相对区域的高度不超过第一掺杂和活化多晶硅层的高度。可以进一步处理以完成MOS器件。本发明的方法消除了先前存在的方法中使用的离子注入和退火步骤。

10. 发明授权

US5982015A High breakdown voltage semiconductor device 失效
公开(公告)号：US5982015A
公开(公告)日：1999-11-09
申请号：US251489
申请日：1999-02-17
申请人： Keizo Hirayama , Hideyuki Funaki , Fumito Suzuki , Akio Nakagawa
发明人： Keizo Hirayama , Hideyuki Funaki , Fumito Suzuki , Akio Nakagawa
IPC分类号： H01L29/06 , H01L29/40 , H01L29/47 , H01L29/861 , H01L29/872 , H01L27/095 , H01L29/812 , H01L31/07
CPC分类号： H01L29/404 , H01L29/0692 , H01L29/8611 , H01L29/872 , Y10S257/928
摘要： Disclosed is a high breakdown voltage semiconductor device comprising a semiconductor substrate, an active layer consisting of a high resistivity semiconductor layer of a first conductivity type formed on the substrate with an insulating layer interposed therebetween, a first impurity region of the first conductivity type formed within the active layer, a second impurity region of a second conductivity type formed within the active layer, a third impurity region of the second conductivity type formed within the second impurity region and having a high impurity concentration, a first electrode being in ohmic contact with the first impurity region and the fourth impurity region, and a second electrode being in Schottky contact with the second impurity region and in ohmic contact with the third impurity region.

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