专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20140019833A1 MEMORY SYSTEM AND METHOD 审中-公开
标题翻译：记忆系统和方法
公开(公告)号：US20140019833A1
公开(公告)日：2014-01-16
申请号：US14031620
申请日：2013-09-19
申请人： Seung-Jun Bae , Kwang-II Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
发明人： Seung-Jun Bae , Kwang-II Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
IPC分类号： G06F11/10
CPC分类号： G06F11/1004 , H03M13/09
摘要： A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.
摘要翻译：存储器系统包括存储器控制器和存储器件。存储器件通过第一通道与存储器控制器交换数据，通过与存储器控制器的第二通道交换与数据相关联的第一循环冗余校验（CRC）代码，并且接收包括相关联的第二CRC码的命令/地址分组具有来自存储器控制器的命令/地址通过第三通道。

22. 发明授权

US08010765B2 Semiconductor memory device and method for controlling clock latency according to reordering of burst data 失效
标题翻译：半导体存储器件和根据突发数据的重排序来控制时钟延迟的方法
公开(公告)号：US08010765B2
公开(公告)日：2011-08-30
申请号：US11775780
申请日：2007-07-10
申请人： Joo-Sun Choi , Won-Chang Jung , Hi-Choon Lee , Sung-Min Yim , Chul-Woo Park , Won-Il Bae
发明人： Joo-Sun Choi , Won-Chang Jung , Hi-Choon Lee , Sung-Min Yim , Chul-Woo Park , Won-Il Bae
IPC分类号： G06F12/00
CPC分类号： G11C7/1045 , G11C7/1072
摘要： In an embodiment, a semiconductor memory device includes a clock latency that can be controlled responsive to whether or not an output order of burst data is reordered. The semiconductor memory device may comprise a control unit and a latency control unit. The control unit may generate a latency control signal having a logic level that varies depending on whether or not an output order of burst data is reordered. The latency control unit may control a latency value in response to the latency control signal. The semiconductor memory device and the method of controlling the latency value responsive to a reordering of the burst data allow for an optimally fast memory access time.
摘要翻译：在一个实施例中，半导体存储器件包括响应于突发数据的输出顺序是否被重新排序而被控制的时钟等待时间。半导体存储器件可以包括控制单元和等待时间控制单元。控制单元可以生成具有根据突发数据的输出顺序是否被重新排列而变化的逻辑电平的等待时间控制信号。延迟控制单元可以响应于等待时间控制信号来控制等待时间值。半导体存储器件和响应于突发数据的重排序来控制延迟值的方法允许最佳的快速存储器存取时间。

23. 发明授权

US07965530B2 Memory modules and memory systems having the same 有权
标题翻译：存储器模块和具有相同功能的存储器系统
公开(公告)号：US07965530B2
公开(公告)日：2011-06-21
申请号：US12330351
申请日：2008-12-08
申请人： You-Keun Han , Seung-Jin Seo , Kwan-Yong Jin , Jung-Hwan Choi , Jong-Hoon Kim , Seok-Il Kim , Joo-Sun Choi
发明人： You-Keun Han , Seung-Jin Seo , Kwan-Yong Jin , Jung-Hwan Choi , Jong-Hoon Kim , Seok-Il Kim , Joo-Sun Choi
IPC分类号： G11C5/02
CPC分类号： G11C5/04 , G11C5/02 , G11C7/1027 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C2207/107 , G11C2207/2272
摘要： A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set.
摘要翻译：存储器模块包括被配置为接收/发送关联数据的多个数据端口和多个存储器件。所述多个存储器件包括至少一个等级的第一组存储器件，第一组的每个存储器件耦合到每个相关联的数据端口，以及在至少一个其它级中的第二组存储器件，所述第二组的每个存储器件被配置为通过所述第一组的至少每个相关联的存储器装置接收/发送所述存储器设备的相关联的数据。

24. 发明授权

US07543106B2 Apparatus and method for controlling refresh of semiconductor memory device according to positional information of memory chips 有权
标题翻译：根据存储芯片的位置信息控制半导体存储器件的刷新的装置和方法
公开(公告)号：US07543106B2
公开(公告)日：2009-06-02
申请号：US11504421
申请日：2006-08-15
申请人： Joo-Sun Choi
发明人： Joo-Sun Choi
IPC分类号： G06F12/16 , G11C7/00
CPC分类号： G06F13/1636 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C2211/4061
摘要： A memory controller controlling a plurality of semiconductor memory devices includes a refresh control circuit controlling refresh operations of the semiconductor memory devices according to positional information of memory chips of the memory devices. The refresh control circuit classifies the semiconductor memory devices into first and second groups and sets an auto refresh interval of the semiconductor memory devices belong to the first group and an auto refresh interval of the semiconductor memory devices belong to the second group different from each other.
摘要翻译：控制多个半导体存储器件的存储器控制器包括根据存储器件的存储器芯片的位置信息控制半导体存储器件的刷新操作的刷新控制电路。刷新控制电路将半导体存储器件分为第一组和第二组，并且设置属于第一组的半导体存储器件的自动刷新间隔，并且属于第二组的半导体存储器件的自动刷新间隔彼此不同。

25. 发明授权

US07366052B2 Memory device, memory system and method of inputting/outputting data into/from the same 有权
标题翻译：存储器件，存储器系统以及从其输入/输出数据的方法
公开(公告)号：US07366052B2
公开(公告)日：2008-04-29
申请号：US11582290
申请日：2006-10-17
申请人： Joo-Sun Choi
发明人： Joo-Sun Choi
IPC分类号： G01C8/00
CPC分类号： G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/107
摘要： A memory device includes a memory cell array, a row decoding section, a K-bit prefetch section and an output buffer section. The row decoding section decodes a row address in response to a first clock, to activate one of the word lines corresponding to the decoded row address. The K-bit prefetch section decodes a column address in response to a second clock and prefetches K data from K memory cells connected to the activated word line and corresponds to the decoded column address, in response to a second clock, where a frequency of the second clock is 1/M of that of the first clock. The output buffer section outputs the K prefetched data as a data stream in response to a third clock. Therefore, a burden from the physical limit of the access speed may be alleviated when the data I/O speed is increased.
摘要翻译：存储器件包括存储单元阵列，行解码部分，K位预取部分和输出缓冲器部分。行解码部分响应于第一时钟解码行地址，以激活对应于解码的行地址的字线之一。 K位预取部分响应于第二时钟对列地址进行解码，并且响应于第二时钟从与连接到激活字线的K个存储器单元中的K个存储器单元相对应地对应于解码的列地址，第二个时钟是第一个时钟的1 / M。输出缓冲器部分响应于第三个时钟输出K个预取数据作为数据流。因此，当数据I / O速度增加时，可以减轻访问速度的物理限制的负担。

26. 发明申请

US20070162689A1 Memory controller, memory module and memory system having the same, and method of controlling the memory system 审中-公开
标题翻译：具有相同的存储器控制器，存储器模块和存储器系统以及控制存储器系统的方法
公开(公告)号：US20070162689A1
公开(公告)日：2007-07-12
申请号：US11649477
申请日：2007-01-04
申请人： Joo-Sun Choi
发明人： Joo-Sun Choi
IPC分类号： G06F13/28
CPC分类号： G06F13/1615
摘要： A memory system includes a memory controller and a plurality of first memory components. The memory controller has a plurality of I/O channels, each of the I/O channels including a command/address bus and a data bus. The plurality of the first memory components are respectively coupled to the memory controller through the plurality of I/O channels. The memory controller respectively transmits commands/addresses and data to the plurality of first memory components through the plurality of I/O channels in order to independently control the plurality of first memory components.
摘要翻译：存储器系统包括存储器控制器和多个第一存储器组件。存储器控制器具有多个I / O通道，每个I / O通道包括命令/地址总线和数据总线。多个第一存储器组件通过多个I / O通道分别耦合到存储器控制器。存储器控制器通过多个I / O通道分别向多个第一存储器组件发送命令/地址和数据，以便独立地控制多个第一存储器组件。

27. 发明申请

US20070133247A1 Memory system having point-to-point (PTP) and point-to-two-point (PTTP) links between devices 有权
标题翻译：在设备之间具有点到点（PTP）和点到两点（PTTP）链路的存储器系统
公开(公告)号：US20070133247A1
公开(公告)日：2007-06-14
申请号：US11603648
申请日：2006-11-22
申请人： Jae-Jun Lee , Joo-Sun Choi , Kyu-Hyoun Kim , Kwang-Soo Park
发明人： Jae-Jun Lee , Joo-Sun Choi , Kyu-Hyoun Kim , Kwang-Soo Park
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： A memory system has first and second primary memories and first and second secondary memories coupled to the first and second primary memories, respectively, the coupling comprising at least one point-to-point connection. A memory module includes at least two of the first and second primary and first and second secondary memories. A first connection element, such as a connector or solder, connects the memory module to a mother board. A second connection element, such as a connector or solder, connects at least one other of the first and second primary and first and second secondary memories to the mother board. At least one of the memories on the first memory module is coupled to at least one of the other memories. The memory system also includes a memory controller which is connected to the primary memories by a point-to-two-point link.
摘要翻译：存储器系统具有第一和第二主存储器以及分别耦合到第一和第二主存储器的第一和第二辅助存储器，耦合器包括至少一个点到点连接。存储器模块包括第一和第二主要和第一和第二辅助存储器中的至少两个。诸如连接器或焊料的第一连接元件将存储器模块连接到母板。诸如连接器或焊料的第二连接元件将第一和第二初级和第二和第二辅助存储器中的至少一个连接到母板。第一存储器模块上的至少一个存储器耦合到至少一个其他存储器。存储器系统还包括存储器控制器，其通过点对二点链接连接到主存储器。

28. 发明授权

US08873324B2 Method of refreshing a memory device, refresh address generator and memory device 有权
标题翻译：刷新存储器件，刷新地址发生器和存储器件的方法
公开(公告)号：US08873324B2
公开(公告)日：2014-10-28
申请号：US13240049
申请日：2011-09-22
申请人： Chul-Woo Park , Joo-Sun Choi , Hong-Sun Hwang
发明人： Chul-Woo Park , Joo-Sun Choi , Hong-Sun Hwang
IPC分类号： G11C7/00
CPC分类号： G11C11/40618 , G11C11/40622 , G11C11/408
摘要： A refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging. A respective refresh is performed on a weak cell having a first address when the refresh address is a second address instead of on a first strong cell having the second address. A respective refresh is performed on one of the first strong cell or a second strong cell having a third address when the refresh address is the third address. Address information is stored for only one of the first, second, and third addresses such that memory capacity may be reduced. In alternative aspects, a respective refresh is performed on one of a weak cell, a first strong cell, or a second strong cell depending on a flag when the refresh address is any of at least one predetermined address to result in refresh leveraging.
摘要翻译：生成具有刷新周期的刷新地址，以刷新刷新的存储器件。当刷新地址是第二地址而不是具有第二地址的第一强单元时，对具有第一地址的弱小区执行相应的刷新。当刷新地址是第三地址时，在具有第三地址的第一强单元或第二强单元之一上执行相应的刷新。仅对第一，第二和第三地址中的一个存储地址信息，从而可以减少存储容量。在替代方面，当刷新地址是至少一个预定地址中的任一个以导致刷新利用时，依赖于标志，在弱小区，第一强小区或第二强小区中的一个上执行相应的刷新。

29. 发明授权

US08368440B2 Phase-locked-loop circuit including digitally-controlled oscillator 有权
标题翻译：锁相环电路包括数字控制振荡器
公开(公告)号：US08368440B2
公开(公告)日：2013-02-05
申请号：US13291548
申请日：2011-11-08
申请人： Woogeun Rhee , He Rui , Xueyi Yu , Tae-Young Oh , Joo-Sun Choi , Zhihua Wang
发明人： Woogeun Rhee , He Rui , Xueyi Yu , Tae-Young Oh , Joo-Sun Choi , Zhihua Wang
IPC分类号： H03L7/06
CPC分类号： H03L7/0995 , H03L7/087 , H03L7/093 , H03L2207/06
摘要： A phase-locked-loop (PLL) circuit is provided. The PLL circuit includes a phase/frequency detector, a digital filter, a digital low pass filter (LPF), a digitally controlled oscillator (DCO), and a frequency divider. The digital LPF performs a low-pass-filtering on least significant bits of first digital data in a digital mode and generates filtered second digital data. The DCO performs a digital-to-analog conversion on the second digital data and most significant bits of the first digital data to generate a first signal, generates an oscillation control signal based on the first signal, and generates an output clock signal oscillating in response to the oscillation control signal.
摘要翻译：提供了锁相环（PLL）电路。 PLL电路包括相位/频率检测器，数字滤波器，数字低通滤波器（LPF），数字控制振荡器（DCO）和分频器。数字LPF以数字模式对最低有效位的第一数字数据进行低通滤波，并产生滤波后的第二数字数据。 DCO对第二数字数据和第一数字数据的最高有效位执行数模转换以产生第一信号，基于第一信号产生振荡控制信号，并产生响应振荡的输出时钟信号到振荡控制信号。

30. 发明申请

US20120300568A1 Method of Refreshing a Memory Device, Refresh Address Generator and Memory Device 有权
标题翻译：刷新存储器件，刷新地址生成器和存储器件的方法
公开(公告)号：US20120300568A1
公开(公告)日：2012-11-29
申请号：US13240049
申请日：2011-09-22
申请人： Chul-Woo Park , Joo-Sun Choi , Hong-Sun Hwang
发明人： Chul-Woo Park , Joo-Sun Choi , Hong-Sun Hwang
IPC分类号： G11C11/402
CPC分类号： G11C11/40618 , G11C11/40622 , G11C11/408
摘要： A refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging. A respective refresh is performed on a weak cell having a first address when the refresh address is a second address instead of on a first strong cell having the second address. A respective refresh is performed on one of the first strong cell or a second strong cell having a third address when the refresh address is the third address. Address information is stored for only one of the first, second, and third addresses such that memory capacity may be reduced. In alternative aspects, a respective refresh is performed on one of a weak cell, a first strong cell, or a second strong cell depending on a flag when the refresh address is any of at least one predetermined address to result in refresh leveraging.
摘要翻译：生成具有刷新周期的刷新地址，以刷新刷新的存储器件。当刷新地址是第二地址而不是具有第二地址的第一强单元时，对具有第一地址的弱小区执行相应的刷新。当刷新地址是第三地址时，在具有第三地址的第一强单元或第二强单元之一上执行相应的刷新。仅对第一，第二和第三地址中的一个存储地址信息，从而可以减少存储容量。在替代方面，当刷新地址是至少一个预定地址中的任一个以导致刷新利用时，依赖于标志，在弱小区，第一强小区或第二强小区中的一个上执行相应的刷新。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式