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1. 发明授权

US10169042B2 Memory device that performs internal copy operation 有权
公开(公告)号：US10169042B2
公开(公告)日：2019-01-01
申请号：US14852774
申请日：2015-09-14
申请人： Young-soo Sohn , Sei-jin Kim , Kwang-il Park , Tae-young Kim , Chul-woo Park
发明人： Young-soo Sohn , Sei-jin Kim , Kwang-il Park , Tae-young Kim , Chul-woo Park
IPC分类号： G06F12/00 , G06F9/30 , G06F15/78
摘要： A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

2. 发明申请

US20160148654A1 MEMORY DEVICE HAVING PAGE STATE INFORMING FUNCTION 有权
标题翻译：具有页面状态信息功能的记忆设备
公开(公告)号：US20160148654A1
公开(公告)日：2016-05-26
申请号：US14852890
申请日：2015-09-14
申请人： Young-soo SOHN , Kwang-il PARK , Sei-jin KIM , Tae-young KIM
发明人： Young-soo SOHN , Kwang-il PARK , Sei-jin KIM , Tae-young KIM
IPC分类号： G11C7/00
CPC分类号： G11C7/109 , G11C7/1063 , G11C2207/2272
摘要： A memory device, system, and/or method are provided for performing a page state informing function. The memory device may compare one or more row addresses received along with a command, determine the page open/close state according to a page hit or miss generated as a result of comparison, count read or write commands with respect to pages corresponding to a same row address, and determine the page open/close state according to a read or write command number generated as a result of counting. The memory device may determine a page open/close state with respect to a corresponding page based on a page hit/miss and a read or write command number and output a flag signal. The memory device may provide the page open/close state for each channel. A memory controller may establish different page open/close policies for each channel.
摘要翻译：提供了用于执行页面状态通知功能的存储器件，系统和/或方法。存储器装置可以比较与命令一起接收的一个或多个行地址，根据作为比较的结果产生的页面命中或未命中来确定页面打开/关闭状态，相对于对应于页面的页面的计数读取或写入命令行地址，并根据由于计数产生的读或写命令号确定页打开/关闭状态。存储装置可以基于页命中/未命中和读或写命令号确定相对于页的页打开/关闭状态，并输出标志信号。存储器件可以为每个通道提供页面打开/关闭状态。存储器控制器可以为每个通道建立不同的页面打开/关闭策略。

3. 发明授权

US09287004B2 Semiconductor memory device and system having redundancy cells 有权
标题翻译：具有冗余单元的半导体存储器件和系统
公开(公告)号：US09287004B2
公开(公告)日：2016-03-15
申请号：US13670792
申请日：2012-11-07
申请人： Su-a Kim , Young-soo Sohn , Dae-hyun Kim
发明人： Su-a Kim , Young-soo Sohn , Dae-hyun Kim
IPC分类号： G06F11/20 , G06F12/00 , G11C29/04 , G11C29/00 , G11C7/10
CPC分类号： G11C29/04 , G11C7/1045 , G11C29/808 , G11C29/81 , G11C29/848
摘要： In one embodiment, the memory device includes a memory cell array having at least a first memory cell group, a second memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, the second memory cell group includes a plurality of second memory cells associated with a second data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. A data line selection circuit is configured to provide a data path between an input/output node and one of the first data line, the second data and the redundancy data line.
摘要翻译：在一个实施例中，存储器件包括具有至少第一存储单元组，第二存储单元组和冗余存储单元组的存储单元阵列。第一存储单元组包括与第一数据线相关联的多个第一存储器单元，第二存储单元组包括与第二数据线相关联的多个第二存储器单元，并且冗余存储单元组包括多个冗余存储器与冗余数据线相关联的单元。数据线选择电路被配置为在输入/输出节点与第一数据线，第二数据和冗余数据线之一之间提供数据路径。

4. 发明申请

US20140317469A1 MEMORY DEVICE FOR PERFORMING ERROR CORRECTION CODE OPERATION AND REDUNDANCY REPAIR OPERATION 有权
标题翻译：用于执行错误修正代码操作和冗余维修操作的存储器件
公开(公告)号：US20140317469A1
公开(公告)日：2014-10-23
申请号：US14208795
申请日：2014-03-13
申请人： Young-soo Sohn , Kwang-il Park , Chul-woo Park , Jong-pil Son , Jae-youn Youn , Hoi-ju Chung
发明人： Young-soo Sohn , Kwang-il Park , Chul-woo Park , Jong-pil Son , Jae-youn Youn , Hoi-ju Chung
IPC分类号： G06F11/10 , G11C29/10
CPC分类号： G06F11/1068 , G06F3/064 , G06F3/0679 , G06F11/1052 , G11C29/42 , G11C29/44 , G11C29/4401 , G11C29/52 , G11C29/808 , G11C29/848 , G11C2029/0409 , G11C2029/0411 , G11C2029/1208
摘要： Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.
摘要翻译：提供了执行ECC操作和冗余修复操作的存储器件和存储器模块。存储器件通过使用纠错码（ECC）操作来修复由于“故障”单元而导致的单位错误，并且当“失败”单元不可修复时，通过使用冗余修复操作来修复“失败”单元通过ECC操作。冗余修复操作包括数据线修复和块修复。 ECC操作可以改变对应于包括“失败”单元的每单位存储器单元的数据的码字，并且还可以改变关于改变的码字的奇偶校验位的大小。

5. 发明授权

US08654593B2 Stacked semiconductor memory device, memory system including the same, and method of repairing defects of through silicon vias 有权
标题翻译：堆叠的半导体存储器件，包括其的存储器系统以及通过硅通孔修复缺陷的方法
公开(公告)号：US08654593B2
公开(公告)日：2014-02-18
申请号：US13085776
申请日：2011-04-13
申请人： Tae-Young Oh , Kwang-Il Park , Yun-Seok Yang , Young-Soo Sohn , Si-Hong Kim , Seung-Jun Bae
发明人： Tae-Young Oh , Kwang-Il Park , Yun-Seok Yang , Young-Soo Sohn , Si-Hong Kim , Seung-Jun Bae
IPC分类号： G11C7/10
CPC分类号： G11C29/702 , G11C7/10 , H01L22/22 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2225/06541
摘要： A stacked semiconductor memory device according to the inventive concepts may include a plurality of memory chips stacked above a processor chip, a plurality of TSVs, and I/O buffers. The TSVs may pass through the memory chips and are connected to the processor chip. I/O buffers may be coupled between all or part of the memory chips and the TSVs and may be selectively activated on the basis of defective states of the TSVs.
摘要翻译：根据本发明构思的叠层半导体存储器件可以包括堆叠在处理器芯片上方的多个存储器芯片，多个TSV和I / O缓冲器。 TSV可以通过存储器芯片并且连接到处理器芯片。 I / O缓冲器可以耦合在所有或部分存储器芯片和TSV之间，并且可以基于TSV的故障状态来选择性地激活。

6. 发明授权

US08645790B2 Data processing device and method using error detection code, method of compensating for data skew, and semiconductor device having the data processing device 有权
标题翻译：使用错误检测码的数据处理装置和方法，补偿数据偏移的方法，以及具有数据处理装置的半导体装置
公开(公告)号：US08645790B2
公开(公告)日：2014-02-04
申请号：US13239156
申请日：2011-09-21
申请人： Jin-il Lee , Dong-min Kim , Young-soo Sohn , Kwang-il Park
发明人： Jin-il Lee , Dong-min Kim , Young-soo Sohn , Kwang-il Park
IPC分类号： H03M13/00
CPC分类号： H03M13/09 , H04L1/0061
摘要： A data processing device for transmitting a first data includes a data generator configured to provide the first data, a cyclic redundancy check (CRC) generator configured to generate a CRC information having at least one bit whose binary value is modified in response to a toggle information, and a data transmitter configured to combine the CRC information and the first data as a combined data and output the combined data in serial. A data processing method for transmitting a first data includes a step of generating a first data, a step of generating cyclic redundancy check (CRC) information having at least one bit whose binary value is modified in response to a toggle information, and a step of generating a combined data by combining the generated CRC information and the first data as a combined data and outputting the combined data in serial.
摘要翻译：一种用于发送第一数据的数据处理装置包括被配置为提供第一数据的数据生成器，循环冗余校验（CRC）发生器，被配置为生成具有响应于切换信息修改其二进制值的至少一个比特的至少一个比特的CRC信息以及数据发送器，被配置为组合CRC信息和第一数据作为组合数据，并串行输出组合数据。用于发送第一数据的数据处理方法包括产生第一数据的步骤，产生具有响应于切换信息修改其二进制值的至少一个比特的循环冗余校验（CRC）信息的步骤，以及步骤通过组合生成的CRC信息和第一数据作为组合数据来生成组合数据，并串行输出组合数据。

7. 发明申请

US20140019833A1 MEMORY SYSTEM AND METHOD 审中-公开
标题翻译：记忆系统和方法
公开(公告)号：US20140019833A1
公开(公告)日：2014-01-16
申请号：US14031620
申请日：2013-09-19
申请人： Seung-Jun Bae , Kwang-II Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
发明人： Seung-Jun Bae , Kwang-II Park , Young-Soo Sohn , Young-Hyun Jun , Joo-Sun Choi , Tae-Young Oh
IPC分类号： G06F11/10
CPC分类号： G06F11/1004 , H03M13/09
摘要： A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.
摘要翻译：存储器系统包括存储器控制器和存储器件。存储器件通过第一通道与存储器控制器交换数据，通过与存储器控制器的第二通道交换与数据相关联的第一循环冗余校验（CRC）代码，并且接收包括相关联的第二CRC码的命令/地址分组具有来自存储器控制器的命令/地址通过第三通道。

8. 发明授权

US08254201B2 Semiconductor memory device having power-saving effect 有权
标题翻译：具有省电效果的半导体存储器件
公开(公告)号：US08254201B2
公开(公告)日：2012-08-28
申请号：US12797791
申请日：2010-06-10
申请人： Young-Soo Sohn , Kwang-Il Park , Kyoung-Ho Kim , Seung-Jun Bae
发明人： Young-Soo Sohn , Kwang-Il Park , Kyoung-Ho Kim , Seung-Jun Bae
IPC分类号： G11C8/18 , G11C7/10
CPC分类号： G11C7/22 , G11C7/1078 , G11C7/1084 , G11C8/18 , G11C2207/2227 , G11C2207/2272
摘要： A semiconductor memory device includes a memory cell array, a controller, and a data input/output (I/O) unit. The memory cell array includes a plurality of memory cells and is configured to store data. The controller is configured to enable a write clock signal in response to an active command when a write latency of the semiconductor device is less than a reference write latency and disable the write clock signal during a disabling period in which read data is output from the semiconductor device. The data I/O unit is configured to receive data in response to the write clock signal and output the data to the memory cell array.
摘要翻译：半导体存储器件包括存储单元阵列，控制器和数据输入/输出（I / O）单元。存储单元阵列包括多个存储单元，并被配置为存储数据。当半导体器件的写入延迟小于参考写入延迟并且在从半导体输出读取数据的禁用期间禁止写入时钟信号时，控制器被配置为响应于有效命令来使能写入时钟信号设备。数据I / O单元被配置为响应于写时钟信号接收数据并将数据输出到存储单元阵列。

9. 发明申请

US20120087194A1 DATA WRITE TRAINING METHOD AND SEMICONDUCTOR DEVICE PERFORMING THE SAME 有权
标题翻译：数据写入训练方法和执行相同的半导体器件
公开(公告)号：US20120087194A1
公开(公告)日：2012-04-12
申请号：US13270710
申请日：2011-10-11
申请人： Tae-Young OH , Young-Soo SOHN , Seung-Jun BAE , Kwang-Il PARK
发明人： Tae-Young OH , Young-Soo SOHN , Seung-Jun BAE , Kwang-Il PARK
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1087 , G11C7/1093 , G11C2207/2254
摘要： Embodiments may be directed to a method of operating a semiconductor device, the method including receiving a first write training command, receiving a first write data responsive to the first write training command through a first data line, and transmitting the first write data through a second data line. Transmitting the first write data is performed without an additional training command.
摘要翻译：实施例可以涉及一种操作半导体器件的方法，所述方法包括接收第一写入训练命令，响应于通过第一数据线的第一写入训练命令接收第一写入数据，以及通过第二数据线发送第一写入数据数据线。在不附加训练命令的情况下执行发送第一写入数据。

10. 发明申请

US20120086490A1 INTEGRATED CIRCUIT DEVICES USING POWER SUPPLY CIRCUITS WITH FEEDBACK FROM A REPLICA LOAD 有权
标题翻译：使用电源电路的集成电路装置与反馈装置的反馈
公开(公告)号：US20120086490A1
公开(公告)日：2012-04-12
申请号：US13240635
申请日：2011-09-22
申请人： Su-yeon Doo , Seung-jun Bae , Kwang-il Park , Young-soo Sohn
发明人： Su-yeon Doo , Seung-jun Bae , Kwang-il Park , Young-soo Sohn
IPC分类号： H03K3/023 , G05F1/10
CPC分类号： H03K19/00361 , G05F1/575
摘要： An integrated circuit device includes an external power supply input configured to be coupled to an external power supply and a digital circuit, such as a clock signal generator circuit, that generates noise at a power supply input thereof. The device further includes a replica load circuit and a power supply circuit coupled to the external power supply input, to a power supply input of the digital circuit and to a power supply input of the replica load circuit. The power supply circuit is configured to selectively couple the external power supply node to the power supply input of the digital circuit responsive to a voltage at the power supply input of the replica load circuit. The replica load circuit may be configured to provide a load that varies responsive to a voltage at the power supply input of the digital circuit.
摘要翻译：集成电路装置包括被配置为耦合到外部电源的外部电源输入和在其电源输入处产生噪声的数字电路，例如时钟信号发生器电路。该装置还包括复制负载电路和耦合到外部电源输入的电源电路，数字电路的电源输入和复制负载电路的电源输入。电源电路被配置为响应于复制负载电路的电源输入处的电压来选择性地将外部电源节点耦合到数字电路的电源输入。复制负载电路可以被配置为提供响应于数字电路的电源输入处的电压而变化的负载。

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