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1. 发明授权

US08279652B2 Reconfigurable input/output in hierarchical memory link 有权
标题翻译：分层存储器链路中可重配置的输入/输出
公开(公告)号：US08279652B2
公开(公告)日：2012-10-02
申请号：US12708049
申请日：2010-02-18
申请人： Joo-Sun Choi
发明人： Joo-Sun Choi
IPC分类号： G11C5/06
CPC分类号： G11C5/04 , G11C7/10 , H01L2924/0002 , H01L2924/00
摘要： A memory system and memory module includes a plurality of memory devices, each having a plurality, e.g. four, ports for transmitting and receiving command signals, write data signals and read data signals. One of the memory devices is connected to a host or controller, and the remaining memories are connected together, typically by point-to-point links. When the memory system configuration is such that at least one of the ports in at least one of the memory devices is not used, one or more other ports can use the pins that may otherwise have been used by the unused ports. As a result, a set of reconfigurable, shared pins is defined in which two ports share the pins. The port that is not being used in a particular application for the memory device is not connected to the shared pins, and another port that is being used in the application is connected to the shared pins. This allows for the used of fewer package pins and, consequently, reduced package size.
摘要翻译：存储器系统和存储器模块包括多个存储器件，每个存储器件具有多个，例如，四个用于发送和接收命令信号的端口，写数据信号和读数据信号。其中一个存储设备连接到主机或控制器，其余存储器通常通过点对点链路连接在一起。当存储器系统配置使得至少一个存储器设备中的至少一个端口不被使用时，一个或多个其他端口可以使用另外可能由未使用的端口使用的引脚。因此，定义了一组可重新配置的共享引脚，其中两个端口共享引脚。在存储器件的特定应用中未使用的端口未连接到共享引脚，并且应用中正在使用的另一个端口连接到共享引脚。这允许使用更少的封装引脚，从而减少封装尺寸。

2. 发明授权

US08161349B2 Data parallelizing receiver 有权
标题翻译：数据并行接收器
公开(公告)号：US08161349B2
公开(公告)日：2012-04-17
申请号：US12183552
申请日：2008-07-31
申请人： Hoe-Ju Chung , Joo-Sun Choi , Ken S. Lim
发明人： Hoe-Ju Chung , Joo-Sun Choi , Ken S. Lim
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/6575
摘要： Provided is a data parallelizing receiver including an input signal receiver for externally receiving serial data as packets, sampling the serial data, aligning the sampled data in an input order, and converting the aligned data into parallel data to output the parallel data, a cyclic redundancy check (CRC) partial calculator for receiving the parallel data, classifying the parallel data into groups according to the input order, and performing a partial CRC calculation on each of the groups to sequentially output a plurality of partial CRC calculation results, and a CRC partial calculation merger for receiving the plurality of partial CRC calculation results and merging the partial CRC calculation results to output CRC calculation data.
摘要翻译：提供了一种数据并行接收器，包括用于从外部接收串行数据作为分组的输入信号接收器，对串行数据进行采样，以输入顺序对准采样数据，并将对准的数据转换为并行数据以输出并行数据，循环冗余检查（CRC）部分计算器，用于接收并行数据，根据输入顺序将并行数据分组成组，并对每个组执行部分CRC计算，以顺序输出多个部分CRC计算结果，以及CRC部分用于接收多个部分CRC计算结果的计算合并，并将部分CRC计算结果合并到输出CRC计算数据。

3. 发明授权

US07930492B2 Memory system having low power consumption 失效
标题翻译：具有低功耗的存储系统
公开(公告)号：US07930492B2
公开(公告)日：2011-04-19
申请号：US12006766
申请日：2008-01-04
申请人： Hoe-Ju Chung , Jung-Bae Lee , Joo-Sun Choi
发明人： Hoe-Ju Chung , Jung-Bae Lee , Joo-Sun Choi
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G11C7/1075
摘要： A memory system selectively sets signaling modes based on stack position information. The memory system includes a memory module having at least one semiconductor memory device and a memory controller configured to set a signaling mode based on stack position information of each of the semiconductor memory devices. A signaling between the memory controller and each of the semiconductor memory devices is performed in a differential signaling mode, and a signaling among the semiconductor memory devices is performed in a single-ended signaling mode. Accordingly, the memory system has reduced power consumption.
摘要翻译：存储器系统基于堆栈位置信息选择性地设置信令模式。存储器系统包括具有至少一个半导体存储器件和存储器控制器的存储器模块，该存储器控制器被配置为基于每个半导体存储器件的堆叠位置信息设置信号模式。在差分信令模式中执行存储器控制器和每个半导体存储器件之间的信令，并且以单端信令模式执行半导体存储器件之间的信令。因此，存储系统具有降低的功耗。

4. 发明授权

US07538573B2 Dynamic output buffer circuit 有权
标题翻译：动态输出缓冲电路
公开(公告)号：US07538573B2
公开(公告)日：2009-05-26
申请号：US11705251
申请日：2007-02-12
申请人： Jae-kwan Kim , Joo-sun Choi
发明人： Jae-kwan Kim , Joo-sun Choi
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H04L25/0278 , H04L25/0288
摘要： A dynamic output buffer circuit performs an impedance matching function and a pre-emphasis function by using input and output signals, and consumes relatively less power, occupies a relatively smaller layout area, and dynamically varies an output impedance. The dynamic output buffer circuit dynamically matches an output impedance to the characteristic impedance of a metal line connected to an external circuit, pre-emphasizes at least one input signal, and includes a control circuit and an output circuit. The control circuit matches the output impedance of the dynamic output circuit to the characteristic impedance of the metal line in response to at least one output signal, and outputs a plurality of resistor control signals which are used to pre-emphasize at least one input signal in response to the input signal. The output circuit controls the output impedance and pre-emphasizes the input signal in response to the resistor control signals, and outputs the output signal.
摘要翻译：动态输出缓冲电路通过使用输入和输出信号来执行阻抗匹配功能和预加重功能，并且消耗相对较小的功率，占据相对较小的布局面积，并且动态地改变输出阻抗。动态输出缓冲电路将输出阻抗与连接到外部电路的金属线的特性阻抗动态匹配，预先强调至少一个输入信号，并且包括控制电路和输出电路。响应于至少一个输出信号，控制电路将动态输出电路的输出阻抗与金属线的特性阻抗相匹配，并输出多个电阻控制信号，用于预先强调至少一个输入信号响应输入信号。输出电路控制输出阻抗，并响应于电阻控制信号预加强输入信号，并输出输出信号。

5. 发明申请

US20090103374A1 MEMORY MODULES AND MEMORY SYSTEMS HAVING THE SAME 有权
标题翻译：具有相同模式的存储器模块和存储器系统
公开(公告)号：US20090103374A1
公开(公告)日：2009-04-23
申请号：US12330351
申请日：2008-12-08
申请人： You-Keun HAN , Seung-Jin SEO , Kwan-Yong JIN , Jung-Hwan CHOI , Jong-Hoon KIM , Seok-Il KIM , Joo-Sun CHOI
发明人： You-Keun HAN , Seung-Jin SEO , Kwan-Yong JIN , Jung-Hwan CHOI , Jong-Hoon KIM , Seok-Il KIM , Joo-Sun CHOI
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C5/04 , G11C5/02 , G11C7/1027 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C2207/107 , G11C2207/2272
摘要： A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set.
摘要翻译：存储器模块包括被配置为接收/发送关联数据的多个数据端口和多个存储器件。所述多个存储器件包括至少一个等级的第一组存储器件，第一组的每个存储器件耦合到每个相关联的数据端口，以及在至少一个其它级中的第二组存储器件，所述第二组的每个存储器件被配置为通过所述第一组的至少每个相关联的存储器装置接收/发送所述存储器设备的相关联的数据。

6. 发明申请

US20070106838A1 Apparatus and method for controlling refresh of semiconductor memory device 有权
标题翻译：用于控制半导体存储器件刷新的装置和方法
公开(公告)号：US20070106838A1
公开(公告)日：2007-05-10
申请号：US11504421
申请日：2006-08-15
申请人： Joo-Sun Choi
发明人： Joo-Sun Choi
IPC分类号： G06F13/28
CPC分类号： G06F13/1636 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C2211/4061
摘要： A memory controller controlling a plurality of semiconductor memory devices includes a refresh control circuit controlling refresh operations of the semiconductor memory devices. The refresh control circuit classifies the semiconductor memory devices into first and second groups and sets an auto refresh interval of the semiconductor memory devices belong to the first group and an auto refresh interval of the semiconductor memory devices belong to the second group different from each other.
摘要翻译：控制多个半导体存储器件的存储器控制器包括控制半导体存储器件的刷新操作的刷新控制电路。刷新控制电路将半导体存储器件分为第一组和第二组，并且设置属于第一组的半导体存储器件的自动刷新间隔，并且属于第二组的半导体存储器件的自动刷新间隔彼此不同。

7. 发明授权

US06242812B1 CSP pin configuration compatible with TSOP pin configuration 有权
标题翻译： CSP引脚配置与TSOP引脚配置兼容
公开(公告)号：US06242812B1
公开(公告)日：2001-06-05
申请号：US09323837
申请日：1999-06-02
申请人： Joo Sun Choi
发明人： Joo Sun Choi
IPC分类号： H01L2348
CPC分类号： H01L24/10 , H01L23/50 , H01L24/06 , H01L24/13 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/13 , H01L2224/13099 , H01L2924/01004 , H01L2924/01005 , H01L2924/01033 , H01L2924/01082 , H01L2924/00
摘要： The present invention relates to a pin configuration in a highly integrated memory chip; and, more particularly, to a CSP pin configuration which is compatible with a TSOP pin configuration. A CSP semiconductor device according to the present invention comprises: a die pad area formed in the middle of a semiconductor chip; a first ball pad area allocated at a left side of the die pad area, having a ball array having first and second columns; and a second ball pad area allocated at a right side of the die pad area, having a ball array having first and second columns, wherein the first ball pad area includes ball pads which are positioned at a right side of a corresponding TSOP, wherein the second ball pad area includes ball pads which are positioned at a left side of the corresponding TSOP, wherein the first column of the first ball pad area includes even number pins of the corresponding TSOP, which are disposed in order of lower priority, and the second column of the first ball pad area includes odd number pins of the corresponding TSOP, which are disposed in order of lower priority, and wherein the first column of the second ball pad area includes even number pins of the corresponding TSOP, which are disposed in order of higher priority, and the second column of the second ball pad area includes odd number pins of the TSOP, which are disposed in order of higher priority.
摘要翻译：本发明涉及高度集成的存储芯片中的引脚配置; 更具体地说，涉及与TSOP引脚配置兼容的CSP引脚配置。根据本发明的CSP半导体器件包括：形成在半导体芯片中间的管芯焊盘区域; 分配在芯片焊盘区域的左侧的第一球焊盘区域，具有具有第一和第二列的球阵列; 以及分配在芯片焊盘区域的右侧的第二球焊盘区域，具有具有第一和第二列的球阵列，其中第一球垫区域包括位于相应TSOP右侧的球垫，其中，第二球垫区域包括位于相应TSOP的左侧的球垫，其中第一球垫区域的第一列包括相应TSOP的偶数针，其按优先级顺序排列，第二球垫所述第一球焊盘区域的列包括相应TSOP的奇数引脚，其以较低优先级的顺序布置，并且其中第二球焊盘区域的第一列包括相应的TSOP的偶数引脚，其按顺序布置并且第二球焊盘区域的第二列包括以较高优先级的顺序设置的TSOP的奇数引脚。

8. 发明授权

US5886932A Composite mode substrate voltage generation circuit for dynamic random access memory 失效
标题翻译：用于动态随机存取存储器的复合模式衬底电压产生电路
公开(公告)号：US5886932A
公开(公告)日：1999-03-23
申请号：US966192
申请日：1997-11-07
申请人： Joo Sun Choi
发明人： Joo Sun Choi
IPC分类号： G11C11/407 , G05F3/20 , G11C5/14 , G11C11/401 , G11C11/403 , G11C11/4074 , G11C11/408 , H01L21/8242 , H01L27/108 , G11C16/04
CPC分类号： G05F3/205 , G11C11/4074 , G11C5/146
摘要： A composite mode substrate voltage generation circuit for a DRAM which has a memory cell block and a peripheral circuit block formed on a single substrate. The circuit comprises a back-bias voltage generator for generating a first back-bias voltage in response to a normal refresh mode control signal or a second back-bias voltage in response to a self-refresh mode control signal and supplying the generated first or second back-bias voltage to the memory cell and peripheral circuit blocks, a first voltage level detector for detecting a level of the first back-bias voltage from the back-bias voltage generator, comparing the detected level of the first back-bias voltage with a first reference voltage level and controlling a voltage pumping operation of the back-bias voltage generator in accordance with the compared result, and a second voltage level detector for detecting a level of the second back-bias voltage from the back-bias voltage generator, comparing the detected level of the second back-bias voltage with a second reference voltage level and controlling the voltage pumping operation of the back-bias voltage generator in accordance with the compared result. A self-refresh operation can stably be performed at low power consumption, resulting in an increase in refresh efficiency of the DRAM.
摘要翻译：一种用于DRAM的复合模式衬底电压产生电路，其具有形成在单个衬底上的存储单元块和外围电路块。电路包括背偏置电压发生器，用于响应于自刷新模式控制信号响应于正常的刷新模式控制信号或第二反向偏置电压而产生第一反偏压，并将产生的第一或第二对所述存储单元和外围电路块的反向偏置电压;第一电压电平检测器，用于检测来自所述背偏电压发生器的所述第一反向偏置电压的电平，将所检测到的所述第一背偏电压的电平与第一参考电压电平，并且根据比较结果控制背偏置电压发生器的电压抽运操作;以及第二电压电平检测器，用于检测来自背偏电压发生器的第二反偏压电平的电平，比较检测到具有第二参考电压电平的第二背偏电压的电平，并且根据机智控制背偏置电压发生器的电压抽运操作 h比较结果。可以在低功耗下稳定地执行自刷新操作，导致DRAM的刷新效率的提高。

9. 发明授权

US08934311B2 Semiconductor memory device capable of screening a weak bit and repairing the same 有权
标题翻译：半导体存储器能够筛选弱点并进行修复
公开(公告)号：US08934311B2
公开(公告)日：2015-01-13
申请号：US13604308
申请日：2012-09-05
申请人： Hak-soo Yu , Uk-song Kang , Chul-woo Park , Joo-sun Choi , Hong-Sun Hwang
发明人： Hak-soo Yu , Uk-song Kang , Chul-woo Park , Joo-sun Choi , Hong-Sun Hwang
IPC分类号： G11C29/44 , G11C29/50 , G11C29/00 , G11C29/04 , G11C11/41
CPC分类号： G11C29/50 , G11C11/41 , G11C29/783 , G11C2029/0409 , G11C2029/4402
摘要： A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells.
摘要翻译：半导体器件包括包括多个存储单元的第一存储区域; 测试单元，被配置为测试所述第一存储器区域，并且从所述多个存储器单元中检测弱位; 以及第二存储器区域，被配置为存储所述第一存储器区域的弱位地址（WBA）以及要存储在所述弱位中的数据，其中所述第一存储器区域和所述第二存储器区域包括不同类型的存储器单元。

10. 发明授权

US08885380B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08885380B2
公开(公告)日：2014-11-11
申请号：US13209026
申请日：2011-08-12
申请人： Uk-song Kang , Young-hyun Jun , Joo-sun Choi
发明人： Uk-song Kang , Young-hyun Jun , Joo-sun Choi
IPC分类号： G11C5/02 , H01L25/18 , G11C7/10
CPC分类号： H01L25/18 , G11C5/02 , G11C7/10 , H01L2224/48091 , H01L2225/06544 , H01L2924/00014
摘要： A semiconductor package is disclosed. The semiconductor package includes a package interface, a stack of semiconductor chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip. The interface circuit includes an input connected to the first pair of terminals to receive a differential signal providing first information, and includes an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias.
摘要翻译：公开了半导体封装。半导体封装包括封装接口，半导体芯片堆叠，多个通过衬底通孔的堆叠以及接口电路。封装接口包括至少第一对端子。每个通过衬底通孔的堆叠包括相应的半导体芯片的多个通过衬底通孔，每个穿过衬底经由电连接到直接相邻的半导体芯片的贯穿衬底通孔。接口电路包括连接到第一对终端的输入端，以接收提供第一信息的差分信号，并且包括输出，以将包括单端信号格式的第一信息的输出信号提供给多个通过衬底通孔的堆叠。

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