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1. 发明授权

US07068280B1 Method and apparatus to provide overlay buffering 有权
标题翻译：提供覆盖缓冲的方法和装置
公开(公告)号：US07068280B1
公开(公告)日：2006-06-27
申请号：US10316727
申请日：2002-12-11
申请人： Joel C. McKee Cooper , Raghunath Rao , Miroslav Dokic
发明人： Joel C. McKee Cooper , Raghunath Rao , Miroslav Dokic
IPC分类号： G06T1/60 , G09G1/399 , G01C7/10 , G01C8/00
CPC分类号： G06F5/10 , G06F3/16 , G10L19/16 , H04N21/4392
摘要： Overlay buffering scheme for multi-channel data in which one memory buffer content is overlayed over another as memory locations of an input buffer are freed when data is output from the input buffer. By overlaying the buffer content, only one input buffer is used, reducing the needed memory by half.
摘要翻译：当从输入缓冲器输出数据时，多通道数据的叠加缓冲方案被释放，其中一个存储器缓冲器内容覆盖另一个存储器缓冲器内容作为输入缓冲器的存储器位置。通过覆盖缓冲区内容，仅使用一个输入缓冲区，将所需内存减少一半。

2. 发明授权

US07411860B2 Multiport semiconductor memory device 失效
标题翻译：多端口半导体存储器件
公开(公告)号：US07411860B2
公开(公告)日：2008-08-12
申请号：US11826493
申请日：2007-07-16
申请人： Koji Nii
发明人： Koji Nii
IPC分类号： G01C8/00 , G11C11/00
CPC分类号： G11C8/10 , G11C8/16 , G11C11/413
摘要： In the same row access, a voltage level of word lines WLA and WLB is set to a power supply voltage VDD−Vtp. On the other hand, in different rows access, a voltage level of word line WLA or WLB is set to power supply voltage VDD. Therefore, when both ports PA and PB simultaneously access the same row, the voltage level of word lines WLA, WLB is set to power supply voltage VDD−Vtp. Thus, a driving current amount of a memory cell is reduced, thereby preventing a reduction in a current ratio of a transistor. As a result, deterioration of SNM can be prevented.
摘要翻译：在同一行访问中，字线WLA和WLB的电压电平被设置为电源电压VDD-Vtp。另一方面，在不同的行访问中，字线WLA或WLB的电压电平被设置为电源电压VDD。因此，当两个端口PA和PB同时访问同一行时，字线WLA，WLB的电压电平被设置为电源电压VDD-Vtp。因此，减小了存储单元的驱动电流量，从而防止了晶体管的电流比的降低。结果，可以防止SNM的劣化。

3. 发明授权

US07366052B2 Memory device, memory system and method of inputting/outputting data into/from the same 有权
标题翻译：存储器件，存储器系统以及从其输入/输出数据的方法
公开(公告)号：US07366052B2
公开(公告)日：2008-04-29
申请号：US11582290
申请日：2006-10-17
申请人： Joo-Sun Choi
发明人： Joo-Sun Choi
IPC分类号： G01C8/00
CPC分类号： G11C7/1039 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4093 , G11C2207/107
摘要： A memory device includes a memory cell array, a row decoding section, a K-bit prefetch section and an output buffer section. The row decoding section decodes a row address in response to a first clock, to activate one of the word lines corresponding to the decoded row address. The K-bit prefetch section decodes a column address in response to a second clock and prefetches K data from K memory cells connected to the activated word line and corresponds to the decoded column address, in response to a second clock, where a frequency of the second clock is 1/M of that of the first clock. The output buffer section outputs the K prefetched data as a data stream in response to a third clock. Therefore, a burden from the physical limit of the access speed may be alleviated when the data I/O speed is increased.
摘要翻译：存储器件包括存储单元阵列，行解码部分，K位预取部分和输出缓冲器部分。行解码部分响应于第一时钟解码行地址，以激活对应于解码的行地址的字线之一。 K位预取部分响应于第二时钟对列地址进行解码，并且响应于第二时钟从与连接到激活字线的K个存储器单元中的K个存储器单元相对应地对应于解码的列地址，第二个时钟是第一个时钟的1 / M。输出缓冲器部分响应于第三个时钟输出K个预取数据作为数据流。因此，当数据I / O速度增加时，可以减轻访问速度的物理限制的负担。

4. 发明授权

US07038972B2 Double data rate synchronous dynamic random access memory semiconductor device 失效
标题翻译：双数据速率同步动态随机存取存储器半导体器件
公开(公告)号：US07038972B2
公开(公告)日：2006-05-02
申请号：US10793209
申请日：2004-03-04
申请人： Sung-min Seo , Chi-wook Kim , Kyu-hyoun Kim
发明人： Sung-min Seo , Chi-wook Kim , Kyu-hyoun Kim
IPC分类号： G01C8/00
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/1093 , G11C7/222
摘要： A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) semiconductor device is provided that prevents a conflict between data read from and data written to the DDR SDRAM semiconductor device when data is written to the DDR SDRAM semiconductor device, which includes a delay locked loop (“DLL”) circuit, a clock signal control unit, an output unit, and an output control unit, where the DLL circuit compensates for skew of an input clock signal and generates an output clock signal; the clock signal control unit receives a read signal activated when data stored in the DDR SDRAM semiconductor device is read out, a DLL locking signal activated when the DLL circuit performs a locking operation on the input clock signal, and the output clock signal, and outputs the output clock signal when either the read signal or the DLL locking signal is active; the output unit buffers data stored in the DDR SDRAM semiconductor device and outputs the data to outside of the DDR SDRAM semiconductor device in synchronization with the output clock signal output from the clock signal control unit; and the output control unit receives the output clock signal output from the clock signal control unit, and the read signal, and outputs the read signal to the output unit in synchronization with the output clock signal output from the clock signal control unit.
摘要翻译：提供了一种双倍数据速率（“DDR”）同步动态随机存取存储器（“SDRAM”）半导体器件，其防止当将数据写入DDR SDRAM半导体器件时从数据读取和写入DDR SDRAM半导体器件的数据之间的冲突，其包括延迟锁定环（“DLL”）电路，时钟信号控制单元，输出单元和输出控制单元，其中DLL电路补偿输入时钟信号的偏斜并产生输出时钟信号; 当读出存储在DDR SDRAM半导体器件中的数据时，时钟信号控制单元接收到激活的读取信号，当DLL电路对输入时钟信号执行锁定操作时激活的DLL锁定信号和输出时钟信号，并且输出当读取信号或DLL锁定信号有效时，输出时钟信号; 输出单元缓冲存储在DDR SDRAM半导体器件中的数据，并将数据与从时钟信号控制单元输出的输出时钟信号同步地输出到DDR SDRAM半导体器件的外部; 并且输出控制单元接收从时钟信号控制单元输出的输出时钟信号和读取信号，并将读出的信号与从时钟信号控制单元输出的输出时钟信号同步输出到输出单元。

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