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1. 发明授权

US09059698B2 Integrated circuit devices using power supply circuits with feedback from a replica load 有权
标题翻译：使用具有来自复制负载的反馈的电源电路的集成电路器件
公开(公告)号：US09059698B2
公开(公告)日：2015-06-16
申请号：US13240635
申请日：2011-09-22
申请人： Su-yeon Doo , Seung-jun Bae , Kwang-il Park , Young-soo Sohn
发明人： Su-yeon Doo , Seung-jun Bae , Kwang-il Park , Young-soo Sohn
IPC分类号： G05F1/00 , H03K19/003 , G05F1/575
CPC分类号： H03K19/00361 , G05F1/575
摘要： An integrated circuit device includes an external power supply input configured to be coupled to an external power supply and a digital circuit, such as a clock signal generator circuit, that generates noise at a power supply input thereof. The device further includes a replica load circuit and a power supply circuit coupled to the external power supply input, to a power supply input of the digital circuit and to a power supply input of the replica load circuit. The power supply circuit is configured to selectively couple the external power supply node to the power supply input of the digital circuit responsive to a voltage at the power supply input of the replica load circuit. The replica load circuit may be configured to provide a load that varies responsive to a voltage at the power supply input of the digital circuit.
摘要翻译：集成电路装置包括被配置为耦合到外部电源的外部电源输入和在其电源输入处产生噪声的数字电路，例如时钟信号发生器电路。该装置还包括复制负载电路和耦合到外部电源输入的电源电路，数字电路的电源输入和复制负载电路的电源输入。电源电路被配置为响应于复制负载电路的电源输入处的电压来选择性地将外部电源节点耦合到数字电路的电源输入。复制负载电路可以被配置为提供响应于数字电路的电源输入处的电压而变化的负载。

2. 发明授权

US08552891B2 Method and apparatus for parallel data interfacing using combined coding and recording medium therefor 有权
公开(公告)号：US08552891B2
公开(公告)日：2013-10-08
申请号：US13040606
申请日：2011-03-04
申请人： Seung Jun Bae , Jong Keun Ahn , Kwang Chol Choe
发明人： Seung Jun Bae , Jong Keun Ahn , Kwang Chol Choe
IPC分类号： H03M7/00
CPC分类号： H03M5/00 , H03K19/00346 , H04L25/03866 , H04L25/14 , H04L25/4908
摘要： A semiconductor device may include a coding lookup table unit including a plurality of coding lookup tables each of which is selected by a respectively selection signal, and a selection unit configured to receive one of N-bit parallel data and extract respective encoded data corresponding to the selection signal and to which the N-bit parallel data is mapped from the coding lookup table unit, and encoded data and extract respective N-bit parallel data corresponding to the selection signal and to which the encoded data is mapped from the coding lookup table unit, wherein N is 2 or an integer greater than 2, and wherein the coding lookup tables respectively store a plurality of coded data patterns that respectively correspond to patterns of the N-bit parallel data and are random temporally and spatially.

3. 发明申请

US20130235683A1 DATA WRITE TRAINING METHOD 有权
标题翻译：数据写入训练方法
公开(公告)号：US20130235683A1
公开(公告)日：2013-09-12
申请号：US13868425
申请日：2013-04-23
申请人： Tae-Young OH , Young-Soo SOHN , Seung-Jun BAE , Kwang-Il PARK
发明人： Tae-Young OH , Young-Soo SOHN , Seung-Jun BAE , Kwang-Il PARK
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G11C7/1087 , G11C7/1093 , G11C2207/2254
摘要： Embodiments may be directed to a method of operating a semiconductor device, the method including receiving a first write training command, receiving a first write data responsive to the first write training command through a first data line, and transmitting the first write data through a second data line. Transmitting the first write data is performed without an additional training command.
摘要翻译：实施例可以涉及一种操作半导体器件的方法，所述方法包括接收第一写入训练命令，响应于通过第一数据线的第一写入训练命令接收第一写入数据，以及通过第二数据线发送第一写入数据数据线。在不附加训练命令的情况下执行发送第一写入数据。

4. 发明授权

US08395955B2 Semiconductor memory interface device with a noise cancellation circuit having a phase and gain adjustment circuitry 有权
标题翻译：具有噪声消除电路的半导体存储器接口装置具有相位和增益调整电路
公开(公告)号：US08395955B2
公开(公告)日：2013-03-12
申请号：US12948193
申请日：2010-11-17
申请人： Tae-Young Oh , Seung-Jun Bae , Kwnag-Il Park
发明人： Tae-Young Oh , Seung-Jun Bae , Kwnag-Il Park
IPC分类号： G11C7/02
CPC分类号： G11C7/10 , G11C7/02
摘要： A memory interface circuit is provided, comprising: a first signal output circuit configured to output a first signal via a first signal line to a first I/O terminal; a second signal output circuit configured to output a second signal via a second signal line to a second I/O terminal; and a noise cancellation circuit having at least one phase adjusting element and at least one gain adjusting element to reduce a noise signal induced on the second signal line due to the presence of the first signal on the first signal line, wherein the second signal line is disposed adjacent to the first signal line.
摘要翻译：提供了一种存储器接口电路，包括：第一信号输出电路，被配置为经由第一信号线将第一信号输出到第一I / O端子; 第二信号输出电路，被配置为经由第二信号线将第二信号输出到第二I / O端子; 以及噪声消除电路，其具有至少一个相位调整元件和至少一个增益调整元件，以减少由于在第一信号线上存在第一信号而在第二信号线上感应到的噪声信号，其中第二信号线是设置在第一信号线附近。

5. 发明授权

US08335291B2 Semiconductor device, a parallel interface system and methods thereof 有权
标题翻译：半导体器件，并行接口系统及其方法
公开(公告)号：US08335291B2
公开(公告)日：2012-12-18
申请号：US12929627
申请日：2011-02-04
申请人： Seung-Jun Bae , Seong-Jin Jang , Beom-Sig Cho
发明人： Seung-Jun Bae , Seong-Jin Jang , Beom-Sig Cho
IPC分类号： H04L7/00
CPC分类号： G11C7/22 , H03K19/0966 , H04L7/0008 , H04L7/033 , H04L7/10
摘要： A semiconductor device, a parallel interface system and methods thereof are provided. The example semiconductor device may include a reference clock transmitting block generating a reference clock signal, a plurality of first transceiver blocks, each of the plurality of first transceiver blocks transmitting at least one parallel data bit signal based on one of a plurality of phase-controlled transmitting sampling clock signals and a per-pin deskew block controlling a phase of a transmitting sampling clock signal to generate the phase-controlled sampling clock signals for the respective plurality of transceiver blocks, the per-pin deskew block controlling the phase of each phase-controlled transmitting sampling clock signal based on a phase skew between a given training data bit signal, among a plurality of training data bit signals, corresponding to a given first transceiver block and the reference clock signal in a first operation mode, and based on phase skew information relating to a phase skew between a given parallel data bit signal of the at least one parallel data bit signal and the reference clock signal in a second operation mode. An example method may include reducing skew based on a comparison between a plurality of transmitted training data bit signals and a corresponding plurality of received training data bit signals in a first mode of operation and reducing skew based on received phase skew information relating to a phase skew difference between a reference signal and a parallel data bit signal in a second mode of operation.
摘要翻译：提供半导体器件，并行接口系统及其方法。示例性半导体器件可以包括产生参考时钟信号的参考时钟发送块，多个第一收发器块，多个第一收发器块中的每一个基于多个相位控制的多个第一收发器块中的一个发送至少一个并行数据位信号传输采样时钟信号和控制发射采样时钟信号的相位的每引脚偏移校正块，以产生相应的多个收发器模块的相位控制的采样时钟信号，每个引脚的去偏移块控制每个相位 - 基于相对于给定的第一收发器块的多个训练数据位信号中的给定训练数据位信号与第一操作模式中的参考时钟信号之间的相位偏移以及基于相位偏移的受控发送采样时钟信号与至少一个并行数据的给定并行数据位信号之间的相位偏移有关的信息在第二操作模式中的位信号和参考时钟信号。示例性方法可以包括基于在第一操作模式中的多个发送的训练数据比特信号与对应的多个接收的训练数据比特信号之间的比较来减少偏斜，并且基于接收到的相位偏移相关的相位偏移信息减少偏斜在第二操作模式中参考信号和并行数据位信号之间的差异。

6. 发明授权

US08169411B2 Touch screen device and operating method thereof 有权
标题翻译：触摸屏设备及其操作方法
公开(公告)号：US08169411B2
公开(公告)日：2012-05-01
申请号：US11646585
申请日：2006-12-28
申请人： Ho Joo Park , Seung Jun Bae , Yoon Hee Koo , Seong Cheol Kang
发明人： Ho Joo Park , Seung Jun Bae , Yoon Hee Koo , Seong Cheol Kang
IPC分类号： G06F3/041
CPC分类号： G06F3/0416 , G06F3/04883 , H04M1/66 , H04M2250/22 , H04R1/10 , H04R1/1041
摘要： A touch screen device and an operating method thereof are provided. More specifically, a touch screen device is provided which allows a user to selectively restrict input through a touch screen. The touch screen device includes a screen that includes a display configured to display images thereon and a detector configured to detect a touch on the display and convert the touch into an electrical signal, and a controller configured to cause images to be displayed on the display and receive and process signals from the detector. Further, a user may determine whether the controller is operated according to the signal input into the detector. The determination may be made either by a switch separately installed on an earphone or by inputting a signal into the detector by a user.
摘要翻译：提供一种触摸屏装置及其操作方法。更具体地，提供了允许用户选择性地限制通过触摸屏的输入的触摸屏设备。触摸屏设备包括：屏幕，其包括被配置为在其上显示图像的显示器;以及检测器，被配置为检测显示器上的触摸并将触摸转换为电信号;以及控制器，被配置为使图像显示在显示器上，以及接收和处理来自检测器的信号。此外，用户可以根据输入到检测器的信号来确定控制器是否被操作。可以通过分别安装在耳机上的开关或用户将信号输入到检测器中进行确定。

7. 发明申请

US20110298499A1 INTERNAL VOLTAGE GENERATOR AND INTEGRATED CIRCUIT DEVICE INCLUDING THE SAME 审中-公开
标题翻译：内部电压发生器和集成电路装置，包括它们
公开(公告)号：US20110298499A1
公开(公告)日：2011-12-08
申请号：US13110242
申请日：2011-05-18
申请人： Ho-Seok Seol , Seung-Jun Bae
发明人： Ho-Seok Seol , Seung-Jun Bae
IPC分类号： G05F3/16
CPC分类号： G11C5/147 , G11C11/4074
摘要： An internal voltage generator includes a comparison unit, a driving circuit and a bias unit. The comparison unit compares a reference voltage and an internal voltage and is configured to output a comparison voltage, which is based on a difference between the reference voltage and the internal voltage. The driving circuit receives the comparison voltage and an external power supply voltage and is configured to output the internal voltage to an output node in response to the comparison voltage. The bias unit receives the internal voltage and is configured to adaptively adjust a bias current that flows through the bias unit to drive the comparison unit, in consideration of a level of the internal voltage.
摘要翻译：内部电压发生器包括比较单元，驱动电路和偏置单元。比较单元比较参考电压和内部电压，并且被配置为输出基于参考电压和内部电压之间的差的比较电压。驱动电路接收比较电压和外部电源电压，并且被配置为响应于比较电压将内部电压输出到输出节点。偏置单元接收内部电压，并且被配置为考虑到内部电压的电平，自适应地调节流过偏置单元的偏置电流以驱动比较单元。

8. 发明申请

US20110249513A1 TRANSMITTING/RECEIVING METHODS AND SYSTEMS WITH SIMULTANEOUS SWITCHING NOISE REDUCING PREAMBLES 审中-公开
标题翻译：同时切换噪声的发射/接收方法和系统
公开(公告)号：US20110249513A1
公开(公告)日：2011-10-13
申请号：US13158616
申请日：2011-06-13
申请人： Seung-Jun Bae , Seong-Jin Jang
发明人： Seung-Jun Bae , Seong-Jin Jang
IPC分类号： G11C7/10
CPC分类号： H03M5/145
摘要： DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.
摘要翻译：通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

9. 发明申请

US20110243289A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME 有权
标题翻译：半导体存储器件及其控制方法
公开(公告)号：US20110243289A1
公开(公告)日：2011-10-06
申请号：US13050277
申请日：2011-03-17
申请人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Kwang-Il Park , Seung-Jun Bae
发明人： Ho-Seok Seol , Young-Soo Sohn , Dong-Min Kim , Kwang-Il Park , Seung-Jun Bae
IPC分类号： H04L7/04
CPC分类号： G11C7/22 , G11C7/04 , G11C7/222 , G11C2207/2254
摘要： A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal; determining one of the data pins to be a representative pin; performing clock and data recovery (CDR) on read data of the representative pin; and adjusting a phase of the data clock signal based on the CDR.
摘要翻译：一种对时钟信号的相位进行调谐的方法包括：与数据时钟信号同步地对输入和输出数据的多个数据引脚进行数据训练; 确定一个数据引脚作为代表性引脚; 在代表引脚的读取数据上执行时钟和数据恢复（CDR）; 以及基于所述CDR调整所述数据时钟信号的相位。

10. 发明申请

US20110185219A1 MEMORY DEVICES IMPLEMENTING CLOCK MIRRORING SCHEME AND RELATED MEMORY SYSTEMS AND CLOCK MIRRORING METHODS 有权
公开(公告)号：US20110185219A1
公开(公告)日：2011-07-28
申请号：US13013157
申请日：2011-01-25
申请人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
发明人： Jin-gook Kim , Kwang-il Park , Seung-jun Bae
IPC分类号： G06F1/08
CPC分类号： G11C5/063 , G06F1/10 , G11C7/1045 , G11C7/22 , G11C7/225 , G11C11/4076 , G11C2207/105
摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

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