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21. 发明申请

US20060049084A1 Fluid circuit module and automatic transmission 失效
公开(公告)号：US20060049084A1
公开(公告)日：2006-03-09
申请号：US11213897
申请日：2005-08-30
申请人： Fuminori Suzuki , Hitoshi Tanaka
发明人： Fuminori Suzuki , Hitoshi Tanaka
IPC分类号： B01D35/143
CPC分类号： G05D7/0635 , F16H61/0009 , Y10T137/8326 , Y10T477/60
摘要： A fluid circuit module controls a fluid to be supplied to a movable element in an automatic transmission. The fluid circuit module is provided with a first body in which a first flow passage is formed, a second body in which a second flow passage is formed. A separation plate is set between the first body and the second body and has a deformation portion that is deformed and strained in accordance with the difference between pressures in the first flow passage and the second flow passage. A strain sensor is attached to the deformation portion for detecting a strain of the deformation portion. A control means controls a supply fluid to be supplied to the movable element on the basis of a detection result of the strain sensor.

22. 发明申请

US20050219904A1 Non volatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US20050219904A1
公开(公告)日：2005-10-06
申请号：US11130274
申请日：2005-05-17
申请人： Ryotaro Sakurai , Hitoshi Tanaka , Satoshi Noda , Koji Shigematsu
发明人： Ryotaro Sakurai , Hitoshi Tanaka , Satoshi Noda , Koji Shigematsu
IPC分类号： G11C16/02 , G11C7/00 , G11C11/34 , G11C11/56 , G11C16/00 , G11C16/06 , G11C16/22 , G11C16/30 , G11C16/34
CPC分类号： G11C16/3409 , G11C11/5621 , G11C16/225 , G11C16/30 , G11C16/3404
摘要： An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation.
摘要翻译：一种电可编程和可擦除的非易失性半导体存储器，例如闪速存储器被设计成这样的配置，其中当在非非易失性存储器中使用的存储器单元执行写入或擦除操作的过程中发生电源的截止时，不稳定的半导体存储器，中断正在执行的操作，并且执行回写操作以改变存储单元在相反方向上的阈值电压。此外，该配置还允许根据电源电压的电平来改变内部电源配置中的电荷泵级数，以使回写操作正确执行。结果，即使在写入或擦除操作的过程中电源断开的情况下，也不会将存储器单元置于耗尽状态。

23. 发明授权

US06906871B2 Cam mechanism for lens barrel 失效
标题翻译：镜筒的凸轮机构
公开(公告)号：US06906871B2
公开(公告)日：2005-06-14
申请号：US10731474
申请日：2003-12-10
申请人： Hitoshi Tanaka , Takamitsu Sasaki , Kunihiko Shimizu
发明人： Hitoshi Tanaka , Takamitsu Sasaki , Kunihiko Shimizu
IPC分类号： G02B7/04 , G02B7/10 , G02B15/14
CPC分类号： G02B15/14 , G02B7/102
摘要： A cam mechanism for a lens barrel includes an annular member which is linearly guided along an optical axis, and having a cam follower on an outer peripheral surface; a cam ring having a cam groove on an inner peripheral surface including a photographing section and an accommodation section, the cam follower being engaged in the cam groove; and a biasing device for biasing the annular member forward to normally press the cam follower against a front cam surface in the cam groove. A rear end portion of the cam groove is open at a rear end surface of the cam ring to serve as the accommodation section, and the cam follower is disengageable from the front cam surface in the cam groove against a biasing force of the biasing device when the cam follower is engaged in the accommodation section.
摘要翻译：用于透镜镜筒的凸轮机构包括沿着光轴线性地引导并且在外周面上具有凸轮从动件的环形构件; 凸轮环，其在包括拍摄部分和收纳部分的内周表面上具有凸轮槽，所述凸轮从动件接合在所述凸轮槽中; 以及偏置装置，用于向前偏压环形构件，以正常地将凸轮从动件抵靠在凸轮槽中的前凸轮表面。所述凸轮槽的后端部在所述凸轮环的后端面开口，以作为所述容纳部，并且所述凸轮从动件抵抗所述偏置装置的偏置力而与所述凸轮槽的前凸轮面脱离接触，凸轮从动件接合在容纳部中。

24. 发明授权

US06780699B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06780699B2
公开(公告)日：2004-08-24
申请号：US10359250
申请日：2003-02-06
申请人： Yasuyuki Tamura , Yusuke Morisaki , Yoshihiro Sugita , Kiyoshi Irino , Takayuki Aoyama , Chikako Yoshida , Yoshihiro Sugiyama , Hitoshi Tanaka , Kanetake Takasaki
发明人： Yasuyuki Tamura , Yusuke Morisaki , Yoshihiro Sugita , Kiyoshi Irino , Takayuki Aoyama , Chikako Yoshida , Yoshihiro Sugiyama , Hitoshi Tanaka , Kanetake Takasaki
IPC分类号： H01L218238
CPC分类号： H01L21/823462 , C23C16/401 , H01L21/28194 , H01L21/28202 , H01L21/3144 , H01L21/31604 , H01L21/31612 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A semiconductor device in which the insulation characteristics of an insulating film of multilayer structure including a lower-layer insulating film and a high-dielectric-constant film formed on the lower-layer insulating film are ensured, and a method for fabricating such a semiconductor device. A silicon oxide film or a silicon oxynitride film is formed on a semiconductor substrate as a lower-layer insulating film and part of the lower-layer insulating film is removed. Then a high-dielectric-constant film the dielectric constant of which is higher than that of the lower-layer insulating film is formed on the exposed semiconductor substrate and the lower-layer insulating film. If the lower-layer insulating film is a silicon oxide film, then a metallic compound not including chlorine is used for forming this high-dielectric-constant film. If the lower-layer insulating film is a silicon oxynitride film, then a metallic chloride can be used for forming this high-dielectric-constant film.
摘要翻译：一种半导体器件，其中确保了在下层绝缘膜上形成的包括下层绝缘膜和高介电常数膜的多层结构的绝缘膜的绝缘特性，以及制造这种半导体器件的方法。在作为下层绝缘膜的半导体基板上形成氧化硅膜或氧氮化硅膜，除去下层绝缘膜的一部分。然后在暴露的半导体衬底和下层绝缘膜上形成其介电常数高于下层绝缘膜的介电常数的高介电常数膜。如果下层绝缘膜是氧化硅膜，则使用不含氯的金属化合物来形成该高介电常数膜。如果下层绝缘膜是氮氧化硅膜，则可以使用金属氯化物来形成该高介电常数膜。

25. 发明授权

US06609236B2 Semiconductor IC device having a memory and a logic circuit implemented with a single chip 有权
公开(公告)号：US06609236B2
公开(公告)日：2003-08-19
申请号：US09964615
申请日：2001-09-28
申请人： Takao Watanabe , Kazushige Ayukawa , Ryo Fujita , Kazumasa Yanagisawa , Hitoshi Tanaka
发明人： Takao Watanabe , Kazushige Ayukawa , Ryo Fujita , Kazumasa Yanagisawa , Hitoshi Tanaka
IPC分类号： G06F945
CPC分类号： G11C7/02 , G11C7/10 , G11C7/1006 , G11C7/1042 , G11C7/1072 , H01L27/10897
摘要： A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.

26. 发明授权

US06550951B2 Vehicle headlamp 失效
公开(公告)号：US06550951B2
公开(公告)日：2003-04-22
申请号：US10083318
申请日：2002-02-26
申请人： Hitoshi Tanaka , Takafumi Iwama , Toru Takahashi
发明人： Hitoshi Tanaka , Takafumi Iwama , Toru Takahashi
IPC分类号： F21W10102
CPC分类号： B60Q1/0094 , B60Q1/0088 , F21S41/17 , F21S41/192 , F21S41/196 , F21S41/395 , F21S41/435 , F21W2102/00
摘要： A vehicle headlamp including a lighting circuit unit for lighting a discharge bulb, the lighting circuit unit being provided on an exterior surface of the side wall of the lamb body that is located on the inner side of the lamp body with respect to the width direction of a vehicle. An electric supply cord extending from the lighting circuit unit is disposed along the reflecting surface backside portion of a reflector that is installed in the lamp body.

27. 发明授权

US06366506B1 Semiconductor device operating by receiving a plurality of operating voltages 有权
标题翻译：半导体器件通过接收多个工作电压而工作
公开(公告)号：US06366506B1
公开(公告)日：2002-04-02
申请号：US09639742
申请日：2000-08-15
申请人： Hiroyuki Mizuno , Takao Watanabe , Mitsuru Hiraki , Hitoshi Tanaka
发明人： Hiroyuki Mizuno , Takao Watanabe , Mitsuru Hiraki , Hitoshi Tanaka
IPC分类号： G11C700
CPC分类号： G11C5/14 , G11C5/147
摘要： A semiconductor device having a first circuit block supplied with a first operating voltage, a second circuit block supplied with a second operating voltage, a voltage generating circuit for generating a third operating voltage in response to the first operating voltage, and a third circuit block supplied with the third operating voltage. Preferably, the third operating voltage is generated such that the first operating voltage is increased to a fourth operating voltage by a voltage-up converter, and then the fourth operating voltage is dropped to the third operating voltage by a voltage down-converter. Hence, a power supply operating internally stably in spite of use of a relatively fluctuating voltage can be provided even in the case where a power-supply voltage is dropped.
摘要翻译：一种半导体器件，具有提供有第一工作电压的第一电路块，提供有第二工作电压的第二电路块，用于响应于第一工作电压产生第三工作电压的电压产生电路，以及提供的第三电路块具有第三工作电压。优选地，产生第三工作电压，使得通过升压转换器将第一工作电压增加到第四工作电压，然后通过电压下变频器将第四工作电压降至第三工作电压。因此，即使在电源电压下降的情况下，即使使用相对波动的电压也能够内部稳定地工作的电源。

28. 发明授权

US06332203B1 Testing apparatus and method for preventing a disk unit from being damaged 失效
标题翻译：用于防止磁盘单元损坏的测试装置和方法
公开(公告)号：US06332203B1
公开(公告)日：2001-12-18
申请号：US08971920
申请日：1997-11-18
申请人： Hitoshi Tanaka , Masao Kobori , Ikuko Tachibana
发明人： Hitoshi Tanaka , Masao Kobori , Ikuko Tachibana
IPC分类号： G06F1100
CPC分类号： G11B25/043 , G11B5/54 , G11B27/36 , G11B2220/20
摘要： By means of a power-saving function in the information processing device to be tested, the motor in the HDD (Hard Disk Drive) is stopped by the testing program, when the information processing device is transported. Thus, the read/write head in the HDD is automatically set to a safe position.
摘要翻译：通过在要测试的信息处理设备中的省电功能，当信息处理设备被传送时，HDD（硬盘驱动器）中的电机被测试程序停止。因此，HDD中的读/写头被自动设置为安全位置。

29. 发明授权

US06246629B1 Semiconductor IC device having a memory and a logic circuit implemented with a single chip 有权
标题翻译：具有存储器的半导体IC器件和用单个芯片实现的逻辑电路
公开(公告)号：US06246629B1
公开(公告)日：2001-06-12
申请号：US09551878
申请日：2000-04-18
申请人： Takao Watanabe , Kazushige Ayukawa , Ryo Fujita , Kazumasa Yanagisawa , Hitoshi Tanaka
发明人： Takao Watanabe , Kazushige Ayukawa , Ryo Fujita , Kazumasa Yanagisawa , Hitoshi Tanaka
IPC分类号： G11C800
CPC分类号： G11C7/02 , G11C7/10 , G11C7/1006 , G11C7/1042 , G11C7/1072 , H01L27/10897
摘要： A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.
摘要翻译：使用具有预先生成并存储在数据库中的多个I / O线，传输电路模块和逻辑库的存储器芯来设计半导体IC器件。存储器核心和逻辑电路被布置成使得它们的I / O线沿相同的方向延伸。在存储器芯的I / O线和逻辑电路的I / O线之间设置包括多级开关组的传输电路。形成开关组的各级的开关形成在存储器芯的I / O线和逻辑电路的I / O线之间。当开关组的一级或少量阶段被接通时，存储器芯的I / O线和逻辑电路的I / O线导通，从而形成期望的转移模式。存储器芯由诸如放大器模块，存储体模块和电源模块的功能模块的组合构成。在银行模块中布置了彼此独立操作的行系统电路和沿位线方向延伸的多个I / O线。

30. 发明授权

US6091660A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US6091660A
公开(公告)日：2000-07-18
申请号：US376468
申请日：1999-08-18
申请人： Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
发明人： Toshio Sasaki , Yuji Tanaka , Kazumasa Yanagisawa , Hitoshi Tanaka , Jun Sato , Takashi Miyamoto , Mariko Ohtsuka , Satoru Nakanishi , Kazushige Ayukawa , Takao Watanabe
IPC分类号： G11C11/401 , G11C8/00 , G11C8/12 , G11C11/407
CPC分类号： G11C8/12
摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.
摘要翻译：安装成与逻辑电路混合的RAM具有多个存储器垫和为多个存储器垫提供的一个控制电路。分别提供用于分别执行+1或-1算术运算的算术电路，以便对应于相应的存储器垫并且以级联形式电连接。初始级算术电路的输入端被提供地址设定固定地址信号。提供给下一个和后续运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器垫的那些）。与上述每个运算电路相关联地提供的比较器比较了存储器访问时输入的地址信号和地址信号之间的一致性。基于所得到的一致信号来选择相应的存储器垫。

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