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21. 发明申请

US20110063003A1 PHASE AND FREQUENCY DETECTOR WITH OUTPUT PROPORTIONAL TO FREQUENCY DIFFERENCE 有权
标题翻译：相位和频率检测器具有输出比例为频率差异
公开(公告)号：US20110063003A1
公开(公告)日：2011-03-17
申请号：US12813828
申请日：2010-06-11
申请人： Daniel J. Friedman , Alexander V. Rylyakov , José A. Tierno
发明人： Daniel J. Friedman , Alexander V. Rylyakov , José A. Tierno
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03L7/093 , H03L7/1077 , H03L7/1976
摘要： Phase and frequency detectors and techniques are disclosed. For example, apparatus comprises a first circuit for receiving first and second clock signals and for generating at least one signal indicative of a phase difference between the first and second clock signals. The apparatus also comprises a second circuit for receiving the at least one signal generated by the first circuit and, in response to the at least one received signal, generating at least one output signal, wherein a frequency associated with the at least one output signal is proportional to a frequency difference between the first and second clock signals.
摘要翻译：公开了相位和频率检测器和技术。例如，装置包括用于接收第一和第二时钟信号的第一电路，以及用于产生指示第一和第二时钟信号之间的相位差的至少一个信号。该装置还包括第二电路，用于接收由第一电路产生的至少一个信号，并响应于该至少一个接收信号，产生至少一个输出信号，其中与该至少一个输出信号相关的频率为与第一和第二时钟信号之间的频率差成比例。

22. 发明授权

US08222936B2 Phase and frequency detector with output proportional to frequency difference 有权
标题翻译：相位和频率检测器，输出与频率差成比例
公开(公告)号：US08222936B2
公开(公告)日：2012-07-17
申请号：US12813828
申请日：2010-06-11
申请人： Daniel J. Friedman , Alexander V. Rylyakov , José A. Tierno
发明人： Daniel J. Friedman , Alexander V. Rylyakov , José A. Tierno
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03L7/093 , H03L7/1077 , H03L7/1976
摘要： Phase and frequency detectors and techniques are disclosed. For example, apparatus comprises a first circuit for receiving first and second clock signals and for generating at least one signal indicative of a phase difference between the first and second clock signals. The apparatus also comprises a second circuit for receiving the at least one signal generated by the first circuit and, in response to the at least one received signal, generating at least one output signal, wherein a frequency associated with the at least one output signal is proportional to a frequency difference between the first and second clock signals.
摘要翻译：公开了相位和频率检测器和技术。例如，装置包括用于接收第一和第二时钟信号的第一电路，以及用于产生指示第一和第二时钟信号之间的相位差的至少一个信号。该装置还包括第二电路，用于接收由第一电路产生的至少一个信号，并响应于该至少一个接收信号，产生至少一个输出信号，其中与该至少一个输出信号相关的频率为与第一和第二时钟信号之间的频率差成比例。

23. 发明授权

US07822114B2 Decision feedback equalizer using soft decisions 失效
标题翻译：决策反馈均衡器使用软判决
公开(公告)号：US07822114B2
公开(公告)日：2010-10-26
申请号：US11761586
申请日：2007-06-12
申请人： John F. Bulzacchelli , Daniel J. Friedman , Alexander Rylyakov , Koon Lun Jackie Wong
发明人： John F. Bulzacchelli , Daniel J. Friedman , Alexander Rylyakov , Koon Lun Jackie Wong
IPC分类号： H03H7/30
CPC分类号： H04L25/03057 , H04L25/067 , H04L2025/0349
摘要： A decision feedback equalizer (DFE) and method include at least two paths. Each path includes the following. An adder is configured to sum an input with a first feedback tap fed back from a different path. A latch is coupled to the adder to receive a summation signal as input. The latch includes a transparent state, and an output of the latch is employed as the first tap in a feedback path to an adder of a different path, wherein a partially resolved first tap in the feedback path is employed during the transparent state to provide a soft decision to supply correction information in advance of a hard decision of the latch.
摘要翻译：决策反馈均衡器（DFE）和方法包括至少两个路径。每个路径包括以下内容。加法器被配置为将输入与从不同路径反馈的第一反馈分接相加。锁存器耦合到加法器以接收加法信号作为输入。锁存器包括透明状态，并且锁存器的输出被用作到到不同路径的加法器的反馈路径中的第一抽头，其中在透明状态期间采用反馈路径中的部分分辨的第一抽头以提供一个软判决在锁存器的硬判决之前提供校正信息。

24. 发明申请

US20120153910A1 DUAL-LOOP VOLTAGE REGULATOR ARCHITECTURE WITH HIGH DC ACCURACY AND FAST RESPONSE TIME 有权
标题翻译：具有高直流精度和快速响应时间的双环电压调节器架构
公开(公告)号：US20120153910A1
公开(公告)日：2012-06-21
申请号：US13213578
申请日：2011-08-19
申请人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
发明人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.
摘要翻译：双环路电压调节器电路和方法，其中使用具有爆轰电压调节器的第一内环实现双回路电压调节框架以实现几乎瞬时的响应时间，以及第二外环，其操作速度较慢比第一个内环，可控地调节砰砰电压调节器的跳闸点，以实现高直流精度。

25. 发明申请

US20080310495A1 DECISION FEEDBACK EQUALIZER USING SOFT DECISIONS 失效
标题翻译：决策反馈平均使用软决策
公开(公告)号：US20080310495A1
公开(公告)日：2008-12-18
申请号：US11761586
申请日：2007-06-12
申请人： John F. Bulzacchelli , Daniel J. Friedman , Alexander Rylyakov , Koon Lun Jackie Wong
发明人： John F. Bulzacchelli , Daniel J. Friedman , Alexander Rylyakov , Koon Lun Jackie Wong
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L25/067 , H04L2025/0349
摘要： A decision feedback equalizer (DFE) and method include at least two paths. Each path includes the following. An adder is configured to sum an input with a first feedback tap fed back from a different path. A latch is coupled to the adder to receive a summation signal as input. The latch includes a transparent state, and an output of the latch is employed as the first tap in a feedback path to an adder of a different path, wherein a partially resolved first tap in the feedback path is employed during the transparent state to provide a soft decision to supply correction information in advance of a hard decision of the latch.
摘要翻译：决策反馈均衡器（DFE）和方法包括至少两个路径。每个路径包括以下内容。加法器被配置为将输入与从不同路径反馈的第一反馈分接相加。锁存器耦合到加法器以接收加法信号作为输入。锁存器包括透明状态，并且锁存器的输出被用作到到不同路径的加法器的反馈路径中的第一抽头，其中在透明状态期间采用反馈路径中的部分分辨的第一抽头以提供一个软判决在锁存器的硬判决之前提供校正信息。

26. 发明授权

US08774228B2 Timing recovery method and apparatus for an input/output bus with link redundancy 有权
标题翻译：具有链路冗余的输入/输出总线的定时恢复方法和装置
公开(公告)号：US08774228B2
公开(公告)日：2014-07-08
申请号：US13157968
申请日：2011-06-10
申请人： John F. Bulzacchelli , Timothy O. Dickson , Daniel J. Friedman , Yong Liu , Sergey V. Rylov
发明人： John F. Bulzacchelli , Timothy O. Dickson , Daniel J. Friedman , Yong Liu , Sergey V. Rylov
IPC分类号： H04J3/06
CPC分类号： H04L7/10 , H04L7/0337
摘要： Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time.
摘要翻译：提供了用于具有链路冗余的输入/输出总线的定时恢复的方法和装置。并行输入/输出接口接收器包括多个数据接收器，每个数据接收器被配置为分别从n + m个通道中的相应一个通道接收输入数据，其中n是大于1的整数，并且m是大于或等于1的整数。输入数据是n个通道的非校准数据，是m个通道的校准数据。接口接收器还包括第一相位调节器，其被配置为向多个数据接收器提供第一时钟信号，用于在任何给定时间仅对非校准数据进行采样，以及第二相位调整器，被配置为向第多个数据接收器，用于在任何给定时间仅对校准数据进行采样。

27. 发明申请

US20120153909A1 HYBRID FAST-SLOW PASSGATE CONTROL METHODS FOR VOLTAGE REGULATORS EMPLOYING HIGH SPEED COMPARATORS 审中-公开
标题翻译：采用高速比较器的电压调节器的混合快速低通控制方法
公开(公告)号：US20120153909A1
公开(公告)日：2012-06-21
申请号：US13213368
申请日：2011-08-19
申请人： William L. Bucossi , John F. Bulzacchelli , Mohak Chhabra , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
发明人： William L. Bucossi , John F. Bulzacchelli , Mohak Chhabra , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
IPC分类号： G05F1/10
CPC分类号： H02M3/1563 , H02M1/15 , H02M2003/1566
摘要： Voltage regulator circuits and methods implementing hybrid fast-slow passgate control circuitry are provided to minimize the ripple amplitude of a regulated voltage output. In one aspect, a voltage regulator circuit includes a comparator, a first passgate device, a second passgate device, and a bandwidth limiting control circuit. The comparator compares a reference voltage to a regulated voltage at an output node of the voltage regulator circuit and generates a first control signal on a first gate control path based on a result of the comparing. The first and second passgate devices are connected to the output node of the regulator circuit. The first passgate device is controlled in a bang-bang mode of operation by the first control signal to supply current to the output node. The bandwidth limiting control circuit has an input connected to the first gate control path and an output connected to the second passgate device. The bandwidth limiting control circuit generates a second control signal based on the first control signal, wherein the second control signal is a slew rate limited version of the first control signal, and wherein the second passgate is controlled by the second control signal to supply current to the output node.
摘要翻译：提供了实现混合快速慢门控制电路的稳压器电路和方法，以最小化稳压电压输出的纹波幅度。在一个方面，电压调节器电路包括比较器，第一通道门，第二通道器件和带宽限制控制电路。比较器将参考电压与调节器电路的输出节点处的调节电压进行比较，并且基于比较的结果在第一门控制路径上产生第一控制信号。第一和第二传递门装置连接到调节器电路的输出节点。第一传递门装置通过第一控制信号被控制在爆炸操作模式中，以向输出节点提供电流。带宽限制控制电路具有连接到第一门控制路径的输入端和连接到第二通道门装置的输出端。带宽限制控制电路基于第一控制信号产生第二控制信号，其中第二控制信号是第一控制信号的转换速率限制版本，并且其中第二传递门由第二控制信号控制以将电流提供给输出节点。

28. 发明授权

US08841893B2 Dual-loop voltage regulator architecture with high DC accuracy and fast response time 有权
标题翻译：双回路稳压器架构，具有高直流精度和响应时间快
公开(公告)号：US08841893B2
公开(公告)日：2014-09-23
申请号：US13213578
申请日：2011-08-19
申请人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
发明人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
IPC分类号： G05F1/575
CPC分类号： G05F1/575
摘要： Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.
摘要翻译：双环路电压调节器电路和方法，其中使用具有爆轰电压调节器的第一内环实现双回路电压调节框架以实现几乎瞬时的响应时间，以及第二外环，其操作速度较慢比第一个内环，可控地调节砰砰电压调节器的跳闸点，以实现高直流精度。

29. 发明申请

US20120314721A1 TIMING RECOVERY METHOD AND APPARATUS FOR AN INPUT/OUTPUT BUS WITH LINK REDUNDANCY 有权
标题翻译：具有链路冗余的输入/输出总线的时序恢复方法和装置
公开(公告)号：US20120314721A1
公开(公告)日：2012-12-13
申请号：US13157968
申请日：2011-06-10
申请人： JOHN F. BULZACCHELLI , Timothy O. Dickson , Daniel J. Friedman , Yong Liu , Sergey V. Rylov
发明人： JOHN F. BULZACCHELLI , Timothy O. Dickson , Daniel J. Friedman , Yong Liu , Sergey V. Rylov
IPC分类号： H04L7/00 , H04J3/06
CPC分类号： H04L7/10 , H04L7/0337
摘要： Methods and apparatus are provided for timing recovery for an input/output bus with link redundancy. A parallel input/output interface receiver includes a plurality of data receivers, each configured to respectively receive input data from a respective one of n+m channels, where n is an integer greater than one and m is an integer greater than or equal to one. The input data is non-calibration data for the n channels and is calibration data for the m channels. The interface receiver further includes a first phase adjustor configured to provide a first clock signal to the plurality of data receivers for sampling of only the non-calibration data at any given time, and a second phase adjustor configured to provide a second clock signal to the plurality of data receivers for sampling of only the calibration data at any given time.
摘要翻译：提供了用于具有链路冗余的输入/输出总线的定时恢复的方法和装置。并行输入/输出接口接收器包括多个数据接收器，每个数据接收器被配置为分别从n + m个通道中的相应一个通道接收输入数据，其中n是大于1的整数，并且m是大于或等于1的整数。输入数据是n个通道的非校准数据，是m个通道的校准数据。接口接收器还包括第一相位调节器，其被配置为向多个数据接收器提供第一时钟信号，用于在任何给定时间仅对非校准数据进行采样，以及第二相位调整器，被配置为向第多个数据接收器，用于在任何给定时间仅对校准数据进行采样。

30. 发明授权

US09203159B2 Phased-array transceiver 有权
标题翻译：相控阵收发器
公开(公告)号：US09203159B2
公开(公告)日：2015-12-01
申请号：US13371924
申请日：2012-02-13
申请人： Daniel J. Friedman , Xiaoxiong Gu , Duixian Liu , Arun S. Natarajan , Scott K. Reynolds , Alberto Valdes Garcia
发明人： Daniel J. Friedman , Xiaoxiong Gu , Duixian Liu , Arun S. Natarajan , Scott K. Reynolds , Alberto Valdes Garcia
IPC分类号： H01Q1/24 , H01Q21/06
CPC分类号： H01Q21/061 , H01L2224/16225 , H01Q21/065 , H01Q23/00 , H04B7/04 , Y10T29/49016
摘要： Systems, methods, devices and apparatuses directed to transceiver devices are disclosed. In accordance with one method, a first set of antenna positions in a first section of a set of sections of a circuit layout for the circuit package is selected. The method further includes selecting another set of antenna positions in another section of the circuit layout such that an arrangement of selected antenna positions of the other set is different from an arrangement of selected antenna positions of a previously selected set of antenna positions. The selecting another set of positions in another section is iterated until selections have been made for a total number of antennas. The selecting the other set is performed such that consecutive unselected positions in the other section do not exceed a predetermined number of positions. In addition, antenna elements are formed at the selected positions to fabricate the circuit package.
摘要翻译：公开了针对收发器设备的系统，方法，设备和设备。根据一种方法，选择电路封装的电路布局的一组部分的第一部分中的第一组天线位置。该方法还包括在电路布局的另一部分中选择另一组天线位置，使得另一组的所选择的天线位置的布置与先前选择的一组天线位置的选定天线位置的布置不同。迭代在另一部分中选择另一组位置，直到对天线总数进行选择。执行另一组的选择，使得另一部分中的连续未选定位置不超过预定数量的位置。此外，天线元件形成在所选择的位置以制造电路封装。

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