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1. 发明授权

US08681839B2 Calibration of multiple parallel data communications lines for high skew conditions 失效
标题翻译：多个并行数据通信线路的校准用于高偏斜条件
公开(公告)号：US08681839B2
公开(公告)日：2014-03-25
申请号：US12912883
申请日：2010-10-27
申请人： John F. Bulzacchelli , Timothy O. Dickson , Frank D. Ferraiolo , Robert J. Reese , Michael B. Spear
发明人： John F. Bulzacchelli , Timothy O. Dickson , Frank D. Ferraiolo , Robert J. Reese , Michael B. Spear
IPC分类号： H04B1/38 , H04L5/16
CPC分类号： H04L25/14 , G06F2213/0038 , H04L7/0025 , H04L7/0337
摘要： A parallel data link includes a redundant line. A bank of switches permits any arbitrary line of the link to be enabled or disabled for carrying functional data, each line being dynamically calibrated in turn by disabling the line and allowing other lines to carry the functional data. The switches are located downstream of alignment mechanisms so that data input to the switches is compensated for data skew. Preferably, receiver synchronization circuitry in each line operates in a respective independent clock domain, while the switches and calibration mechanism operate in a common clock domain. Preferably, the receiver synchronization circuits provide an adjustable delay corresponding to a variable number of clock cycles to align the outputs of the receiver synchronization circuits with respect to one another, which can accommodate high data skew.
摘要翻译：并行数据链路包括冗余线路。一组交换机允许链路的任意任意行被启用或禁用以承载功能数据，每行通过禁用线路并允许其他线路携带功能数据依次被动态地校准。开关位于对准机构的下游，以便数据输入到开关的数据偏移。优选地，每行中的接收器同步电路在相应的独立时钟域中操作，而开关和校准机构在公共时钟域中操作。优选地，接收机同步电路提供对应于可变数量的时钟周期的可调节延迟，以使接收机同步电路的输出相对于彼此对准，这可以适应高数据偏移。

2. 发明授权

US08558597B2 High-resolution phase interpolators 有权
公开(公告)号：US08558597B2
公开(公告)日：2013-10-15
申请号：US13538621
申请日：2012-06-29
申请人： Ankur Agrawal , John F. Bulzacchelli , Sergey V. Rylov
发明人： Ankur Agrawal , John F. Bulzacchelli , Sergey V. Rylov
IPC分类号： H03H11/16
CPC分类号： H04L25/03878 , H03K5/135 , H03K2005/00052 , H03K2005/00065 , H04L27/01
摘要： A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

3. 发明申请

US20130215954A1 ANALOG SIGNAL CURRENT INTEGRATORS WITH TUNABLE PEAKING FUNCTION 有权
标题翻译：具有可调峰值功能的模拟信号电流积分器
公开(公告)号：US20130215954A1
公开(公告)日：2013-08-22
申请号：US13399675
申请日：2012-02-17
申请人： Troy J. Beukema , John F. Bulzacchelli
发明人： Troy J. Beukema , John F. Bulzacchelli
IPC分类号： H04L27/01 , H03F3/45
CPC分类号： G06G7/184 , H03F3/45098 , H03F2203/45296 , H03F2203/45298 , H03F2203/45374 , H03F2203/45466 , H03F2203/45616 , H03F2203/45618 , H04L25/0296 , H04L25/03885
摘要： Analog signal current integrators are provided having tunable peaking functions. Analog signal current integrators with tunable peaking functions enable data rate dependent loss compensation for applications in high data rate receiver integrated circuits incorporating advanced equalization functions, such as decision-feedback equalizers. For instance, a current integrator circuit includes a current integrating amplifier circuit comprising an adjustable circuit element to tune a peaking response of the current integrator circuit, and a peaking control circuit to generate a control signal to adjust a value of the adjustable circuit element as a function of an operating condition of the current integrator circuit. The operating condition may be a specified data rate or a communication channel characteristic or both. The adjustable circuit element may be a degeneration capacitor or a bias current source.
摘要翻译：模拟信号电流积分器具有可调峰值功能。具有可调谐峰值功能的模拟信号电流积分器可实现数据速率相关的损耗补偿，适用于包含高级均衡功能的高数据速率接收机集成电路中的应用，如决策反馈均衡器。例如，电流积分器电路包括电流积分放大器电路，该电流积分放大器电路包括调整电路元件以调节电流积分器电路的峰值响应，以及峰值控制电路，用于产生控制信号，以将可调节电路元件的值调整为当前积分器电路的工作状态的功能。操作条件可以是指定的数据速率或通信信道特性，也可以是两者。可调电路元件可以是退化电容器或偏置电流源。

4. 发明申请

US20130207708A1 HIGH-RESOLUTION PHASE INTERPOLATORS 有权
标题翻译：高分辨率相位插件
公开(公告)号：US20130207708A1
公开(公告)日：2013-08-15
申请号：US13538621
申请日：2012-06-29
申请人： Ankur Agrawal , John F. Bulzacchelli , Sergey V. Rylov
发明人： Ankur Agrawal , John F. Bulzacchelli , Sergey V. Rylov
IPC分类号： H03K5/13
CPC分类号： H04L25/03878 , H03K5/135 , H03K2005/00052 , H03K2005/00065 , H04L27/01
摘要： A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.
摘要翻译：提供了相位插值器电路，其通过在第一和第二时钟信号的相位之间进行内插来产生输出时钟信号。通过检测第一时钟信号的边沿并施加第一电流来将输出节点的电容充电至小于或等于电压比较器的切换阈值的电压电平，并且检测第第二时钟信号，并且施加第二电流以将输出节点的电容充电到超过电压比较器的切换阈值的电压电平。改变第一电流的大小以调节输出节点的电容被充电到超过电压比较器的切换阈值的电压电平的时刻，并调整从电压比较器输出的输出时钟信号的相位。

5. 发明申请

US20130207707A1 HIGH-RESOLUTION PHASE INTERPOLATORS 有权
公开(公告)号：US20130207707A1
公开(公告)日：2013-08-15
申请号：US13538276
申请日：2012-06-29
申请人： Ankur Agrawal , John F. Bulzacchelli , Sergey V. Rylov
发明人： Ankur Agrawal , John F. Bulzacchelli , Sergey V. Rylov
IPC分类号： H03K5/13
CPC分类号： H04L25/03878 , H03K5/135 , H03K2005/00052 , H03K2005/00065 , H04L27/01
摘要： A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

6. 发明申请

US20120153910A1 DUAL-LOOP VOLTAGE REGULATOR ARCHITECTURE WITH HIGH DC ACCURACY AND FAST RESPONSE TIME 有权
标题翻译：具有高直流精度和快速响应时间的双环电压调节器架构
公开(公告)号：US20120153910A1
公开(公告)日：2012-06-21
申请号：US13213578
申请日：2011-08-19
申请人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
发明人： John F. Bulzacchelli , Carrie E. Cox , Zeynep Toprak-Deniz , Daniel J. Friedman , Joseph A. Iadanza , Todd M. Rasmus
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： Dual-loop voltage regulator circuits and methods in which a dual-loop voltage regulation framework is implemented with a first inner loop having a bang-bang voltage regulator to achieve nearly instantaneous response time, and a second outer loop, which is slower in operating speed than the first inner loop, to controllably adjust a trip point of the bang-bang voltage regulator to achieve high DC accuracy.
摘要翻译：双环路电压调节器电路和方法，其中使用具有爆轰电压调节器的第一内环实现双回路电压调节框架以实现几乎瞬时的响应时间，以及第二外环，其操作速度较慢比第一个内环，可控地调节砰砰电压调节器的跳闸点，以实现高直流精度。

7. 发明授权

US08138840B2 Optimal dithering of a digitally controlled oscillator with clock dithering for gain and bandwidth control 有权
标题翻译：具有时钟抖动的数字控制振荡器的最佳抖动，用于增益和带宽控制
公开(公告)号：US08138840B2
公开(公告)日：2012-03-20
申请号：US12358736
申请日：2009-01-23
申请人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , John F. Bulzacchelli , Zeynep Toprak Deniz , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/085 , H03L7/089
CPC分类号： H03L7/081 , H03L7/085 , H03L7/099
摘要： A digital phase locked loop (DPLL) and method include an adjustable delay line configured to receive a reference clock as an input and to output a dithered reference clock signal. A phase and frequency detector (PFD) is configured to compare the dithered reference clock signal with a feedback clock signal to determine phase and frequency differences between the dithered reference clock signal and the feedback clock signal. A digitally controlled oscillator (DCO) is configured to receive early or late determinations from the PFD to adjust an output in accordance therewith, wherein the dithered reference clock signal distributes jitter response to enhance overall operation of the DPLL.
摘要翻译：数字锁相环（DPLL）和方法包括可调延迟线，其配置为接收参考时钟作为输入并输出抖动参考时钟信号。相位和频率检测器（PFD）被配置为将抖动参考时钟信号与反馈时钟信号进行比较，以确定抖动参考时钟信号和反馈时钟信号之间的相位和频率差。数字控制振荡器（DCO）被配置为接收来自PFD的早期或晚期确定以根据其调整输出，其中抖动参考时钟信号分配抖动响应以增强DPLL的整体操作。

8. 发明申请

US20090252215A1 SAMPLED CURRENT-INTEGRATING DECISION FEEDBACK EQUALIZER AND METHOD 有权
标题翻译：采样电流一体化决策反馈均衡器和方法
公开(公告)号：US20090252215A1
公开(公告)日：2009-10-08
申请号：US12061268
申请日：2008-04-02
申请人： John F. Bulzacchelli , Timothy O. Dickson , Daniel J. Friedman , Alexander V. Rylyakov
发明人： John F. Bulzacchelli , Timothy O. Dickson , Daniel J. Friedman , Alexander V. Rylyakov
IPC分类号： H04L27/01
CPC分类号： H04L25/03019 , H04L25/03031
摘要： A decision feedback equalizer (DFE) and method including a branch coupled to an input and including a sample-and-hold element configured to receive and sample a received input signal from the input and a current-integrating summer. The current-integrating summer is coupled to an output of the sample-and-hold element. The summer is configured to receive and sum currents representing at least one previous decision and an input sample. The at least one previous decision and the input sample are integrated onto a node, wherein the input sample is held constant during an integration period, thereby mitigating the effects of input transitions on an output of the summer.
摘要翻译：一种判决反馈均衡器（DFE）和方法，包括耦合到输入端并包括采样保持元件的分支，所述采样保持元件被配置为从所述输入端接收和采样所接收的输入信号以及电流积分夏令。电流积分加法器与采样保持元件的输出耦合。夏天被配置为接收并且表示至少一个先前决定和输入样本的和电流。至少一个先前的决定和输入样本被集成到节点上，其中输入样本在积分期间保持不变，从而减轻输入转换对夏季输出的影响。

9. 发明申请

US20080310495A1 DECISION FEEDBACK EQUALIZER USING SOFT DECISIONS 失效
标题翻译：决策反馈平均使用软决策
公开(公告)号：US20080310495A1
公开(公告)日：2008-12-18
申请号：US11761586
申请日：2007-06-12
申请人： John F. Bulzacchelli , Daniel J. Friedman , Alexander Rylyakov , Koon Lun Jackie Wong
发明人： John F. Bulzacchelli , Daniel J. Friedman , Alexander Rylyakov , Koon Lun Jackie Wong
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L25/067 , H04L2025/0349
摘要： A decision feedback equalizer (DFE) and method include at least two paths. Each path includes the following. An adder is configured to sum an input with a first feedback tap fed back from a different path. A latch is coupled to the adder to receive a summation signal as input. The latch includes a transparent state, and an output of the latch is employed as the first tap in a feedback path to an adder of a different path, wherein a partially resolved first tap in the feedback path is employed during the transparent state to provide a soft decision to supply correction information in advance of a hard decision of the latch.
摘要翻译：决策反馈均衡器（DFE）和方法包括至少两个路径。每个路径包括以下内容。加法器被配置为将输入与从不同路径反馈的第一反馈分接相加。锁存器耦合到加法器以接收加法信号作为输入。锁存器包括透明状态，并且锁存器的输出被用作到到不同路径的加法器的反馈路径中的第一抽头，其中在透明状态期间采用反馈路径中的部分分辨的第一抽头以提供一个软判决在锁存器的硬判决之前提供校正信息。

10. 发明授权

US08633764B2 Restoring output common-mode of amplifier via capacitive coupling 失效
标题翻译：通过电容耦合恢复放大器的输出共模
公开(公告)号：US08633764B2
公开(公告)日：2014-01-21
申请号：US13157957
申请日：2011-06-10
申请人： Ankur Agrawal , John F. Bulzacchelli , Thomas H. Toifl
发明人： Ankur Agrawal , John F. Bulzacchelli , Thomas H. Toifl
IPC分类号： H03F3/00
CPC分类号： H03F3/211 , H03F3/45183 , H03F3/45197 , H03F3/45632 , H03F2200/264 , H03F2203/45681
摘要： An apparatus comprises an amplifier circuit comprising at least one output node and a common-mode restoration circuit capacitively coupled to the at least one output node of the amplifier circuit. The common-mode restoration circuit is configured to introduce at least one common-mode restoring signal onto the output node, wherein the at least one common-mode restoring signal transitions in correspondence with an operation interval of the amplifier circuit and thereby compensates for a common-mode voltage drop on the at least one output node of the amplifier circuit. In one example, the amplifier circuit may comprise a current-integrating amplifier circuit, and the operation interval may comprise an integration interval.
摘要翻译：一种装置包括放大器电路，其包括至少一个输出节点和电容耦合到放大器电路的至少一个输出节点的共模恢复电路。共模恢复电路被配置为将至少一个共模恢复信号引入到输出节点上，其中至少一个共模恢复信号与放大器电路的操作间隔对应地转变，从而补偿公共 - 放大器电路的至少一个输出节点上的模式电压降。在一个示例中，放大器电路可以包括电流积分放大器电路，并且操作间隔可以包括积分间隔。

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