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21. 发明申请

US20110314259A1 OPERATING A STACK OF INFORMATION IN AN INFORMATION HANDLING SYSTEM 有权
标题翻译：在信息处理系统中操作信息堆栈
公开(公告)号：US20110314259A1
公开(公告)日：2011-12-22
申请号：US12817609
申请日：2010-06-17
申请人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , IL Park
发明人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , IL Park
IPC分类号： G06F9/30
CPC分类号： G06F9/30 , G06F9/30134 , G06F9/30163 , G06F9/3861
摘要： A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to a second location within the stack as being the next-to-read location; and the information is written for storage at the second location. For popping the information from the stack: in response to the pointer, the information is read from the second location as the next-to-read location; and the pointer is restored to equal the saved value so that it points to the first location as being the next-to-read location.
摘要翻译：一个指针用于指向一堆信息中的下一个读取位置。将信息推送到堆栈中：保存指针的值，该指针指向堆栈内的第一个位置作为下一个读取位置; 指针被更新，使得它指向堆栈内的第二位置作为下一个读取位置; 并且将信息写入第二位置处的存储。为了从堆栈弹出信息：响应于指针，从第二位置读取信息作为下一个读取位置; 并且指针被恢复为等于保存的值，使得其指向作为下一个读取位置的第一位置。

22. 发明授权

US07877586B2 Branch target address cache selectively applying a delayed hit 有权
标题翻译：分支目标地址缓存有选择地应用延迟命中
公开(公告)号：US07877586B2
公开(公告)日：2011-01-25
申请号：US12024190
申请日：2008-02-01
申请人： David S. Levitan , Lixin Zhang
发明人： David S. Levitan , Lixin Zhang
IPC分类号： G06F9/32 , G06F9/42
CPC分类号： G06F9/3806 , G06F9/3844 , G06F9/3869
摘要： In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including branch target address prediction circuitry that stores a branch target address prediction associating a first instruction fetch address with a branch target address to be used as a second instruction fetch address. The branch target address prediction circuitry includes delay logic that, in response to at least a tag portion of a third instruction fetch address matching the first instruction fetch address, delays access to the memory system utilizing the second instruction fetch address if no branch target address prediction was made in an immediately previous cycle of operation.
摘要翻译：在至少一个实施例中，处理器包括至少一个执行单元，其执行耦合到所述至少一个执行单元的指令和指令排序逻辑，所述指令和指令排序逻辑从存储器系统取出用于由所述至少一个执行单元执行的指令。指令排序逻辑包括分支目标地址预测电路，其存储将第一指令取出地址与要用作第二指令取出地址的分支目标地址相关联的分支目标地址预测。分支目标地址预测电路包括延迟逻辑，响应于与第一指令获取地址匹配的第三指令获取地址的至少一个标签部分，如果没有分支目标地址预测，则使用第二指令获取地址延迟对存储器系统的访问是在上一个操作循环中进行的。

23. 发明授权

US07865705B2 Branch target address cache including address type tag bit 有权
标题翻译：分支目标地址缓存包括地址类型标签位
公开(公告)号：US07865705B2
公开(公告)日：2011-01-04
申请号：US12024203
申请日：2008-02-01
申请人： David S. Levitan , Lixin Zhang
发明人： David S. Levitan , Lixin Zhang
IPC分类号： G06F9/35 , G06F9/355
CPC分类号： G06F9/3806 , G06F9/30094 , G06F9/3013 , G06F9/30174 , G06F9/3802 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3844 , G06F9/3889
摘要： In at least one embodiment, a processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a branch target address prediction circuitry concurrently holding a first entry providing storage for a first branch target address prediction associating a first instruction fetch address with a first branch target address to be used as an instruction fetch address and a second entry providing storage for a second branch target address prediction associating the first instruction fetch address with a different second branch target address. The first entry indicates a first instruction address type for the first instruction fetch address, and the second entry indicates a second instruction address type for the first instruction fetch address.
摘要翻译：在至少一个实施例中，处理器包括执行单元和指令排序逻辑，其从存储器系统中取出指令以供执行单元执行。指令排序逻辑包括分支逻辑，该分支逻辑输出用作指令获取地址的预测分支目标地址。分支逻辑包括分支目标地址预测电路，同时保持提供用于第一分支目标地址预测的存储的第一条目，其中第一分支目标地址预测将第一指令获取地址与要用作指令获取地址的第一转移目标地址相关联，以及第二条目提供存储用于将第一指令提取地址与不同的第二分支目标地址相关联的第二分支目标地址预测。第一条目指示第一指令获取地址的第一指令地址类型，第二条目指示第一指令提取地址的第二指令地址类型。

24. 发明申请

US20090198985A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING BRANCH TARGET ADDRESS CACHE WITH HASHED INDICES 有权
标题翻译：数据处理系统，具有分散目标地址缓存的数据处理器和数据处理方法
公开(公告)号：US20090198985A1
公开(公告)日：2009-08-06
申请号：US12024219
申请日：2008-02-01
申请人： SHELDON B. LEVENSTEIN , David S. Levitan , Lixin Zhang
发明人： SHELDON B. LEVENSTEIN , David S. Levitan , Lixin Zhang
IPC分类号： G06F9/30
CPC分类号： G06F9/3806 , G06F9/3844
摘要： In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including a branch target address cache (BTAC) including a plurality of entries for storing branch target address predictions. The BTAC includes index logic that selects an entry to access utilizing a BTAC index based upon at least a set of higher order bits of an instruction address and a set of lower order bits of the instruction address.
摘要翻译：在至少一个实施例中，处理器包括至少一个执行单元，其执行耦合到所述至少一个执行单元的指令和指令排序逻辑，所述指令和指令排序逻辑从存储器系统取出用于由所述至少一个执行单元执行的指令。指令排序逻辑包括分支目标地址高速缓存（BTAC），其包括用于存储分支目标地址预测的多个条目。 BTAC包括索引逻辑，其基于指令地址的至少一组较高位和指令地址的较低位的集合来选择使用BTAC索引的访问条目。

25. 发明授权

US07032097B2 Zero cycle penalty in selecting instructions in prefetch buffer in the event of a miss in the instruction cache 失效
标题翻译：在指令高速缓存中发生错误的情况下，在预取缓冲区中选择指令时的零周期损失
公开(公告)号：US07032097B2
公开(公告)日：2006-04-18
申请号：US10422808
申请日：2003-04-24
申请人： Gregory W. Alexander , David S. Levitan , Balaram Sinharoy , William J. Starke
发明人： Gregory W. Alexander , David S. Levitan , Balaram Sinharoy , William J. Starke
IPC分类号： G06F12/00
CPC分类号： G06F9/3802 , G06F9/3814
摘要： A method and processor for selecting instructions in a prefetch buffer in the event of a miss in an instruction cache with a zero cycle penalty. A first, second and third hash may be performed on an address retrieved from a program counter. The first hashed address may be used to index into the instruction cache. The second hashed address may be used to index into the prefetch buffer. If the value stored in the indexed entry in an effective address array of the instruction cache does not equal the value of the third hash of the address (an instruction cache miss), then the instructions in the indexed entry in the prefetch buffer are selected. In this manner, instructions may be selected in the prefetch buffer in the event of a miss in the instruction cache with a zero cycle penalty.
摘要翻译：一种方法和处理器，用于在具有零循环损失的指令高速缓存中的未命中的情况下，在预取缓冲器中选择指令。可以对从程序计数器检索的地址执行第一，第二和第三散列。第一个散列地址可以用于索引到指令高速缓存。第二个散列地址可以用于索引到预取缓冲区。如果存储在指令高速缓存的有效地址阵列中的索引条目中的值不等于地址（指令高速缓存未命中）的第三散列值，则选择预取缓冲器中索引条目中的指令。以这种方式，可以在具有零周期损失的指令高速缓存中的未命中的情况下在预取缓冲器中选择指令。

26. 发明授权

US5421020A Counter register implementation for speculative execution of branch on count instructions 失效
标题翻译：计数器寄存器实现用于推算执行分支计数指令
公开(公告)号：US5421020A
公开(公告)日：1995-05-30
申请号：US2445
申请日：1993-01-08
申请人： David S. Levitan
发明人： David S. Levitan
IPC分类号： G06F9/32 , G06F9/38 , G06F9/22
CPC分类号： G06F9/3863 , G06F9/325
摘要： A data processing system for speculatively executing instructions. The data processing system includes a memory for storing instructions at addresses which can be generated by a branch unit in a processor. The processor also has a count register for storing an update value, a dispatch version value and a completion version value. A fetcher connected to the branch unit fetches instructions from memory based upon addresses calculated by the branch unit. The branch unit handles processing of conditional branch instructions. To do so, means for initializing the update value and the dispatch version value for branch control are provided. Further included are means responsive to completion of initialization for copying the update value as the completion version value. The system further includes means responsive to dispatch of a conditional branch instruction for examining the dispatch version value to determine if a branch should be taken and then decrementing the dispatch version value. Means responsive to completion of the branch provide for decrementing contents of a completion version register. Finally, means responsive to occurrence of an interrupt prior to completion of the branch provide for replacing the dispatch version value with the completion version value to restore the system to a state prior to the speculative execution of instructions.
摘要翻译：用于推测执行指令的数据处理系统。数据处理系统包括用于存储可由处理器中的分支单元生成的地址处的指令的存储器。处理器还具有用于存储更新值，分派版本值和完成版本值的计数寄存器。连接到分支单元的提取器基于由分支单元计算的地址从存储器获取指令。分支单元处理条件分支指令的处理。为此，提供了初始化更新值和分支控制的调度版本值的方法。还包括响应于完成初始化的装置，用于将更新值复制为完成版本值。该系统还包括响应于调度用于检查分派版本值的条件分支指令的装置，以确定是否应该分支，然后减去分派版本值。响应于分支完成的手段提供完成版本寄存器的递减内容。最后，在分支完成之前响应于中断的发生的装置提供用完成版本值替换分派版本值，以将系统恢复到在推测执行指令之前的状态。

27. 发明授权

US08943299B2 Operating a stack of information in an information handling system 有权
标题翻译：在信息处理系统中操作一堆信息
公开(公告)号：US08943299B2
公开(公告)日：2015-01-27
申请号：US12817609
申请日：2010-06-17
申请人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , Il Park
发明人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , Il Park
IPC分类号： G06F9/30
CPC分类号： G06F9/30 , G06F9/30134 , G06F9/30163 , G06F9/3861
摘要： A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to a second location within the stack as being the next-to-read location; and the information is written for storage at the second location. For popping the information from the stack: in response to the pointer, the information is read from the second location as the next-to-read location; and the pointer is restored to equal the saved value so that it points to the first location as being the next-to-read location.
摘要翻译：一个指针用于指向一堆信息中的下一个读取位置。将信息推送到堆栈中：保存指针的值，该指针指向堆栈内的第一个位置作为下一个读取位置; 指针被更新，使得它指向堆栈内的第二位置作为下一个读取位置; 并且将信息写入第二位置处的存储。为了从堆栈弹出信息：响应于指针，从第二位置读取信息作为下一个读取位置; 并且指针被恢复为等于保存的值，使得其指向作为下一个读取位置的第一位置。

28. 发明授权

US08635408B2 Controlling power of a cache based on predicting the instruction cache way for high power applications 有权
标题翻译：基于预测大功率应用的指令高速缓存方式来控制高速缓存的功率
公开(公告)号：US08635408B2
公开(公告)日：2014-01-21
申请号：US12984300
申请日：2011-01-04
申请人： Sheldon B. Levenstein , David S. Levitan
发明人： Sheldon B. Levenstein , David S. Levitan
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F9/3804 , G06F9/3808 , G06F9/381 , G06F12/0882 , G06F2212/1028 , Y02D10/13
摘要： A mechanism for accessing a cache memory is provided. With the mechanism of the illustrative embodiments, a processor of the data processing system performs a first execution a portion of code. During the first execution of the portion of code, information identifying which cache lines in the cache memory are accessed during the execution of the portion of code is stored in a storage device of the data processing system. Subsequently, during a second execution of the portion of code, power to the cache memory is controlled such that only the cache lines that were accessed during the first execution of the portion of code are powered-up.
摘要翻译：提供了用于访问高速缓冲存储器的机制。利用说明性实施例的机制，数据处理系统的处理器执行代码的一部分的第一执行。在代码部分的第一次执行期间，在代码部分的执行期间识别高速缓冲存储器中的哪些高速缓存行被访问的信息被存储在数据处理系统的存储装置中。随后，在代码部分的第二次执行期间，控制对高速缓冲存储器的电力，使得只有在代码部分的第一次执行期间被访问的高速缓存行被加电。

29. 发明授权

US07962722B2 Branch target address cache with hashed indices 有权
标题翻译：具有散列索引的分支目标地址缓存
公开(公告)号：US07962722B2
公开(公告)日：2011-06-14
申请号：US12024219
申请日：2008-02-01
申请人： Sheldon B. Levenstein , David S. Levitan , Lixin Zhang
发明人： Sheldon B. Levenstein , David S. Levitan , Lixin Zhang
IPC分类号： G06F9/32 , G06F9/34
CPC分类号： G06F9/3806 , G06F9/3844
摘要： In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including a branch target address cache (BTAC) including a plurality of entries for storing branch target address predictions. The BTAC includes index logic that selects an entry to access utilizing a BTAC index based upon at least a set of higher order bits of an instruction address and a set of lower order bits of the instruction address.
摘要翻译：在至少一个实施例中，处理器包括至少一个执行单元，其执行耦合到至少一个执行单元的指令和指令排序逻辑，其从存储器系统取出用于由至少一个执行单元执行的指令。指令排序逻辑包括分支目标地址高速缓存（BTAC），其包括用于存储分支目标地址预测的多个条目。 BTAC包括索引逻辑，其基于指令地址的至少一组较高位和指令地址的较低位的集合来选择使用BTAC索引的访问条目。

30. 发明授权

US07689816B2 Branch prediction with partially folded global history vector for reduced XOR operation time 失效
标题翻译：具有部分折叠的全局历史矢量的分支预测，用于减少XOR运算时间
公开(公告)号：US07689816B2
公开(公告)日：2010-03-30
申请号：US12023154
申请日：2008-01-31
申请人： David S. Levitan
发明人： David S. Levitan
IPC分类号： G06F9/38
CPC分类号： G06F9/3848
摘要： A global history vector (GHV) mechanism maintains a folded (XORed) GHV with higher order entries and an unfolded (no XORed) GHV with lower order entries. When a new entry arrives at the GHV, the GHV mechanism performs an XOR of the oldest unfolded entry in the unfolded GHV with the new entry. The XOR result is then shifted into the folded GHV as the newest folded entry. The oldest folded entry is discarded during the shift in of the newest folded entry. The GHV mechanism thus provides a resulting folded GHV that is current and can be utilized for XORing with an IFAR by performing an XOR operation. Only a single XOR logic is required to perform a single bit XOR operation between the oldest entry and the youngest entry, resulting in reducing the cycle time required to complete the folding (XORing) operation on a GHV.
摘要翻译：全局历史向量（GHV）机制保持具有更高阶条目的折叠（异或）GHV和具有较低阶条目的展开（无异或）GHV。当新条目到达GHV时，GHV机制使用新条目在展开的GHV中执行最早展开条目的异或。然后将XOR结果作为最新的折叠条目移入折叠的GHV。最旧的折叠条目在最新的折叠条目的移位期间被丢弃。因此，GHV机构提供了一种电流折叠的GHV，并且可以通过执行异或运算来与IFAR进行异或运算。只需要一个XOR逻辑来执行最旧条目和最小条目之间的单个XOR操作，从而减少完成GHV上的折叠（异或）操作所需的周期时间。

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