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1. 发明申请

US20110314259A1 OPERATING A STACK OF INFORMATION IN AN INFORMATION HANDLING SYSTEM 有权
标题翻译：在信息处理系统中操作信息堆栈
公开(公告)号：US20110314259A1
公开(公告)日：2011-12-22
申请号：US12817609
申请日：2010-06-17
申请人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , IL Park
发明人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , IL Park
IPC分类号： G06F9/30
CPC分类号： G06F9/30 , G06F9/30134 , G06F9/30163 , G06F9/3861
摘要： A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to a second location within the stack as being the next-to-read location; and the information is written for storage at the second location. For popping the information from the stack: in response to the pointer, the information is read from the second location as the next-to-read location; and the pointer is restored to equal the saved value so that it points to the first location as being the next-to-read location.
摘要翻译：一个指针用于指向一堆信息中的下一个读取位置。将信息推送到堆栈中：保存指针的值，该指针指向堆栈内的第一个位置作为下一个读取位置; 指针被更新，使得它指向堆栈内的第二位置作为下一个读取位置; 并且将信息写入第二位置处的存储。为了从堆栈弹出信息：响应于指针，从第二位置读取信息作为下一个读取位置; 并且指针被恢复为等于保存的值，使得其指向作为下一个读取位置的第一位置。

2. 发明授权

US08943299B2 Operating a stack of information in an information handling system 有权
标题翻译：在信息处理系统中操作一堆信息
公开(公告)号：US08943299B2
公开(公告)日：2015-01-27
申请号：US12817609
申请日：2010-06-17
申请人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , Il Park
发明人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , Il Park
IPC分类号： G06F9/30
CPC分类号： G06F9/30 , G06F9/30134 , G06F9/30163 , G06F9/3861
摘要： A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to a second location within the stack as being the next-to-read location; and the information is written for storage at the second location. For popping the information from the stack: in response to the pointer, the information is read from the second location as the next-to-read location; and the pointer is restored to equal the saved value so that it points to the first location as being the next-to-read location.
摘要翻译：一个指针用于指向一堆信息中的下一个读取位置。将信息推送到堆栈中：保存指针的值，该指针指向堆栈内的第一个位置作为下一个读取位置; 指针被更新，使得它指向堆栈内的第二位置作为下一个读取位置; 并且将信息写入第二位置处的存储。为了从堆栈弹出信息：响应于指针，从第二位置读取信息作为下一个读取位置; 并且指针被恢复为等于保存的值，使得其指向作为下一个读取位置的第一位置。

3. 发明授权

US08683175B2 Seamless interface for multi-threaded core accelerators 有权
标题翻译：多线程核心加速器的无缝界面
公开(公告)号：US08683175B2
公开(公告)日：2014-03-25
申请号：US13048214
申请日：2011-03-15
申请人： Kattamuri Ekanadham , Hung Q. Le , Jose E. Moreira , Pratap C. Pattnaik
发明人： Kattamuri Ekanadham , Hung Q. Le , Jose E. Moreira , Pratap C. Pattnaik
IPC分类号： G06F9/30 , G06F12/10
CPC分类号： G06F9/3877 , G06F9/30043 , G06F9/3012 , G06F9/30123 , G06F9/3851 , G06F12/1027
摘要： A method, system and computer program product are disclosed for interfacing between a multi-threaded processing core and an accelerator. In one embodiment, the method comprises copying from the processing core to the hardware accelerator memory address translations for each of multiple threads operating on the processing core, and simultaneously storing on the hardware accelerator one or more of the memory address translations for each of the threads. Whenever any one of the multiple threads operating on the processing core instructs the hardware accelerator to perform a specified operation, the hardware accelerator has stored thereon one or more of the memory address translations for the any one of the threads. This facilitates starting that specified operation without memory translation faults. In an embodiment, the copying includes, each time one of the memory address translations is updated on the processing core, copying the updated one of the memory address translations to the hardware accelerator.
摘要翻译：公开了用于在多线程处理核心和加速器之间进行接口的方法，系统和计算机程序产品。在一个实施例中，该方法包括从处理核心复制到在处理核心上操作的多个线程中的每个线程的硬件加速器存储器地址转换，以及同时在硬件加速器上存储每个线程的一个或多个存储器地址转换。只要在处理核心上操作的多个线程中的任何一个指示硬件加速器执行指定的操作，则硬件加速器在其上存储有针对任何一个线程的一个或多个存储器地址转换。这有助于启动指定的操作，而不会出现内存转换错误。在一个实施例中，复制包括每次在处理核心上更新一个存储器地址转换时，将更新的一个存储器地址转换复制到硬件加速器。

4. 发明申请

US20120239904A1 SEAMLESS INTERFACE FOR MULTI-THREADED CORE ACCELERATORS 有权
标题翻译：多线程加速器的无缝接口
公开(公告)号：US20120239904A1
公开(公告)日：2012-09-20
申请号：US13048214
申请日：2011-03-15
申请人： Kattamuri Ekanadham , Hung Q. Le , Jose E. Moreira , Pratap C. Pattnaik
发明人： Kattamuri Ekanadham , Hung Q. Le , Jose E. Moreira , Pratap C. Pattnaik
IPC分类号： G06F9/30 , G06F12/10
CPC分类号： G06F9/3877 , G06F9/30043 , G06F9/3012 , G06F9/30123 , G06F9/3851 , G06F12/1027
摘要： A method, system and computer program product are disclosed for interfacing between a multi-threaded processing core and an accelerator. In one embodiment, the method comprises copying from the processing core to the hardware accelerator memory address translations for each of multiple threads operating on the processing core, and simultaneously storing on the hardware accelerator one or more of the memory address translations for each of the threads. Whenever any one of the multiple threads operating on the processing core instructs the hardware accelerator to perform a specified operation, the hardware accelerator has stored thereon one or more of the memory address translations for the any one of the threads. This facilitates starting that specified operation without memory translation faults. In an embodiment, the copying includes, each time one of the memory address translations is updated on the processing core, copying the updated one of the memory address translations to the hardware accelerator.
摘要翻译：公开了用于在多线程处理核心和加速器之间进行接口的方法，系统和计算机程序产品。在一个实施例中，该方法包括从处理核心复制到在处理核心上操作的多个线程中的每个线程的硬件加速器存储器地址转换，以及同时在硬件加速器上存储每个线程的一个或多个存储器地址转换。只要在处理核心上操作的多个线程中的任何一个指示硬件加速器执行指定的操作，则硬件加速器在其上存储有针对任何一个线程的一个或多个存储器地址转换。这有助于启动指定的操作而不会出现内存转换错误在一个实施例中，复制包括每次在处理核心上更新一个存储器地址转换时，将更新的一个存储器地址转换复制到硬件加速器。

5. 发明申请

US20130019083A1 Redundant Transactional Memory 审中-公开
标题翻译：冗余事务记忆
公开(公告)号：US20130019083A1
公开(公告)日：2013-01-17
申请号：US13179672
申请日：2011-07-11
申请人： Harold W. Cain, III , David M. Daly , Kattamuri Ekanadham , Michael C. Huang , Jose E. Moreira , Mauricio J. Serrano
发明人： Harold W. Cain, III , David M. Daly , Kattamuri Ekanadham , Michael C. Huang , Jose E. Moreira , Mauricio J. Serrano
IPC分类号： G06F9/30
CPC分类号： G06F9/30087 , G06F9/3834 , G06F9/3842 , G06F11/1492 , G06F11/1629 , G06F2201/845
摘要： A mechanism is provided for redundant execution of a set of instructions. A redundant execution begin (rbegin) instruction to be executed by a first hardware thread on the first processor is identified in the set of instructions. The set of instructions immediately after the rbegin instruction are executed on the first hardware thread and on a second hardware thread. Responsive to both the first processor and the second processor ending execution of the set of instructions, responsive to a first set of cache lines in a first speculative store matching a second set of cache lines in a second speculative store, and responsive to a first set of register states in a first status register matching a second set of register states in a second status register, dirty lines in the first speculative store are committed thereby committing a redundant transaction state to an architectural state.
摘要翻译：提供了用于一组指令的冗余执行的机制。在该组指令中识别由第一处理器上的第一硬件线程执行的冗余执行开始（rbegin）指令。 rbegin指令之后的指令集在第一个硬件线程和第二个硬件线程上执行。响应于所述第一处理器和所述第二处理器结束所述指令集的执行，响应于在第二推测存储器中匹配第二组高速缓存行的第一推测存储器中的第一组高速缓存行，并响应于第一集合在与第二状态寄存器中的第二组寄存器状态匹配的第一状态寄存器中的寄存器状态被提交，从而将第一推测存储器中的脏线提交给架构状态的冗余事务状态。

6. 发明申请

US20130019085A1 Efficient Recombining for Dual Path Execution 审中-公开
标题翻译：双路执行的有效重组
公开(公告)号：US20130019085A1
公开(公告)日：2013-01-17
申请号：US13180634
申请日：2011-07-12
申请人： Harold W. Cain, III , David M. Daly , Michael C. Huang , Jose E. Moreira , IL Park
发明人： Harold W. Cain, III , David M. Daly , Michael C. Huang , Jose E. Moreira , IL Park
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3804 , G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F9/3859 , G06F9/3861
摘要： A mechanism is provided for reducing a penalty for executing a correct branch of a branch instruction. An execution unit in a processor of a data processing system executes a first branch of the branch instruction from a main thread of a processor and executes a second branch of the branch instruction from an assist thread of the processor. The execution unit determines whether the main thread is a correct branch of the branch instruction or the assist thread is the correct branch of the branch instruction. Responsive to the assist thread being the correct branch of the branch instruction, the execution unit pauses execution of the branch instruction on both the main thread and the assist thread. The execution unit then properly inherits a context of the main thread in order that execution of the second branch may continue.
摘要翻译：提供了用于减少执行分支指令的正确分支的惩罚的机制。数据处理系统的处理器中的执行单元从处理器的主线程执行分支指令的第一分支，并从处理器的辅助线程执行分支指令的第二分支。执行单元确定主线程是否是分支指令的正确分支，或辅助线程是分支指令的正确分支。响应于辅助线程是分支指令的正确分支，执行单元暂停在主线程和辅助线程上执行分支指令。执行单元然后适当地继承主线程的上下文，以便第二分支的执行可以继续。

7. 发明申请

US20110320765A1 VARIABLE WIDTH VECTOR INSTRUCTION PROCESSOR 审中-公开
标题翻译：可变宽度矢量指示处理器
公开(公告)号：US20110320765A1
公开(公告)日：2011-12-29
申请号：US12825328
申请日：2010-06-28
申请人： Tejas Karkhanis , Jose E. Moreira , Valentina Salapura
发明人： Tejas Karkhanis , Jose E. Moreira , Valentina Salapura
IPC分类号： G06F9/30 , G06F15/76
CPC分类号： G06F9/30112 , G06F9/30014 , G06F9/30036 , G06F9/30109 , G06F9/30123 , G06F9/30141 , G06F9/3851 , G06F15/8076
摘要： A computer processor, method, and computer program product for executing vector processing instructions on a variable width vector register file. An example embodiment is a computer processor that includes an instruction execution unit coupled to a variable width vector register file which contains a number of vector registers, the width of the vector registers is changeable during operation of the computer processor.
摘要翻译：一种用于在可变宽度向量寄存器文件上执行矢量处理指令的计算机处理器，方法和计算机程序产品。示例性实施例是一种计算机处理器，其包括耦合到包含多个向量寄存器的可变宽度向量寄存器文件的指令执行单元，在计算机处理器的操作期间向量寄存器的宽度是可变的。

8. 发明申请

US20110258347A1 COMMUNICATIONS SUPPORT IN A TRANSACTIONAL MEMORY 失效
标题翻译：通信在交易记忆中的支持
公开(公告)号：US20110258347A1
公开(公告)日：2011-10-20
申请号：US12763813
申请日：2010-04-20
申请人： Jose E. Moreira , Patricia M. Sagmeister
发明人： Jose E. Moreira , Patricia M. Sagmeister
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F9/467
摘要： A system, method and computer program product are provided for supporting Transactional Memory communications. In one embodiment, the system comprises a transactional memory host with a host transactional memory buffer, an endpoint device, a transactional memory buffer associated with the endpoint device, and a communication path connecting the endpoint device and host. Input/Output transactions associated with the endpoint device executed in transactional memory on the host are stored in both the host transactional memory buffer and the transactional memory buffer associated with the endpoint device. In an embodiment, the Transactional Memory system further comprises an intermediate device located on the communication path between the host and the endpoint device, and an intermediate transactional memory buffer associated with said intermediate devices. In this embodiment, the Input/Output transactions associated with said endpoint device are stored in the intermediate transactional memory buffer associated with the intermediate device.
摘要翻译：提供了一种用于支持事务性存储器通信的系统，方法和计算机程序产品。在一个实施例中，系统包括具有主机事务存储器缓冲器，端点设备，与端点设备相关联的事务存储器缓冲器以及连接端点设备和主机的通信路径的事务存储器主机。与在主机上的事务性存储器中执行的端点设备相关联的输入/输出事务存储在与端点设备相关联的主机事务存储器缓冲器和事务存储器缓冲器中。在一个实施例中，事务存储器系统还包括位于主机和端点设备之间的通信路径上的中间设备以及与所述中间设备相关联的中间事务存储器缓冲器。在该实施例中，与所述端点设备相关联的输入/输出事务存储在与中间设备相关联的中间事务存储器缓冲器中。

9. 发明申请

US20090282151A1 SEMI-HIERARCHICAL SYSTEM AND METHOD FOR ADMINISTRATION OF CLUSTERS OF COMPUTER RESOURCES 审中-公开
标题翻译：用于管理计算机资源集群的半分层系统和方法
公开(公告)号：US20090282151A1
公开(公告)日：2009-11-12
申请号：US12509368
申请日：2009-07-24
申请人： Myung Mun Bae , Jose E. Moreira , Ramendra Kumar Sahoo
发明人： Myung Mun Bae , Jose E. Moreira , Ramendra Kumar Sahoo
IPC分类号： G06F15/173
CPC分类号： G06F9/5061
摘要： A method for managing clustered computer resources, and particularly very large scale clusters of computer resources by a semi-hierarchical n level, n+1 tier approach. Controller resources and controlled resources exist at different hardware levels. The top level consists of controller nodes and a first tier is defined for at least part of the top level. At a last level, at which controlled nodes are found, a last tier is defined. Additional levels of controlled and controller resources may exist between the top and last levels. At least one logical intermediate tier is introduced between adjacent levels and comprises at least one proxy or set of proxy processes.
摘要翻译：一种用于通过半层次n级，n + 1级方法来管理集群计算机资源的方法，特别是非常大规模的计算机资源集群。控制器资源和受控资源存在于不同的硬件级别。顶层由控制器节点组成，第一层定义为顶层的至少一部分。在最后一级，找到受控节点，定义最后一层。顶级和最后级别之间可能存在附加级别的受控和控制器资源。在相邻级别之间引入至少一个逻辑中间层，并且包括至少一个代理或一组代理进程。

10. 发明申请

US20110296148A1 Transactional Memory System Supporting Unbroken Suspended Execution 有权
标题翻译：支持不间断暂停执行的事务性内存系统
公开(公告)号：US20110296148A1
公开(公告)日：2011-12-01
申请号：US12788351
申请日：2010-05-27
申请人： Harold W. Cain, III , Bradly G. Frey , Benjamin Herrenschmidt , Hung Q. Le , Cathy May , Maged M. Michael , Jose E. Moreira , Priya A. Nagpurkar , Naresh Nayar , Randal C. Swanberg
发明人： Harold W. Cain, III , Bradly G. Frey , Benjamin Herrenschmidt , Hung Q. Le , Cathy May , Maged M. Michael , Jose E. Moreira , Priya A. Nagpurkar , Naresh Nayar , Randal C. Swanberg
IPC分类号： G06F9/312
CPC分类号： G06F9/30087 , G06F9/3004 , G06F9/30189 , G06F9/3834 , G06F9/3842 , G06F9/3859 , G06F9/3863 , G06F9/3865 , G06F9/467
摘要： Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued.
摘要翻译：在具有处理器和事务存储器的数据处理系统中提供用于在数据处理系统中执行事务的机制。这些机制执行包括修改事务存储器的至少一部分的一个或多个指令的事务。响应于由处理器执行的事务挂起指令，事务被暂停。当事务被暂停时，暂停的代码块以非事务方式执行。确定在事务中止时是否发生中断。响应于在事务中止时发生的中断，事务中止操作被延迟，直到事务中止停止为止。

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