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1. 发明授权

US08661230B2 Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions 有权
标题翻译：从计数器池分配计数器，以跟踪逻辑寄存器到物理寄存器的映射，用于基于映射器的指令执行
公开(公告)号：US08661230B2
公开(公告)日：2014-02-25
申请号：US13088298
申请日：2011-04-15
申请人： Gregory W. Alexander , Brian D. Barrick , John W. Ward, III
发明人： Gregory W. Alexander , Brian D. Barrick , John W. Ward, III
IPC分类号： G06F9/30
CPC分类号： G06F9/30098 , G06F9/384
摘要： A mapper unit of an out-of-order processor assigns a particular counter currently in a counter free pool to count a number of mappings of logical registers to a particular physical register from among multiple physical registers, responsive to an execution of an instruction by the mapper unit mapping at least one logical register to the particular physical register. The number of counters is less than the number of physical registers. The mapper unit, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool.
摘要翻译：无序处理器的映射器单元分配当前在计数器可用池中的特定计数器，以响应于由多个物理寄存器执行的指令来计数多个物理寄存器中的逻辑寄存器到多个物理寄存器的数量的映射映射器单元将至少一个逻辑寄存器映射到特定物理寄存器。计数器的数量少于物理寄存器的数量。映射器单元响应于逻辑寄存器对特定物理寄存器的映射的计数数量减少到小于最小值，将特定计数器返回给计数器可用池。

2. 发明授权

US08433855B2 Serializing translation lookaside buffer access around address translation parameter modification 有权
标题翻译：序列化翻译后备缓冲区访问围绕地址转换参数修改
公开(公告)号：US08433855B2
公开(公告)日：2013-04-30
申请号：US12032178
申请日：2008-02-15
申请人： Gregory W. Alexander , Lisa C. Heller , Chung-Lung Kevin Shum
发明人： Gregory W. Alexander , Lisa C. Heller , Chung-Lung Kevin Shum
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/684
摘要： Embodiments of the invention include a method of synchronizing translation changes in a processor including a translation lookaside buffer, the method including setting a control bit to enable blocking of all fetch requests that miss the translation lookaside buffer without changing a translation state of the current process; if there is at least one pending translation, then waiting for completion of the at least one pending translation; and resetting the control bit. A processor and a computer program product are provided.
摘要翻译：本发明的实施例包括一种在包括翻译后备缓冲器的处理器中同步翻译改变的方法，所述方法包括设置控制位以使得能够阻止错过所述翻译后备缓冲器的所有提取请求，而不改变当前进程的转换状态; 如果存在至少一个未完成的翻译，则等待完成至少一个等待翻译; 并重置控制位。提供处理器和计算机程序产品。

3. 发明申请

US20120265971A1 ALLOCATION OF COUNTERS FROM A POOL OF COUNTERS TO TRACK MAPPINGS OF LOGICAL REGISTERS TO PHYSICAL REGISTERS FOR MAPPER BASED INSTRUCTION EXECUTIONS 有权
标题翻译：将计数器从计数器分配到跟踪逻辑寄存器映射到基于MAPPER的指令执行的物理寄存器
公开(公告)号：US20120265971A1
公开(公告)日：2012-10-18
申请号：US13088298
申请日：2011-04-15
申请人： GREGORY W. ALEXANDER , BRIAN D. BARRICK , JOHN W. WARD, III
发明人： GREGORY W. ALEXANDER , BRIAN D. BARRICK , JOHN W. WARD, III
IPC分类号： G06F9/315
CPC分类号： G06F9/30098 , G06F9/384
摘要： A mapper unit of an out-of-order processor assigns a particular counter currently in a counter free pool to count a number of mappings of logical registers to a particular physical register from among multiple physical registers, responsive to an execution of an instruction by the mapper unit mapping at least one logical register to the particular physical register. The number of counters is less than the number of physical registers. The mapper unit, responsive to the counted number of mappings of logical registers to the particular physical register decremented to less than a minimum value, returns the particular counter to the counter free pool.
摘要翻译：无序处理器的映射器单元分配当前在计数器可用池中的特定计数器，以响应于由多个物理寄存器执行的指令来计数多个物理寄存器中的逻辑寄存器到多个物理寄存器的数量的映射映射器单元将至少一个逻辑寄存器映射到特定物理寄存器。计数器的数量少于物理寄存器的数量。映射器单元响应于逻辑寄存器对特定物理寄存器的映射的计数数量减少到小于最小值，将特定计数器返回给计数器可用池。

4. 发明授权

US08082467B2 Triggering workaround capabilities based on events active in a processor pipeline 有权
标题翻译：根据处理器管道中活动的事件触发解决方法的功能
公开(公告)号：US08082467B2
公开(公告)日：2011-12-20
申请号：US12645771
申请日：2009-12-23
申请人： Gregory W. Alexander , Fadi Busaba , David A. Schroter , Eric Schwarz , Brian W. Thompto , Wesley J. Ward, III
发明人： Gregory W. Alexander , Fadi Busaba , David A. Schroter , Eric Schwarz , Brian W. Thompto , Wesley J. Ward, III
IPC分类号： G06F11/00
CPC分类号： G06F9/30145 , G06F9/30189 , G06F9/3853 , G06F9/3861 , G06F9/3867 , G06F11/004 , G06F11/0721 , G06F11/0724 , G06F11/0751 , G06F11/0793
摘要： A novel system and method for working around a processing flaw in a processor is disclosed. At least one instruction is fetched from a memory location. The instruction is decoded. A set of opcode compare logic, associated with an instruction decode unit and/or a set of global completion table, is used for an opcode compare operation. The compare operation compares the instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw. The pattern is separate and distinct from opcode information within the instruction that is utilized by the set of opcode compare logic during the opcode compare operation.
摘要翻译：公开了一种用于处理处理器中的处理缺陷的新颖系统和方法。从存储器位置获取至少一个指令。该指令被解码。与指令解码单元和/或一组全局完成表相关联的一组操作码比较逻辑被用于操作码比较操作。响应于解码，比较操作将指令和至少一个操作码比较寄存器中的一组值进行比较。该指令用基于操作码比较操作的模式标记。该模式表示该指令与处理缺陷相关联。该模式与操作码比较操作期间的一组操作码比较逻辑所使用的指令内的操作码信息分开且不同。

5. 发明申请

US20110154116A1 PREDICTING AND AVOIDING OPERAND-STORE-COMPARE HAZARDS IN OUT-OF-ORDER MICROPROCESSORS 有权
公开(公告)号：US20110154116A1
公开(公告)日：2011-06-23
申请号：US12644923
申请日：2009-12-22
申请人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
发明人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
IPC分类号： G06F11/07
CPC分类号： G06F9/3834
摘要： A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.

6. 发明申请

US20090216952A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR MANAGING CACHE MEMORY 有权
标题翻译：用于管理高速缓存存储器的方法，系统和计算机程序产品
公开(公告)号：US20090216952A1
公开(公告)日：2009-08-27
申请号：US12037829
申请日：2008-02-26
申请人： Robert J. Sonnelitter, III , Gregory W. Alexander , Brian R. Prasky
发明人： Robert J. Sonnelitter, III , Gregory W. Alexander , Brian R. Prasky
IPC分类号： G06F12/08
CPC分类号： G06F12/121
摘要： A method for managing cache memory including receiving an instruction fetch for an instruction stream in a cache memory, wherein the instruction fetch includes an instruction fetch reference tag for the instruction stream and the instruction stream is at least partially included within a cache line, comparing the instruction fetch reference tag to a previous instruction fetch reference tag, maintaining a cache replacement status of the cache line if the instruction fetch reference tag is the same as the previous instruction fetch reference tag, and upgrading the cache replacement status of the cache line if the instruction fetch reference tag is different from the previous instruction fetch reference tag, whereby the cache replacement status of the cache line is upgraded if the instruction stream is independently fetched more than once. A corresponding system and computer program product.
摘要翻译：一种用于管理高速缓存存储器的方法，包括接收高速缓冲存储器中的指令流的指令取出，其中指令获取包括用于指令流的指令获取参考标签，并且指令流至少部分地包括在高速缓存行内，指令获取参考标签到先前的指令获取参考标签，如果指令获取引用标签与先前的指令获取引用标签相同，则保持高速缓存行的高速缓存替换状态，并且如果高速缓存行的高速缓存替换状态指令获取参考标签与先前的指令获取参考标签不同，从而如果指令流被独立地提取多次，则缓存行的高速缓存替换状态被升级。相应的系统和计算机程序产品。

7. 发明授权

US07306871B2 Hybrid power generating system combining a fuel cell and a gas turbine 有权
标题翻译：组合燃料电池和燃气轮机的混合动力发电系统
公开(公告)号：US07306871B2
公开(公告)日：2007-12-11
申请号：US10793303
申请日：2004-03-04
申请人： Malcolm J. Grieve , John A. MacBain , Kaushik Rajashekara , Gregory W. Alexander , Brett W. Buck , Daniel D. Richey
发明人： Malcolm J. Grieve , John A. MacBain , Kaushik Rajashekara , Gregory W. Alexander , Brett W. Buck , Daniel D. Richey
IPC分类号： H01M2/02
CPC分类号： H01M8/04097 , F02C1/05 , F02C1/08 , F05D2220/60 , H01M8/04022 , H01M8/0612 , H01M2250/407 , Y02E20/16 , Y02E60/563
摘要： A system for co-generation of electricity combining a hydrocarbon catalytic reformer, an SOFC assembly and a generator driven by a gas turbine. The fuel cell assembly recycles a high percentage of anode exhaust gas into the reformer. Oxygen for reforming is derived from water in an endothermic process. The stack exit temperature is normally above 800° C. DC power from the fuel cell assembly and AC power from the gas turbine generator are directed to a power conditioner. Anode exhaust gas including carbon monoxide and hydrogen is divided into a plurality of portions by which heat may be added to the reforming, gas turbine, and cathode air heating processes. Water may be recovered from the exhaust. A power system in accordance with the invention is capable of operating at a higher total efficiency than either the fuel cell component or the gas turbine component alone.
摘要翻译：一种用于共同生成电力的系统，其组合烃催化重整器，SOFC组件和由燃气轮机驱动的发电机。燃料电池组件将高百分比的阳极废气再循环到重整器中。用于重整的氧气是在吸热过程中来自水。堆叠出口温度通常高于800℃。来自燃料电池组件的直流电力和来自燃气涡轮发电机的AC电力被引导到功率调节器。包括一氧化碳和氢的阳极废气被分成多个部分，通过该部分可以向重整燃气轮机和阴极空气加热过程加热。水可以从废气中回收。根据本发明的电力系统能够以比燃料电池部件或燃气轮机部件单独地更高的总效率运行。

8. 发明授权

US09519480B2 Branch target preloading using a multiplexer and hash circuit to reduce incorrect branch predictions 有权
标题翻译：分支目标预加载使用多路复用器和散列电路来减少不正确的分支预测
公开(公告)号：US09519480B2
公开(公告)日：2016-12-13
申请号：US12029258
申请日：2008-02-11
申请人： Gregory W. Alexander , Anton Blanchard , Milton D. Miller, II , Todd A. Venton , Kenneth L. Wright
发明人： Gregory W. Alexander , Anton Blanchard , Milton D. Miller, II , Todd A. Venton , Kenneth L. Wright
IPC分类号： G06F9/312 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3005 , G06F9/3804 , G06F9/3806
摘要： A system provides complex branch execution hardware and a hardware-based Multiplexer (MUX) to multiplex a fetch address of a future branch and a preloaded branch fetch address to create an index hash value that is used to index a branch target prediction table for execution by a processor core, in order to reduce branch mis-prediction by preloading.
摘要翻译：系统提供复杂的分支执行硬件和基于硬件的多路复用器（MUX）来复用未来分支的提取地址和预加载的分支提取地址，以创建用于索引分支目标预测表以执行的索引散列值处理器核心，以便通过预加载减少分支误预测。

9. 发明授权

US08667258B2 High performance cache translation look-aside buffer (TLB) lookups using multiple page size prediction 失效
标题翻译：使用多页大小预测的高性能缓存翻译后备缓冲区（TLB）查找
公开(公告)号：US08667258B2
公开(公告)日：2014-03-04
申请号：US12821723
申请日：2010-06-23
申请人： Brian R. Prasky , Gregory W. Alexander , James J. Bonanno , Aaron Tsai , Joshua M. Weinberg
发明人： Brian R. Prasky , Gregory W. Alexander , James J. Bonanno , Aaron Tsai , Joshua M. Weinberg
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F9/26 , G06F9/34
CPC分类号： G06F9/3806 , G06F12/1027 , G06F2212/652 , G06F2212/654
摘要： A computer processing system method and apparatus having a processor employing an operating system (O/S) multi-task control between multiple user programs and which ensures that the programs do not interfere with each other, said computing processing system having a branch multiple page size prediction mechanism which predicts a page size along with a branch direction and a branch target of a branch for instructions of a processing pipeline, having a branch target buffer (BTB) predicting the branch target, said branch prediction mechanism storing recently used instructions close to the processor in a local cache, and having a translation look-aside buffer TLB mechanism which tracks the translation of the most recent pages and supports multiple page sizes.
摘要翻译：一种具有处理器的计算机处理系统方法和装置，所述处理器采用多个用户程序之间的操作系统（O / S）多任务控制，并确保所述程序不相互干扰，所述计算处理系统具有分支多页大小预测机构，其预测具有分支目标缓冲器（BTB）的处理流水线的指示的分支方向的分支方向和分支目标的分页目标，所述分支目标缓冲器（BTB）预测分支目标，所述分支预测机制存储最近使用的指令，处理器，并且具有跟踪最近页面的翻译并支持多个页面大小的翻译后备缓冲器TLB机制。

10. 发明授权

US08468325B2 Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors 有权
公开(公告)号：US08468325B2
公开(公告)日：2013-06-18
申请号：US12644923
申请日：2009-12-22
申请人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
发明人： Gregory W. Alexander , Khary J. Alexander , Brian Curran , Jonathan T. Hsieh , Christian Jacobi , James R. Mitchell , Brian R. Prasky , Brian W. Thompto
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3834
摘要： A method and information processing system manage load and store operations executed out-of-order. At least one of a load instruction and a store instruction is executed. A determination is made that an operand store compare hazard has been encountered. An entry within an operand store compare hazard prediction table is created based on the determination. The entry includes at least an instruction address of the instruction that has been executed and a hazard indicating flag associated with the instruction. The hazard indicating flag indicates that the instruction has encountered the operand store compare hazard. When a load instruction is associated with the hazard indicating flag the load instruction becomes dependent upon all store instructions associated with a substantially similar flag.

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