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1. 发明授权

US07092270B2 Apparatus and method for detecting multiple hits in CAM arrays 失效
公开(公告)号：US07092270B2
公开(公告)日：2006-08-15
申请号：US10880719
申请日：2004-06-30
申请人： Michael Ju Hyeok Lee , Sheldon B. Levenstein , Edelmar Seewann
发明人： Michael Ju Hyeok Lee , Sheldon B. Levenstein , Edelmar Seewann
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： An apparatus and method are disclosed for detecting multiple hits in CAM arrays. A binary address value is stored for each entry of the CAM array and is output to identify the matching entry for a single hit. However, to facilitate multiple hit detection, both the true and complement components of this address are stored and output to determine whether or not a multiple hit occurred. If a multiple hit occurs (e.g., more than one address location has been matched), all the bits that make up the binary address and the complement will not be complements of each other and a multiple hit condition can be detected by XORing each bit of an address location value with the complement of that address location value. If the XORed bits are equal to “1”, then a single hit has occurred. Otherwise, a multiple hit has occurred.

2. 发明授权

US5566305A Duplicated logic and interconnection system for arbitration among multiple information processors 失效
公开(公告)号：US5566305A
公开(公告)日：1996-10-15
申请号：US462673
申请日：1995-06-05
申请人： Sheldon B. Levenstein
发明人： Sheldon B. Levenstein
IPC分类号： G06F15/16 , G06F9/46 , G06F15/167 , G06F15/177 , G06F13/00
CPC分类号： G06F9/52 , G06F15/167 , G06F9/3004 , G06F9/30087
摘要： An information processing network includes multiple processing devices, a main storage memory, and an interface coupling the processing devices to the main storage memory. All processing devices contend for control of the interface on an equal basis, subject to a dynamically shifting sequence of priority rankings, invoked to resolve contentions for the interface or for one of a plurality of hardware class locks. The class locks are uniquely associated with different capabilities or classes of data operations, which reduces the number of contentions and allows multiple operations to proceed simultaneously. Arbitration logic encompassing all of the processing devices is duplicated in each of the processing devices, and kept coherent through an interconnection of multiple data buses. One bus is associated with each processing device, receives the output of the associated processing device and provides the output to each of the other processing devices. A lock sequencer includes a store-tracking feature that minimizes the time that any processor, after losing a contention for a lock, is in a hold condition.

3. 发明申请

US20120297162A1 Method for Detecting Address Match in a Deeply Pipelined Processor Design 有权
标题翻译：在深度流水线处理器设计中检测地址匹配的方法
公开(公告)号：US20120297162A1
公开(公告)日：2012-11-22
申请号：US13297199
申请日：2011-11-15
申请人： Miles Robert Dooley , Scott Bruce Frommer , David Allen Hrusecky , Sheldon B. Levenstein
发明人： Miles Robert Dooley , Scott Bruce Frommer , David Allen Hrusecky , Sheldon B. Levenstein
IPC分类号： G06F12/06
CPC分类号： G06F11/362
摘要： A method, apparatus and algorithm for quickly detecting an address match in a deeply pipelined processor design in a manner that may be implemented using a minimum of physical space in the critical area of the processor. The address comparison is split into two parts. The first part is a fast, partial address match comparator system. The second part is a slower, full address match comparator system. If a partial match between a requested address and a registry address is detected, then execution of the program or set of instructions requesting the address is temporarily suspended while a full address match check is performed. If the full address match check results in a full match between the requested address and a registry address, then the program or set of instructions is interrupted and stopped. Otherwise, the program or set of instructions continues execution.
摘要翻译：一种用于以可以使用处理器的关键区域中的最小物理空间来实现的深度流水线处理器设计中的地址匹配的快速检测的方法，装置和算法。地址比较分为两部分。第一部分是快速部分地址匹配比较系统。第二部分是较慢的全地址匹配比较系统。如果检测到请求的地址和注册表地址之间的部分匹配，则在执行完整的地址匹配检查时暂时停止执行请求地址的程序或指令集。如果完整的地址匹配检查导致所请求的地址和注册表地址之间的完全匹配，则程序或指令集被中断和停止。否则，程序或指令集继续执行。

4. 发明授权

US07660965B2 Method to optimize effective page number to real page number translation path from page table entries match resumption of execution stream 有权
标题翻译：从页表条目优化有效页码到实际页码转换路径的方法匹配恢复执行流
公开(公告)号：US07660965B2
公开(公告)日：2010-02-09
申请号：US11969988
申请日：2008-01-07
申请人： Joaquin Hinojosa , Sheldon B. Levenstein , Bruce Joseph Ronchetti
发明人： Joaquin Hinojosa , Sheldon B. Levenstein , Bruce Joseph Ronchetti
IPC分类号： G06F12/10 , G06F13/28
CPC分类号： G06F12/1027 , G06F2212/681
摘要： A method, system and computer program product for optimizing EPN to RPN translation when a data miss occurs. The method, system and computer program product take advantage of the high-likelihood of finding the matching PTE in the first half of the PTEG and utilize early data-coming signals from the L2 cache to prime the data-flow pipe to the D-ERAT arrays and requesting a joint steal cycle for executing the write into the D-ERAT and a restart request for re-dispatching the next-to-complete instruction.
摘要翻译：一种在数据丢失发生时优化EPN到RPN转换的方法，系统和计算机程序产品。该方法，系统和计算机程序产品利用在PTEG的前半部分找到匹配的PTE的高似然性，并利用来自L2缓存的早期数据来信号将数据流管道引导到D-ERAT 阵列并请求执行对D-ERAT的写入的联合窃取循环以及重新发送下一条完整指令的重新启动请求。

5. 发明授权

US07360058B2 System and method for generating effective address 有权
标题翻译：用于生成有效地址的系统和方法
公开(公告)号：US07360058B2
公开(公告)日：2008-04-15
申请号：US11054274
申请日：2005-02-09
申请人： Rachel Marie Flood , Scott Bruce Frommer , David Allen Hrusecky , Sheldon B. Levenstein , Michael Thomas Vaden
发明人： Rachel Marie Flood , Scott Bruce Frommer , David Allen Hrusecky , Sheldon B. Levenstein , Michael Thomas Vaden
IPC分类号： G06F12/00
CPC分类号： G06F9/355 , G06F9/30043 , G06F9/3816 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3861 , G06F12/1027
摘要： Method, system and computer program product for generating effective addresses in a data processing system. A method, in a data processing system, for generating an effective address includes generating a first portion of the effective address by calculating a first plurality of effective address bits of the effective address, and generating a second portion of the effective address by guessing a second plurality of effective address bits of the effective address. By intelligently guessing a plurality of the effective address bits that form the effective address, the effective address can be generated and sent to a translation unit more quickly than in a system in which all the effective address bits of the effective address are calculated. The method and system is particularly suitable for generating effective addresses in a CAM-based effective address translation design in a multi-threaded environment.
摘要翻译：用于在数据处理系统中生成有效地址的方法，系统和计算机程序产品。一种在数据处理系统中用于产生有效地址的方法包括通过计算有效地址的第一多个有效地址位来产生有效地址的第一部分，以及通过猜测有效地址产生有效地址的第二部分多个有效地址的有效地址位。通过智能地猜测形成有效地址的多个有效地址位，可以比在其中计算有效地址的所有有效地址位的系统中更快地生成有效地址并将其发送到转换单元。该方法和系统特别适用于在多线程环境中的基于CAM的有效地址转换设计中生成有效地址。

6. 发明授权

US07228385B2 Processor, data processing system and method for synchronizing access to data in shared memory 有权
标题翻译：处理器，数据处理系统和方法，用于同步共享存储器中数据的访问
公开(公告)号：US07228385B2
公开(公告)日：2007-06-05
申请号：US10965113
申请日：2004-10-14
申请人： Guy Lynn Guthrie , Sheldon B. Levenstein , William John Starke , Derek Edward Williams
发明人： Guy Lynn Guthrie , Sheldon B. Levenstein , William John Starke , Derek Edward Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3851 , G06F12/0811 , G06F12/0831 , G06F12/0855
摘要： A processing unit for a multiprocessor data processing system includes a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, at least one instruction execution unit that executes a store-conditional instruction to determine a store target address, a store queue that, following execution of the store-conditional instruction, buffers a corresponding store operation, sequencer logic associated with the store queue. The sequencer logic, responsive to receipt of a latency indication indicating that resolution of the store-conditional operation as passing or failing is subject to significant latency, invalidates, prior to resolution of the store-conditional operation, a cache line in the store-through upper level cache to which a load-reserve operation previously bound.
摘要翻译：一种用于多处理器数据处理系统的处理单元，包括存储器上级缓存器，取指令执行指令排序单元，至少一个执行存储条件指令以确定存储目标地址的指令执行单元，存储器在存储条件指令的执行之后，缓存与存储队列相关联的对应存储操作，定序器逻辑的队列。定序器逻辑响应于指示存储条件操作的解析作为传递或失败的等待时间指示受到重大等待时间的影响，在存储条件操作的解析之前无效，存储器中的高速缓存行加载预备操作先前绑定到的高级缓存。

7. 发明授权

US6088788A Background completion of instruction and associated fetch request in a multithread processor 失效
标题翻译：在多线程处理器中完成指令和相关的提取请求
公开(公告)号：US6088788A
公开(公告)日：2000-07-11
申请号：US773572
申请日：1996-12-27
申请人： John M. Borkenhagen , Richard J. Eickemeyer , Sheldon B. Levenstein , Andrew H. Wottreng , Duane A. Averill , James I. Brookhouser
发明人： John M. Borkenhagen , Richard J. Eickemeyer , Sheldon B. Levenstein , Andrew H. Wottreng , Duane A. Averill , James I. Brookhouser
IPC分类号： G06F9/38 , G06F9/40 , G06F15/76
CPC分类号： G06F9/3851 , G06F9/3824
摘要： The data processing system includes a plurality of execution units forming a plurality of processing pipelines. The plurality of processing pipelines process instructions and include a storage pipeline. The data processing system further includes an instruction unit and a storage control unit. The instruction unit outputs instructions to the plurality of execution units, and controls execution of multiple threads by the plurality of execution units. If an instruction for a first thread in the storage pipeline experiences a cache miss and the instruction unit decides to switch threads, the instruction unit begins processing a second thread. The instruction unit also issues a data request to the storage control unit to obtain the missing data. During processing of the second thread, unused slots will appear in the storage pipeline because it is not possible to always dispatch instructions to completely keep the pipelines filled. After the requested data returns from higher level memory, the storage control unit will dispatch the instruction from the first thread having received the cache miss to an unused slot in the storage pipeline. Consequently, this instruction from the first thread will be processed along with the instructions from the second thread.
摘要翻译：数据处理系统包括形成多个处理流水线的多个执行单元。多个处理管线处理指令并且包括存储管线。数据处理系统还包括指令单元和存储控制单元。指令单元向多个执行单元输出指令，并且控制多个执行单元执行多个线程。如果存储管线中的第一线程的指令经历高速缓存未命中并且指令单元决定切换线程，则指令单元开始处理第二线程。指令单元还向存储控制单元发出数据请求以获得丢失的数据。在处理第二个线程期间，未使用的插槽将出现在存储管道中，因为不可能总是调度指令以完全保持管道的填充。在所请求的数据从较高级存储器返回之后，存储控制单元将从接收到高速缓存未命中的第一线程的指令发送到存储流水线中的未使用的时隙。因此，来自第一个线程的指令将与第二个线程的指令一起处理。

8. 发明授权

US5586331A Duplicated logic and interconnection system for arbitration among multiple information processors 失效
公开(公告)号：US5586331A
公开(公告)日：1996-12-17
申请号：US459456
申请日：1995-06-02
申请人： Sheldon B. Levenstein
发明人： Sheldon B. Levenstein
IPC分类号： G06F15/16 , G06F9/46 , G06F15/167 , G06F15/177 , G06F12/14
CPC分类号： G06F9/52 , G06F15/167 , G06F9/3004 , G06F9/30087
摘要： An information processing network includes multiple processing devices, a main storage memory, and an interface coupling the processing devices to the main storage memory. All processing devices contend for control of the interface on an equal basis, subject to a dynamically shifting sequence of priority rankings, invoked to resolve contentions for the interface or for one of a plurality of hardware class locks. The class locks are uniquely associated with different capabilities or classes of data operations, which reduces the number of contentions and allows multiple operations to proceed simultaneously. Arbitration logic encompassing all of the processing devices is duplicated in each of the processing devices, and kept coherent through an interconnection of multiple data buses. One bus is associated with each processing device, receives the output of the associated processing device and provides the output to each of the other processing devices. A lock sequencer includes a store-tracking feature that minimizes the time that any processor, after losing a contention for a lock, is in a hold condition.

9. 发明授权

US5339397A Hardware primary directory lock 失效
标题翻译：硬件主目录锁
公开(公告)号：US5339397A
公开(公告)日：1994-08-16
申请号：US596812
申请日：1990-10-12
申请人： Richard G. Eikill , Sheldon B. Levenstein , Lynn A. McMahon , Joseph P. Weigel
发明人： Richard G. Eikill , Sheldon B. Levenstein , Lynn A. McMahon , Joseph P. Weigel
IPC分类号： G06F12/08 , G06F9/46 , G06F12/10 , G06F15/167 , G06F12/14 , G06F13/00 , G06F13/376
CPC分类号： G06F15/167 , G06F12/1036 , G06F9/526 , G06F2209/521 , G06F2212/682
摘要： An information processing network includes multiple processing devices, a main storage memory, one or more disk drives or other auxiliary storage devices, and an interface for coupling the processing devices to the main storage memory and the auxiliary devices. A primary directory in main storage contains mapping information for translating virtual addresses to real addresses in main storage. Look-aside buffers in the processing devices duplicate some of the mapping information. A primary directory hardware lock, subject to exclusive control by any one of the processing devices to update the primary directory, inhibits access to the primary directory based on hardware address translations initiated when one of the processors holds the primary directory lock. Address translations in progress when the lock is acquired proceed to completion before the primary directory is updated under the lock. Accordingly, such updates proceed atomically relative to hardware primary directory searches. Unnecessary quiesces and purges of the look-aside buffers are eliminated, substantially improving network performance.
摘要翻译：信息处理网络包括多个处理设备，主存储存储器，一个或多个盘驱动器或其他辅助存储设备，以及用于将处理设备耦合到主存储器和辅助设备的接口。主存储中的主目录包含用于将虚拟地址转换为主存储中的实际地址的映射信息。处理设备中的旁路缓冲区重复一些映射信息。主目录硬件锁（由任何一个处理设备进行排他控制以更新主目录）禁止基于当其中一个处理器保持主目录锁定时启动的硬件地址转换来访问主目录。在获取锁定之前，正在进行的地址转换在主目录在锁定之前被更新之前进行完成。因此，这样的更新相对于硬件主目录搜索原子地进行。消除了不必要的停顿和清除缓冲区，大大提高了网络性能。

10. 发明申请

US20120173821A1 Predicting the Instruction Cache Way for High Power Applications 有权
标题翻译：预测大功率应用的指令缓存方式
公开(公告)号：US20120173821A1
公开(公告)日：2012-07-05
申请号：US12984300
申请日：2011-01-04
申请人： Sheldon B. Levenstein , David S. Levitan
发明人： Sheldon B. Levenstein , David S. Levitan
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0864 , G06F9/3804 , G06F9/3808 , G06F9/381 , G06F12/0882 , G06F2212/1028 , Y02D10/13
摘要： A mechanism for accessing a cache memory is provided. With the mechanism of the illustrative embodiments, a processor of the data processing system performs a first execution a portion of code. During the first execution of the portion of code, information identifying which cache lines in the cache memory are accessed during the execution of the portion of code is stored in a storage device of the data processing system. Subsequently, during a second execution of the portion of code, power to the cache memory is controlled such that only the cache lines that were accessed during the first execution of the portion of code are powered-up.
摘要翻译：提供了用于访问高速缓冲存储器的机制。利用说明性实施例的机制，数据处理系统的处理器执行代码的一部分的第一执行。在代码部分的第一次执行期间，在代码部分的执行期间识别高速缓冲存储器中的哪些高速缓存行被访问的信息被存储在数据处理系统的存储装置中。随后，在代码部分的第二次执行期间，控制对高速缓冲存储器的电力，使得只有在代码部分的第一次执行期间被访问的高速缓存行被加电。

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