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21. 发明授权

US07215577B2 Flash memory cell and methods for programming and erasing 有权
标题翻译：闪存单元和编程和擦除的方法
公开(公告)号：US07215577B2
公开(公告)日：2007-05-08
申请号：US11511763
申请日：2006-08-29
申请人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
发明人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
IPC分类号： G11C11/34 , G11C16/04 , H01L29/78
CPC分类号： G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/66833
摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.
摘要翻译：提供了闪存单元，其包括形成在衬底沟道区上方的电介质材料，在电介质材料上形成的电荷俘获材料，以及形成在电荷俘获材料上的控制栅。可以通过将电子从控制栅极引导到电荷捕获材料中来提高电池阈值电压来编程电池。电子可以通过将衬底耦合到衬底电压电势，并将控制栅极耦合到栅极电压电位，其中栅极电压电位低于衬底电压电位，从控制栅极引导到电荷俘获材料。可以通过将电子从电荷捕获材料引入控制栅极来降低闪速存储器单元的阈值电压，例如通过将衬底耦合到衬底电压电位，以及将控制栅极耦合到栅极电压电位来擦除电池，其中栅极电压电位高于衬底电压电位。

22. 发明申请

US20060091439A1 System and method for protecting semiconductor devices 有权
标题翻译：用于保护半导体器件的系统和方法
公开(公告)号：US20060091439A1
公开(公告)日：2006-05-04
申请号：US10976816
申请日：2004-11-01
申请人： Ihsan Djomehri , Mark Randolph , Yi He , Wei Zheng
发明人： Ihsan Djomehri , Mark Randolph , Yi He , Wei Zheng
IPC分类号： H01L29/94
CPC分类号： H01L27/115 , H01L27/0288
摘要： A semiconductor memory device includes a group of word lines and a structure that is configured to dissipate current from the group of word lines during fabrication of the semiconductor memory device.
摘要翻译：半导体存储器件包括一组字线和被配置成在制造半导体存储器件期间消散来自字线组的电流的结构。

23. 发明申请

US20050073886A1 Memory device and method using positive gate stress to recover overerased cell 有权
标题翻译：使用正栅极应力的存储器件和方法来恢复过度电池
公开(公告)号：US20050073886A1
公开(公告)日：2005-04-07
申请号：US10677790
申请日：2003-10-02
申请人： Darlene Hamilton , Zhizheng Liu , Mark Randolph , Yi He , Edward Hsia , Kulachet Tanpairoj , Mimi Lee , Alykhan Madhani
发明人： Darlene Hamilton , Zhizheng Liu , Mark Randolph , Yi He , Edward Hsia , Kulachet Tanpairoj , Mimi Lee , Alykhan Madhani
IPC分类号： G11C16/04 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3404 , G11C16/0475 , G11C16/107 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345
摘要： A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.
摘要翻译：擦除由多个存储器单元组成的闪存电可擦除只读存储器（EEPROM）器件的方法包括对多个存储器单元进行预编程，向多个存储器单元施加擦除脉冲，随后进行擦除验证。擦除验证之后是对具有低于预定最小电平的阈值电压的任何存储器单元进行软编程，并向多个存储单元施加正栅极应力。擦除方法可以防止过压，并提供紧固的阈值电压分布。

24. 发明授权

US08652582B2 Method of making ligand functionalized substrates 有权
标题翻译：制备配体官能化底物的方法
公开(公告)号：US08652582B2
公开(公告)日：2014-02-18
申请号：US12937458
申请日：2009-05-26
申请人： Catherine A. Bothof , Yi He , Jerald K. Rasmussen , Kannan Seshadri , Clinton P. Waller, Jr. , Douglas E. Weiss
发明人： Catherine A. Bothof , Yi He , Jerald K. Rasmussen , Kannan Seshadri , Clinton P. Waller, Jr. , Douglas E. Weiss
IPC分类号： C08F2/46
CPC分类号： C07C279/12 , B01D39/1676 , B01J20/285 , C07C277/08 , C07C279/14 , C07C281/16 , C07K1/34 , C08F259/08 , C08F283/04 , C08G69/48 , C08J7/18 , C08J9/283 , C08J9/42 , C08J2327/16 , C08J2377/00 , C12N7/00 , Y02C10/08 , Y10T428/31855
摘要： Ligand functionalized substrates, methods of making ligand functionalized substrates, and methods of using functionalized substrates are disclosed. The ligand functionalized substrate may be described as the grafted reaction product of a substrate and a ligand monomer of Formula I:
摘要翻译：配体功能化底物，制备配体官能化底物的方法，以及使用官能化底物的方法。配体官能化底物可以描述为底物和式I的配体单体的接枝反应产物：

25. 发明授权

US08497353B2 Polypeptides for microbial detection 有权
公开(公告)号：US08497353B2
公开(公告)日：2013-07-30
申请号：US12867078
申请日：2009-02-12
申请人： Stephen B. Roscoe , Stephanie J. Moeller , Yi He , Richard B. Ross
发明人： Stephen B. Roscoe , Stephanie J. Moeller , Yi He , Richard B. Ross
IPC分类号： A61K38/16
CPC分类号： G01N33/56961 , C07K7/08 , G01N2469/10
摘要： Polypeptides which can be activated to cause the formation of pores in a lipid membrane are disclosed. Also disclosed are polypeptide compositions for the detection of target microorganisms and methods of using said compositions.

26. 发明授权

US08102679B2 Utilization of a multifunctional pin to control a switched-mode power converter 有权
标题翻译：利用多功能引脚来控制开关式功率转换器
公开(公告)号：US08102679B2
公开(公告)日：2012-01-24
申请号：US12192399
申请日：2008-08-15
申请人： Xiaowu Gong , Siu Kam Kok , Yi He , Tuck Meng Chan
发明人： Xiaowu Gong , Siu Kam Kok , Yi He , Tuck Meng Chan
IPC分类号： H02M3/335
CPC分类号： H02M3/156 , H02M3/33507 , H02M2001/0022 , H02M2001/0032 , Y02B70/16
摘要： An embodiment of the invention relates to a power converter including a resistor divider with an internal node to sense an input line voltage. The internal node is operable as a multifunctional pin. A controller compares a feedback voltage dependent on a power converter output characteristic to a current-sense signal including an offset dependent on a voltage of the internal node to control entry and exit of the power converter from burst mode operation. The node may be employed to manage power converter operation by sensing or controlling its voltage to signal operation in a standby or burst mode, to sense the input line voltage, to enable an external system to signal shutdown to the power converter, and to enable the power converter to signal a delayed restart condition to the external system.
摘要翻译：本发明的实施例涉及一种功率转换器，其包括具有用于感测输入线电压的内部节点的电阻分压器。内部节点可用作多功能引脚。控制器将取决于功率转换器输出特性的反馈电压与包括取决于内部节点的电压的偏移的电流检测信号进行比较，以控制功率转换器的进入和退出以进行突发模式操作。可以采用该节点来管理功率转换器的操作，通过感测或控制其电压以在备用或突发模式下信号操作，以感测输入线路电压，使外部系统能够向功率转换器发出信号关闭，电源转换器向外部系统发出延迟重启状态信号。

27. 发明申请

US20110217752A1 LIGAND FUNCTIONALIZED POLYMERS 有权
标题翻译：配体官能化聚合物
公开(公告)号：US20110217752A1
公开(公告)日：2011-09-08
申请号：US13026331
申请日：2011-02-14
申请人： Jerald K. Rasmussen , Kannan Seshadri , Robert T. Fitzsimons, JR. , James I. Hembre , Catherine A. Bothof , Erin A. Satterwhite , George W. Griesgraber , Yi He , Louis C. Haddad
发明人： Jerald K. Rasmussen , Kannan Seshadri , Robert T. Fitzsimons, JR. , James I. Hembre , Catherine A. Bothof , Erin A. Satterwhite , George W. Griesgraber , Yi He , Louis C. Haddad
IPC分类号： C12N9/00 , C07K1/14 , C07H1/06 , B01D21/01
CPC分类号： C07K1/14 , B01D21/01 , C08F120/60 , C08F126/02 , C08G69/10 , C08G73/0206 , C08G73/022 , C08G73/028 , C08L77/04 , C08L79/02 , C08L83/08 , C12N7/02 , C12N11/08 , G01N33/54393 , G01N33/545 , Y10T428/249978 , Y10T428/249991 , Y10T428/2935 , Y10T428/2998 , Y10T442/20
摘要： Ligand functionalized substrates, methods of making ligand functionalized substrates, and methods of using functionalized substrates are disclosed.
摘要翻译：配体功能化底物，制备配体官能化底物的方法，以及使用官能化底物的方法。

28. 发明授权

US07765086B2 Modulation domain trigger 有权
标题翻译：调制域触发
公开(公告)号：US07765086B2
公开(公告)日：2010-07-27
申请号：US11009161
申请日：2004-12-09
申请人： Alfred K. Hillman, Jr. , Marcus K. Dasilva , Edward C. Gee , Yi He
发明人： Alfred K. Hillman, Jr. , Marcus K. Dasilva , Edward C. Gee , Yi He
IPC分类号： G06F11/30
CPC分类号： G01R23/16 , G01R13/0263
摘要： A modulation domain trigger generator demodulates a modulated input signal to extract information content, and a trigger is generated from the extracted information content in response to specified trigger criteria. The modulation domain trigger generator may be combined with a plurality of different types of trigger generators, including frequency domain and time domain trigger generators, to process the input signal in response to different trigger criteria to produce more than one trigger. The different trigger outputs may be combined to produce an acquisition trigger to acquire data surrounding an anomalous or identifiable event within the input signal.
摘要翻译：调制域触发发生器解调调制输入信号以提取信息内容，并且响应于指定的触发标准从所提取的信息内容产生触发。调制域触发发生器可以与多个不同类型的触发发生器组合，包括频域和时域触发发生器，以响应于不同的触发标准处理输入信号以产生多于一个的触发。可以组合不同的触发输出以产生采集触发以获取围绕输入信号内的异常或可识别事件的数据。

29. 发明授权

US07667526B2 Apparatus, system, and method for multifunctional pin in an integrated circuit 失效
标题翻译：集成电路中多功能引脚的装置，系统和方法
公开(公告)号：US07667526B2
公开(公告)日：2010-02-23
申请号：US11461303
申请日：2006-07-31
申请人： Tuck Meng Chan , Xiao Wu Gong , Yi He , Meng Kiat Jeoh , Junyang Luo
发明人： Tuck Meng Chan , Xiao Wu Gong , Yi He , Meng Kiat Jeoh , Junyang Luo
IPC分类号： H03K17/687
CPC分类号： H03K17/0822 , H03K17/133
摘要： Some embodiments of the invention include an integrated circuit having a node or pin to detect a first information during a first a detection period and to detect a second information during a second detection period. In some embodiments, the information at the pin may allow the integrated circuit to operate in a quasi-resonant operation. Other embodiments are described and claimed.
摘要翻译：本发明的一些实施例包括具有节点或引脚以在第一检测周期期间检测第一信息并在第二检测周期期间检测第二信息的集成电路。在一些实施例中，引脚处的信息可以允许集成电路在准谐振操作中操作。描述和要求保护其他实施例。

30. 发明授权

US07573103B1 Back-to-back NPN/PNP protection diodes 有权
标题翻译：背对背NPN / PNP保护二极管
公开(公告)号：US07573103B1
公开(公告)日：2009-08-11
申请号：US11855704
申请日：2007-09-14
申请人： Yi He , Zhizheng Liu , Meng Ding , Wei Zheng
发明人： Yi He , Zhizheng Liu , Meng Ding , Wei Zheng
IPC分类号： H01L27/06
CPC分类号： H01L27/0266 , H01L27/0255
摘要： A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN diode includes a p-type substrate connected to ground, a well of n-type material formed in the p-type substrate in direct physical contact with the p-type substrate and electrically connected to the p-type substrate via a first metal line, a well of p-type material formed in the first well of n-type material, a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and connected to the word line of the memory device, and a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and electrically connected to the well of p-type material via a second metal line. The PNP diode includes a n-type substrate connected to ground, a well of p-type material formed in the n-type substrate in direct physical contact with the n-type substrate and electrically connected to the n-type substrate via a first metal line, a well of n-type material formed in the first well of p-type material, a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and connected to the word line of the memory device, and a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and electrically connected to the well of n-type material via a second metal line.
摘要翻译：一种设备包括存储器件和耦合到存储器件的字线的NPN或PNP二极管。 NPN二极管包括连接到地的p型衬底，在p型衬底中形成的与p型衬底直接物理接触的n型材料的阱，并通过第一金属电连接到p型衬底线，在n型材料的第一阱中形成的p型材料的阱，形成在p型材料的阱中的第一n型区，与p型材料的阱直接物理接触并连接到存储器件的字线和形成在n型材料的阱中的与n型材料的阱直接物理接触并且经由第二p型材料电连接到p型材料的阱的第一p型区域金属线。 PNP二极管包括连接到地的n型衬底，形成在n型衬底中的p型材料的阱与n型衬底直接物理接触并且经由第一金属电连接到n型衬底线，在p型材料的第一阱中形成的n型材料的阱，形成在n型材料的阱中的与n型材料的阱直接物理接触的第一p型区，并连接到存储器件的字线和形成在p型材料的阱中的第一n型区域，其与p型材料的阱直接物理接触并且经由第二类型的n型材料电连接到n型材料的阱金属线。

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