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1. 发明申请

US20060291282A1 Flash memory cell and methods for programming and erasing 有权
公开(公告)号：US20060291282A1
公开(公告)日：2006-12-28
申请号：US11511763
申请日：2006-08-29
申请人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
发明人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
IPC分类号： G11C11/34
CPC分类号： G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/66833
摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

2. 发明授权

US07120063B1 Flash memory cell and methods for programming and erasing 有权
标题翻译：闪存单元和编程和擦除的方法
公开(公告)号：US07120063B1
公开(公告)日：2006-10-10
申请号：US10841850
申请日：2004-05-07
申请人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
发明人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/66833
摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.
摘要翻译：提供了闪存单元，其包括形成在衬底沟道区上方的电介质材料，在电介质材料上形成的电荷俘获材料，以及形成在电荷俘获材料上的控制栅。可以通过将电子从控制栅极引导到电荷捕获材料中来提高电池阈值电压来编程电池。电子可以通过将衬底耦合到衬底电压电势，并将控制栅极耦合到栅极电压电位，其中栅极电压电位低于衬底电压电位，从控制栅极引导到电荷俘获材料。可以通过将电子从电荷捕获材料引入控制栅极来降低闪速存储器单元的阈值电压，例如通过将衬底耦合到衬底电压电位，以及将控制栅极耦合到栅极电压电位来擦除电池，其中栅极电压电位高于衬底电压电位。

3. 发明授权

US07215577B2 Flash memory cell and methods for programming and erasing 有权
标题翻译：闪存单元和编程和擦除的方法
公开(公告)号：US07215577B2
公开(公告)日：2007-05-08
申请号：US11511763
申请日：2006-08-29
申请人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
发明人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
IPC分类号： G11C11/34 , G11C16/04 , H01L29/78
CPC分类号： G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/66833
摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.
摘要翻译：提供了闪存单元，其包括形成在衬底沟道区上方的电介质材料，在电介质材料上形成的电荷俘获材料，以及形成在电荷俘获材料上的控制栅。可以通过将电子从控制栅极引导到电荷捕获材料中来提高电池阈值电压来编程电池。电子可以通过将衬底耦合到衬底电压电势，并将控制栅极耦合到栅极电压电位，其中栅极电压电位低于衬底电压电位，从控制栅极引导到电荷俘获材料。可以通过将电子从电荷捕获材料引入控制栅极来降低闪速存储器单元的阈值电压，例如通过将衬底耦合到衬底电压电位，以及将控制栅极耦合到栅极电压电位来擦除电池，其中栅极电压电位高于衬底电压电位。

4. 发明授权

US06934190B1 Ramp source hot-hole programming for trap based non-volatile memory devices 有权
标题翻译：用于基于陷阱的非易失性存储器设备的斜坡源热孔编程
公开(公告)号：US06934190B1
公开(公告)日：2005-08-23
申请号：US10863933
申请日：2004-06-09
申请人： Zengtao Liu , Zhizheng Liu , Yi He , Sameer Haddad , Mark Randolph
发明人： Zengtao Liu , Zhizheng Liu , Yi He , Sameer Haddad , Mark Randolph
IPC分类号： G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C16/3454
摘要： Methods of operating dual bit memory devices including programming with a range of values are provided. The present invention employs a range of ramp source program pulses to iteratively perform a program operation that employs hot hole injection. The range is related to channel lengths of individual dual bit memory cells within the memory device. To program a bit of a particular dual bit memory cell, a negative gate program voltage is applied to its gate, a positive drain voltage is applied to its acting drain, and its substrate is connected to ground. Additionally, a ramp source voltage of the range of ramp source program pulses is concurrently applied to an acting source of the dual bit memory cell. A verification operation is then performed and the programming is repeated with a decremented ramp source voltage on verification failure.
摘要翻译：提供了包括具有一定范围值的编程的双位存储器件的操作方法。本发明采用一系列斜坡源程序脉冲来迭代地执行采用热空穴注入的程序操作。该范围与存储器件内的各个双位存储单元的通道长度有关。为了编程一个特定的双位存储单元，负栅极编程电压被施加到其栅极，正的漏极电压被施加到其作用漏极，并且其衬底连接到地。此外，斜坡源程序脉冲范围的斜坡源电压同时施加到双位存储单元的作用源。然后执行验证操作，并且在验证失败时以递减的斜坡源电压重复编程。

5. 发明授权

US06834012B1 Memory device and methods of using negative gate stress to correct over-erased memory cells 有权
标题翻译：存储器件和使用负栅极应力校正过擦除存储器单元的方法
公开(公告)号：US06834012B1
公开(公告)日：2004-12-21
申请号：US10863673
申请日：2004-06-08
申请人： Yi He , Edward Franklin Runnion , Zhizheng Liu , Zengtao Liu , Mark William Randolph
发明人： Yi He , Edward Franklin Runnion , Zhizheng Liu , Zengtao Liu , Mark William Randolph
IPC分类号： G11C1604
CPC分类号： G11C16/3404 , G11C16/0475
摘要： Methods of operating dual bit flash memory devices and correcting over-erased dual bit flash memory devices are provided. The present invention includes a corrective action that employs a negative gate to correct over-erased memory cells without substantially altering threshold voltage values or charge states for properly erased memory cells. The negative gate stress is performed as a block operation by applying a negative gate voltage to gates and connecting active regions and a substrate to ground.
摘要翻译：提供了操作双位闪存器件和校正过擦除的双位闪存器件的方法。本发明包括采用负栅极来校正过擦除的存储单元而没有基本上改变正确擦除的存储单元的阈值电压值或电荷状态的校正动作。通过向栅极施加负栅极电压并将有源区域和衬底连接到地来执行负栅极应力作为块操作。

6. 发明申请

US20060268593A1 Read-only memory array with dielectric breakdown programmability 审中-公开
标题翻译：具有介电击穿可编程性的只读存储阵列
公开(公告)号：US20060268593A1
公开(公告)日：2006-11-30
申请号：US11136981
申请日：2005-05-25
申请人： Meng Ding , Zhizheng Liu , Yi He , Mark Randolph
发明人： Meng Ding , Zhizheng Liu , Yi He , Mark Randolph
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C2213/72 , H01L27/1021 , H01L27/112 , H01L27/11206 , H01L27/118
摘要： According to one exemplary embodiment, a programmable ROM array includes at least one bitline situated in a substrate. The programmable ROM array further includes at least one wordline situated over the at least one bitline. The programmable ROM array further includes a memory cell situated at an intersection of the at least one bitline and the at least one wordline, where the memory cell includes a dielectric region situated between the at least one bitline and the at least one wordline. A programming operation causes the memory cell to change from a first logic state to a second logic state by causing the dielectric region to break down. The programming operation causes the memory cell to operate as a diode. A resistance of the memory cell can be measured in a read operation to determine if the memory cell has the first or second logic state.
摘要翻译：根据一个示例性实施例，可编程ROM阵列包括位于衬底中的至少一个位线。可编程ROM阵列还包括位于至少一个位线上的至少一个字线。可编程ROM阵列还包括位于所述至少一个位线和所述至少一个字线的交叉点处的存储器单元，其中所述存储器单元包括位于所述至少一个位线和所述至少一个字线之间的电介质区域。通过使介电区域分解，编程操作使存储单元从第一逻辑状态变为第二逻辑状态。编程操作使存储单元作为二极管工作。可以在读取操作中测量存储器单元的电阻，以确定存储单元是否具有第一或第二逻辑状态。

7. 发明授权

US07750407B2 Strapping contact for charge protection 有权
标题翻译：带式触点用于充电保护
公开(公告)号：US07750407B2
公开(公告)日：2010-07-06
申请号：US11612265
申请日：2006-12-18
申请人： Wei Zheng , Jean Yang , Mark Randolph , Ming Kwan , Yi He , Zhizheng Liu , Meng Ding
发明人： Wei Zheng , Jean Yang , Mark Randolph , Ming Kwan , Yi He , Zhizheng Liu , Meng Ding
IPC分类号： H01L29/76
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.
摘要翻译：半导体器件包括衬底和形成在衬底上的存储单元。存储单元包括字线。半导体器件还包括形成在衬底中的保护区域，被配置为将字线延伸到保护区域的导电结构以及被配置为使字线和保护区域短路的触点。

8. 发明授权

US07626869B2 Multi-phase wordline erasing for flash memory 有权
标题翻译：闪存多相字线擦除
公开(公告)号：US07626869B2
公开(公告)日：2009-12-01
申请号：US11745327
申请日：2007-05-07
申请人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
发明人： Xuguang Wang , Yi He , Zhizheng Liu , Sung-Yong Chung , Darlene G. Hamilton , Ashot Melik-Martirosian , Gulzar Kathawala , Ming Sang Kwan , Mark Randolph , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： G11C16/16
摘要： Erasing wordlines at the same time can cause undesirable results because some wordlines are affected by electromagnetic waves of other wordlines. However, other wordlines are not affected because they are next to contacts. Therefore, it can be beneficial to erase wordlines in a multi-phase sequence that allows for erasing wordlines without an impact from other wordlines.
摘要翻译：同时删除字线可能会导致不良结果，因为某些字线受到其他字线的电磁波的影响。然而，其他字线不受影响，因为它们在联系人旁边。因此，删除允许擦除字线而不受其他字线影响的多相序列中的字线可能是有益的。

9. 发明授权

US08404541B2 Strapping contact for charge protection 有权
标题翻译：带式触点用于充电保护
公开(公告)号：US08404541B2
公开(公告)日：2013-03-26
申请号：US12790578
申请日：2010-05-28
申请人： Wei Zheng , Jean Yang , Mark Randolph , Ming Kwan , Yi He , Zhizheng Liu , Meng Ding
发明人： Wei Zheng , Jean Yang , Mark Randolph , Ming Kwan , Yi He , Zhizheng Liu , Meng Ding
IPC分类号： H01L21/8247
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.
摘要翻译：半导体器件包括衬底和形成在衬底上的存储单元。存储单元包括字线。半导体器件还包括形成在衬底中的保护区域，被配置为将字线延伸到保护区域的导电结构以及被配置为使字线和保护区域短路的触点。

10. 发明授权

US07167398B1 System and method for erasing a memory cell 有权
标题翻译：擦除存储单元的系统和方法
公开(公告)号：US07167398B1
公开(公告)日：2007-01-23
申请号：US11062641
申请日：2005-02-23
申请人： Zhizheng Liu , Satoshi Torii , Mark Randolph , Yi He
发明人： Zhizheng Liu , Satoshi Torii , Mark Randolph , Yi He
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0475 , G11C16/14 , H01L29/66833 , H01L29/7923
摘要： A method erases a memory cell of a semiconductor device that includes a group of memory cells. Each memory cell includes a group of storage regions. The method includes determining that each storage region of the group of storage regions of a first memory cell is to be erased and erasing the group of storage regions of the first memory cell via a single hot hole injection process.
摘要翻译：一种方法擦除包括一组存储单元的半导体器件的存储单元。每个存储单元包括一组存储区域。该方法包括：通过单个热孔注入处理确定要擦除第一存储器单元组的存储区域的每个存储区域并擦除第一存储单元的存储区域组。

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