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21. 发明授权

US08049527B2 Process, voltage, and temperature sensor 有权
标题翻译：过程，电压和温度传感器
公开(公告)号：US08049527B2
公开(公告)日：2011-11-01
申请号：US12843955
申请日：2010-07-27
申请人： Jung Hee Lee
发明人： Jung Hee Lee
IPC分类号： G01R31/02 , G01R31/00
CPC分类号： G01R31/2601 , H03F1/30 , H03F2200/447
摘要： An integrated circuit includes a process sensor, a temperature sensor, and a voltage sensor. The process sensor is configured to sense a process parameter indicative of a semiconductor process by which the integrated circuit is formed and, based upon the sensed process parameter, to provide a characterization of the semiconductor process to the output of the process sensor. The temperature sensor is configured to provide an indication of a temperature of the integrated circuit to an output of the temperature sensor and the voltage sensor is configured to provide an indication of a power supply voltage level of the integrated circuit to an output of the voltage sensor. The output of the process sensor is coupled to at least one of the temperature sensor and the voltage sensor to compensate at least one of the indication of the temperature and the indication of the power supply voltage level.
摘要翻译：集成电路包括过程传感器，温度传感器和电压传感器。过程传感器被配置为感测指示形成集成电路的半导体工艺的工艺参数，并且基于所感测的工艺参数，以提供对工艺传感器的输出的半导体工艺的表征。温度传感器被配置为提供集成电路的温度到温度传感器的输出的指示，并且电压传感器被配置为提供集成电路的电源电压电平到电压传感器的输出的指示。过程传感器的输出耦合到温度传感器和电压传感器中的至少一个，以补偿温度指示和电源电压电平指示中的至少一个。

22. 发明申请

US20110237079A1 METHOD FOR EXPOSING THROUGH-BASE WAFER VIAS FOR FABRICATION OF STACKED DEVICES 审中-公开
标题翻译：用于制造用于制造堆叠设备的通过基底波形六角形的方法
公开(公告)号：US20110237079A1
公开(公告)日：2011-09-29
申请号：US12888872
申请日：2010-09-23
申请人： Hyoung Sik Kim , Jung Hee Lee , Daniel Hernandez Castillo, II , James Matthew Henry
发明人： Hyoung Sik Kim , Jung Hee Lee , Daniel Hernandez Castillo, II , James Matthew Henry
IPC分类号： H01L21/306 , H01L21/304
CPC分类号： H01L21/30625 , C09G1/02 , H01L21/31053 , H01L21/76898
摘要： An effective method for forming through-base wafer vias for the fabrication of stacked devices, such as electronic devices, is described. The base wafer can be a silicon wafer, in which case the method relates to TSV (through-silicon via) technology. The method affords high removal rates of silicon under appropriate conditions.
摘要翻译：描述了用于形成用于制造诸如电子装置的堆叠装置的通孔晶圆通孔的有效方法。基底晶片可以是硅晶片，在这种情况下，该方法涉及TSV（穿硅通孔）技术。该方法在合适的条件下提供高的硅去除率。

23. 发明申请

US20110233612A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110233612A1
公开(公告)日：2011-09-29
申请号：US12907653
申请日：2010-10-19
申请人： Ki Yeol PARK , Woo Chul Jeon , Young Hwan Park , Jung Hee Lee
发明人： Ki Yeol PARK , Woo Chul Jeon , Young Hwan Park , Jung Hee Lee
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/41725 , H01L29/66462
摘要： There is provided a semiconductor device having a High Electron Mobility Transistor (HEMT) structure allowing for enhanced performance and a method of manufacturing the same. The semiconductor device includes a base substrate; a semiconductor layer provided on the base substrate; a source electrode, a gate electrode and a drain electrode provided on the semiconductor layer to be spaced apart from one another; and an ohmic-contact layer partially provided at an interface between the drain electrode and the semiconductor layer.
摘要翻译：提供了具有允许增强性能的高电子迁移率晶体管（HEMT）结构的半导体器件及其制造方法。半导体器件包括：基底; 设置在所述基底基板上的半导体层; 源电极，栅电极和漏极，设置在所述半导体层上以彼此间隔开; 以及部分地设置在漏电极和半导体层之间的界面处的欧姆接触层。

24. 发明申请

US20110057234A1 Semiconductor device and method for manufacturing of the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20110057234A1
公开(公告)日：2011-03-10
申请号：US12654940
申请日：2010-01-08
申请人： Woo Chul Jeon , Jung Hee Lee , Young Hwan Park , Ki Yeol Park
发明人： Woo Chul Jeon , Jung Hee Lee , Young Hwan Park , Ki Yeol Park
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/66007 , H01L21/02521 , H01L29/0692 , H01L29/2003 , H01L29/66143 , H01L29/872
摘要： Disclosed is a semiconductor device including: a base substrate; a semiconductor layer disposed on the base substrate; an ohmic electrode part which has ohmic electrode lines disposed in a first direction, on the semiconductor layer; and a Schottky electrode part which is disposed to be spaced apart from the ohmic electrode lines on the semiconductor layer and includes Schottky electrode lines disposed in the first direction, wherein the Schottky electrode lines and the ohmic electrode lines are alternately disposed in parallel, and the ohmic electrode part further includes first ohmic electrodes covered by the Schottky electrode lines on the semiconductor layer.
摘要翻译：公开了一种半导体器件，包括：基底; 设置在所述基底基板上的半导体层; 在所述半导体层上具有沿第一方向设置的欧姆电极线的欧姆电极部; 以及肖特基电极部，其设置为与半导体层上的欧姆电极线间隔开，并且包括沿第一方向设置的肖特基电极线，其中肖特基电极线和欧姆电极线交替地平行设置，并且欧姆电极部分还包括由半导体层上的肖特基电极线覆盖的第一欧姆电极。

25. 发明申请

US20110057231A1 Semiconductor device and method for manufacturing of the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20110057231A1
公开(公告)日：2011-03-10
申请号：US12654897
申请日：2010-01-07
申请人： Woo Chul Jeon , Jung Hee Lee , Young Hwan Park , Ki Yeol Park
发明人： Woo Chul Jeon , Jung Hee Lee , Young Hwan Park , Ki Yeol Park
IPC分类号： H01L29/47 , H01L21/20 , H01L21/28
CPC分类号： H01L29/0692 , H01L29/861 , H01L29/872
摘要： The present invention provides a semiconductor device including: a base substrate; a first semiconductor layer disposed on the base substrate; first ohmic electrodes disposed on a central region of the first semiconductor layer; a second ohmic electrode having a ring shape surrounding the first ohmic electrodes, on edge regions of the first semiconductor layer; a second semiconductor layer interposed between the first ohmic electrodes and the first semiconductor layer; and a Schottky electrode part which covers the first ohmic electrodes on the central regions, and is spaced apart from the second ohmic electrode.
摘要翻译：本发明提供一种半导体器件，包括：基底; 设置在所述基底基板上的第一半导体层; 设置在第一半导体层的中心区域上的第一欧姆电极; 在所述第一半导体层的边缘区域上具有围绕所述第一欧姆电极的环形形状的第二欧姆电极; 插入在所述第一欧姆电极和所述第一半导体层之间的第二半导体层; 以及肖特基电极部件，其覆盖中心区域上的第一欧姆电极，并且与第二欧姆电极间隔开。

26. 发明申请

US20110029266A1 PROCESS, VOLTAGE, AND TEMPERATURE SENSOR 有权
标题翻译：过程，电压和温度传感器
公开(公告)号：US20110029266A1
公开(公告)日：2011-02-03
申请号：US12843955
申请日：2010-07-27
申请人： Jung Hee Lee
发明人： Jung Hee Lee
IPC分类号： G06F19/00
CPC分类号： G01R31/2601 , H03F1/30 , H03F2200/447
摘要： An integrated circuit includes a process sensor, a temperature sensor, and a voltage sensor. The process sensor is configured to sense a process parameter indicative of a semiconductor process by which the integrated circuit is formed and, based upon the sensed process parameter, to provide a characterization of the semiconductor process to the output of the process sensor. The temperature sensor is configured to provide an indication of a temperature of the integrated circuit to an output of the temperature sensor and the voltage sensor is configured to provide an indication of a power supply voltage level of the integrated circuit to an output of the voltage sensor. The output of the process sensor is coupled to at least one of the temperature sensor and the voltage sensor to compensate at least one of the indication of the temperature and the indication of the power supply voltage level.
摘要翻译：集成电路包括过程传感器，温度传感器和电压传感器。过程传感器被配置为感测指示形成集成电路的半导体工艺的工艺参数，并且基于所感测的工艺参数，以提供对工艺传感器的输出的半导体工艺的表征。温度传感器被配置为提供集成电路的温度到温度传感器的输出的指示，并且电压传感器被配置为提供集成电路的电源电压电平到电压传感器的输出的指示。过程传感器的输出耦合到温度传感器和电压传感器中的至少一个，以补偿温度指示和电源电压电平指示中的至少一个。

27. 发明授权

US07400001B2 Nitride based hetero-junction field effect transistor 失效
标题翻译：基于氮化物的异质结场效应晶体管
公开(公告)号：US07400001B2
公开(公告)日：2008-07-15
申请号：US10998942
申请日：2004-11-30
申请人： Jae Hoon Lee , Jung Hee Lee
发明人： Jae Hoon Lee , Jung Hee Lee
IPC分类号： H01L29/778
CPC分类号： H01L29/7787 , H01L29/2003
摘要： A nitride based hetero-junction field effect transistor includes a high resistance nitride semiconductor layer formed on a substrate, an Al-doped GaN layer formed on the high resistance nitride semiconductor layer and having an Al content of 0.1˜1%, an undoped GaN layer formed on the Al-doped GaN layer, and an AlGaN layer formed on the undoped GaN layer such that a two-dimensional electron gas (2DEG) layer is formed at an interface of the undoped GaN layer.
摘要翻译：氮化物基异质结场效应晶体管包括形成在衬底上的高电阻氮化物半导体层，形成在高电阻氮化物半导体层上且Al含量为0.1〜1％的Al掺杂GaN层，未掺杂的GaN层形成在Al掺杂GaN层上的AlGaN层和形成在未掺杂的GaN层上的AlGaN层，使得在未掺杂的GaN层的界面处形成二维电子气（2DEG）层。

28. 发明授权

US08980049B2 Apparatus for supporting substrate and plasma etching apparatus having the same 有权
标题翻译：用于支撑基板的等离子体蚀刻装置
公开(公告)号：US08980049B2
公开(公告)日：2015-03-17
申请号：US12531068
申请日：2008-04-01
申请人： Won Haeng Lee , Kwan Goo Rha , Jung Hee Lee , Chul Hee Jang , Hyang Joo Lee , Dong Wan Kim
发明人： Won Haeng Lee , Kwan Goo Rha , Jung Hee Lee , Chul Hee Jang , Hyang Joo Lee , Dong Wan Kim
IPC分类号： C23C16/00 , H01L21/306 , H01L21/67 , H01L21/683 , H01L21/687
CPC分类号： H01L21/67069 , H01L21/6831 , H01L21/68742
摘要： Provided are a substrate supporting apparatus and a plasma etching apparatus having the same. There is provided a substrate supporting apparatus that can separately provide powers to a central region and an edge region by disposing an electrode supporting a substrate at the central region of the substrate supporting apparatus, and disposing an electrode receiving radio frequency (RF) power at the edge region of the substrate supporting apparatus. There is provided a substrate edge etching apparatus having the substrate supporting apparatus for removing layers or particles deposited in an edge region of a semiconductor substrate and preventing damage of a center region of the semiconductor substrate during an etching process of the substrate edge.
摘要翻译：提供了一种基板支撑装置和具有该基板支撑装置的等离子体蚀刻装置。提供了一种基板支撑装置，其可以通过在基板支撑装置的中心区域设置支撑基板的电极，并且在该基板支撑装置的中心区域设置接收射频（RF）电力的电极，边缘区域。提供了一种基板边缘蚀刻装置，其具有用于去除沉积在半导体基板的边缘区域中的层或颗粒的基板支撑装置，并且防止在基板边缘的蚀刻处理期间对半导体基板的中心区域的损坏。

29. 发明授权

US08911775B2 pH-sensitive block copolymer forming polyionic complex micelles and drug or protein carrier using the same 有权
标题翻译：形成多聚离子复合物胶束的pH敏感嵌段共聚物和使用其的药物或蛋白质载体
公开(公告)号：US08911775B2
公开(公告)日：2014-12-16
申请号：US12842388
申请日：2010-07-23
申请人： Doo Sung Lee , Bong Sup Kim , Jung Hee Lee , Guanghui Gao
发明人： Doo Sung Lee , Bong Sup Kim , Jung Hee Lee , Guanghui Gao
IPC分类号： A61K38/38 , C08G73/06 , A61K9/127 , A61P35/00 , A61P9/10 , A61P29/00 , A61P19/02 , C08L71/02 , C08F299/02 , B82Y5/00 , C08F290/06 , A61K9/107
CPC分类号： C08F290/062 , A61K9/1075 , B82Y5/00 , C08F299/024 , C08G2261/126 , C08L71/02 , C08L2201/06 , C08L2203/02 , C08L2205/05 , C08L67/00
摘要： Disclosed is a pH-sensitive block copolymer that forms polyionic complex micelles. The block copolymer is prepared by copolymerization of (a) a polyethylene glycol compound, (b) a poly(amino acid) compound, and (c) a heterocyclic alkyl amine compound having the ability to induce the formation of ionic complexes. Further disclosed is a drug or protein carrier using the block copolymer.
摘要翻译：公开了形成聚离子复合物胶束的pH敏感性嵌段共聚物。嵌段共聚物通过（a）聚乙二醇化合物，（b）聚（氨基酸）化合物和（c）具有诱导形成离子络合物的能力的杂环烷基胺化合物的共聚制备。还公开了使用嵌段共聚物的药物或蛋白质载体。

30. 发明授权

US08735940B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08735940B2
公开(公告)日：2014-05-27
申请号：US12965640
申请日：2010-12-10
申请人： Woo Chul Jeon , Ki Yeol Park , Young Hwan Park , Jung Hee Lee
发明人： Woo Chul Jeon , Ki Yeol Park , Young Hwan Park , Jung Hee Lee
IPC分类号： H01L29/66
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/66462
摘要： There are provided a semiconductor device and a method for manufacturing the same. The semiconductor device according to the present invention includes a base substrate; a semiconductor layer that includes a receiving groove and a protrusion part formed on the base substrate, a first carrier injection layer and at least two insulating layers formed to traverse the first carrier injection layer formed in the semiconductor layer, and a second carrier injection layer spaced apart from the first carrier injection layer formed on the protrusion part; a source electrode and a drain electrode that are disposed to be spaced apart from each other on the semiconductor layer; and a gate electrode that is insulated from the source electrode and the drain electrode and has a recess part recessed into the receiving groove, wherein the lowest end portion of the receiving groove contacts the uppermost layer of the first carrier injection layer and the insulating pattern disposed at the innermost side of the semiconductor layer among the insulating patterns traverses the entire layer forming the first carrier injection layer and is disposed at the outer side of both side end portions in the thickness direction of the receiving groove.
摘要翻译：提供了一种半导体器件及其制造方法。根据本发明的半导体器件包括：基底; 半导体层，其包括形成在所述基底基板上的接收槽和突出部，第一载流子注入层和形成为穿过形成在所述半导体层中的所述第一载流子注入层的至少两个绝缘层，以及间隔开的第二载流子注入层除了形成在突出部上的第一载流子注入层之外; 源电极和漏电极，其设置成在半导体层上彼此间隔开; 以及与源电极和漏电极绝缘并且具有凹入到接收槽中的凹部的栅电极，其中接收槽的最低端部接触第一载流子注入层的最上层，并且布置的绝缘图案在绝缘图案中的半导体层的最内侧穿过形成第一载流子注入层的整个层，并且设置在接收槽的厚度方向上的两个侧端部的外侧。

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