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21. 发明授权

US6074906A Complementary metal-oxide semiconductor device having source/drain regions formed using multiple spacers 失效
标题翻译：具有使用多个间隔物形成的源/漏区的互补金属氧化物半导体器件
公开(公告)号：US6074906A
公开(公告)日：2000-06-13
申请号：US958534
申请日：1997-10-27
申请人： Jon Cheek , Derick J. Wristers , H. Jim Fulford
发明人： Jon Cheek , Derick J. Wristers , H. Jim Fulford
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864
摘要： A CMOS semiconductor device having NMOS source/drain regions formed using multiple spacers has at least one NMOS region and at least one PMOS region. A first n-type dopant is selectively implanted into an NMOS active region of the substrate adjacent a NMOS gate electrode to form a first n-doped region in the NMOS active region. A first NMOS spacer is formed on a sidewall of the NMOS gate electrode and a first PMOS spacer on a sidewall of a PMOS gate electrode. A second n-type dopant is selectively implanted into the NMOS active region using the first NMOS spacer as a mask. A p-type dopant is selectively implanted into a PMOS active region using the first PMOS spacer as a mask to form a first p-doped region in the PMOS active region. A second NMOS spacer and a second PMOS spacer are formed adjacent the first NMOS spacer and first PMOS spacer, respectively. A third n-type dopant is selectively implanted into the NMOS active region using the second NMOS spacer as a mask to form a third n-doped region deeper than the second n-doped region in the NMOS active region. A second p-type dopant is selectively implanted into the PMOS active region using the second PMOS spacer as a mask to form a second p-doped region in the PMOS active region deeper than the first p-doped region.
摘要翻译：具有使用多个间隔物形成的NMOS源极/漏极区域的CMOS半导体器件具有至少一个NMOS区域和至少一个PMOS区域。第一n型掺杂剂被选择性地注入到与NMOS栅电极相邻的衬底的NMOS有源区中，以在NMOS有源区中形成第一n掺杂区。第一NMOS间隔物形成在NMOS栅电极的侧壁和PMOS栅电极的侧壁上的第一PMOS间隔物上。使用第一NMOS间隔物作为掩模，将第二n型掺杂剂选择性地注入NMOS有源区。使用第一PMOS间隔物作为掩模将p型掺杂剂选择性地注入PMOS有源区，以在PMOS有源区中形成第一p掺杂区。分别与第一NMOS间隔物和第一PMOS间隔物相邻地形成第二NMOS间隔物和第二PMOS间隔物。使用第二NMOS间隔物作为掩模，将第三n型掺杂剂选择性地注入NMOS有源区，以形成比NMOS有源区中的第二n掺杂区更深的第三n掺杂区。使用第二PMOS间隔物作为掩模将第二p型掺杂剂选择性地注入到PMOS有源区中，以在PMOS有源区中形成比第一p掺杂区更深的第二p掺杂区。

22. 发明授权

US5970311A Method and structure for optimizing the performance of a semiconductor device having dense transistors 失效
标题翻译：用于优化具有致密晶体管的半导体器件的性能的方法和结构
公开(公告)号：US5970311A
公开(公告)日：1999-10-19
申请号：US961980
申请日：1997-10-31
申请人： Jon Cheek , Daniel Kadosh , Derick J. Wristers
发明人： Jon Cheek , Daniel Kadosh , Derick J. Wristers
IPC分类号： H01L21/66 , H01L23/544 , H01L21/00 , G01R31/26
CPC分类号： H01L22/20 , H01L22/34 , H01L2924/0002
摘要： A method and structure for optimizing the performance of a semiconductor device having dense transistors. A method consistent with the present invention includes forming a first test structure on a first substrate portion. The first test structure includes a transistor having a gate electrode formed at a design width and at a first line spacing similar to the line spacing of a dense transistor. One or more electrical properties the transistor of the first test structure is measured. A second test structure is formed on a second substrate portion. The second test structure includes a transistor having a gate electrode formed at the same design width as the transistor of the first test structure and at a second line spacing greater than the first line spacing. One or more electrical properties of the transistor of the second test structure are measured. Using the measured one or more electrical properties, one or more relationships are developed between the measured one or more electrical properties and the transistors at the first line spacing and the second line spacing.
摘要翻译：一种用于优化具有致密晶体管的半导体器件的性能的方法和结构。与本发明一致的方法包括在第一衬底部分上形成第一测试结构。第一测试结构包括晶体管，其晶体管具有以类似于致密晶体管的线间距的设计宽度和第一行间距形成的栅电极。测量第一测试结构的晶体管的一个或多个电特性。在第二基板部分上形成第二测试结构。第二测试结构包括晶体管，其晶体管具有与第一测试结构的晶体管相同的设计宽度并且在大于第一线间距的第二线间距处形成栅电极。测量第二测试结构的晶体管的一个或多个电特性。使用所测量的一个或多个电性能，在所测量的一个或多个电性能和在第一线间距和第二线间距处的晶体管之间形成一个或多个关系。

23. 发明授权

US07253484B2 Low-power multiple-channel fully depleted quantum well CMOSFETs 有权
标题翻译：低功耗多通道全耗尽量子阱CMOSFET
公开(公告)号：US07253484B2
公开(公告)日：2007-08-07
申请号：US11445345
申请日：2006-06-02
申请人： James N. Pan , John G. Pellerin , Jon Cheek
发明人： James N. Pan , John G. Pellerin , Jon Cheek
IPC分类号： H01L27/088 , H01L29/78 , H01L21/336
CPC分类号： H01L29/78696 , H01L29/78639
摘要： A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.
摘要翻译：多通道半导体器件具有完全或部分耗尽的量子阱，并且在超大规模集成器件（例如CMOSFET）中特别有用。多个通道区域设置在基板上，其栅电极形成在最上通道区域上，例如由栅极氧化物分隔开。多通道和栅电极的垂直堆叠允许增加半导体器件中的驱动电流，而不增加器件占用的硅面积。

24. 发明申请

US20050196928A1 Method of reducing STI divot formation during semiconductor device fabrication 有权
标题翻译：在半导体器件制造期间减少STI纹路形成的方法
公开(公告)号：US20050196928A1
公开(公告)日：2005-09-08
申请号：US10791759
申请日：2004-03-04
申请人： Douglas Bonser , Johannes Groschopf , Srikanteswara Dakshina-Murthy , John Pellerin , Jon Cheek
发明人： Douglas Bonser , Johannes Groschopf , Srikanteswara Dakshina-Murthy , John Pellerin , Jon Cheek
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/336
CPC分类号： H01L21/76224
摘要： STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g., no thicker than 400 Å. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions, and is removed prior to gate oxide and gate electrode formation.
摘要翻译：通过使用非常薄的氮化物抛光停止层例如不厚于400来消除或显着降低STI纹线形成。非常薄的氮化物抛光停止层在随后的掩模，注入和清洁步骤中保持就位以形成掺杂剂区域，并且在栅极氧化物和栅电极形成之前被去除。

25. 发明授权

US5913116A Method of manufacturing an active region of a semiconductor by diffusing a dopant out of a sidewall spacer 失效
标题翻译：通过从侧壁间隔物扩散掺杂剂来制造半导体的有源区的方法
公开(公告)号：US5913116A
公开(公告)日：1999-06-15
申请号：US780455
申请日：1997-01-08
申请人： Mark I. Gardner , Jon Cheek
发明人： Mark I. Gardner , Jon Cheek
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864
摘要： In semiconductor device fabrication process, an active region of a semiconductor device is formed by diffusing a dopant out of a sidewall spacer. In the fabrication process, a gate electrode having a sidewall adjacent an active region is formed on a substrate and a doped spacer layer having a dopant disposed therein is formed over the substrate and gate electrode. A portion of the spacer layer is then removed to form a spacer on the sidewall of the gate electrode. The dopant in the spacer is diffused into the substrate to form a lightly-doped region in the active region of the substrate. The lightly-doped region may form an LDD region of an LDD structure.
摘要翻译：在半导体器件制造工艺中，半导体器件的有源区通过从侧壁间隔物扩散出来形成。在制造工艺中，在衬底上形成具有邻近有源区的侧壁的栅电极，并且在衬底和栅电极上形成其中具有掺杂剂的掺杂间隔层。然后去除间隔层的一部分以在栅电极的侧壁上形成间隔物。间隔物中的掺杂剂扩散到衬底中以在衬底的有源区中形成轻掺杂区域。轻掺杂区域可以形成LDD结构的LDD区域。

26. 发明授权

US07235433B2 Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device 失效
标题翻译：具有不同晶体取向的硅层的绝缘体上半导体器件和形成绝缘体上硅半导体器件的方法
公开(公告)号：US07235433B2
公开(公告)日：2007-06-26
申请号：US10976780
申请日：2004-11-01
申请人： Andrew M. Waite , Jon Cheek
发明人： Andrew M. Waite , Jon Cheek
IPC分类号： H01L21/84
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78654
摘要： A semiconductor device comprising a substrate having a first crystal orientation and an insulating layer overlying the substrate is provided. A plurality of silicon layers are formed overlying the insulating layer. A first silicon layer comprises silicon having the first crystal orientation and a second silicon layer comprises silicon having a second crystal orientation. In addition, a method of forming a semiconductor device providing a silicon-on-insulator structure comprising a substrate with a silicon layer overlying the substrate and a first insulating layer interposed therebetween is provided. An opening is formed in a first region of the silicon-on-insulator structure by removing a portion of the silicon layer and the first insulating layer to expose a portion of the substrate layer. Selective epitaxial silicon is grown in the opening. A second insulating layer is formed in the silicon grown in the opening to provide an insulating layer between the grown silicon in the opening and the substrate.
摘要翻译：提供了包括具有第一晶体取向的衬底和覆盖在衬底上的绝缘层的半导体器件。在绝缘层上形成多个硅层。第一硅层包括具有第一晶体取向的硅，而第二硅层包含具有第二晶体取向的硅。此外，提供一种形成提供绝缘体上硅结构的半导体器件的方法，该半导体器件包括具有覆盖在衬底上的硅层的衬底和插入其间的第一绝缘层。通过去除硅层和第一绝缘层的一部分以露出衬底层的一部分，在绝缘体上硅结构的第一区域中形成开口。选择性外延硅在开口中生长。在开口中生长的硅中形成第二绝缘层，以在开口中的生长的硅和衬底之间提供绝缘层。

27. 发明申请

US20060278938A1 Low-power multiple-channel fully depleted quantum well CMOSFETs 有权
公开(公告)号：US20060278938A1
公开(公告)日：2006-12-14
申请号：US11445345
申请日：2006-06-02
申请人： James Pan , John Pellerin , Jon Cheek
发明人： James Pan , John Pellerin , Jon Cheek
IPC分类号： H01L29/76
CPC分类号： H01L29/78696 , H01L29/78639
摘要： A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.

28. 发明申请

US20060091427A1 Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device 失效
标题翻译：具有不同晶体取向的硅层的绝缘体上半导体器件和形成绝缘体上硅半导体器件的方法
公开(公告)号：US20060091427A1
公开(公告)日：2006-05-04
申请号：US10976780
申请日：2004-11-01
申请人： Andrew Waite , Jon Cheek
发明人： Andrew Waite , Jon Cheek
IPC分类号： H01L29/76
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/78654
摘要： A semiconductor device comprising a substrate having a first crystal orientation and an insulating layer overlying the substrate is provided. A plurality of silicon layers are formed overlying the insulating layer. A first silicon layer comprises silicon having the first crystal orientation and a second silicon layer comprises silicon having a second crystal orientation. In addition, a method of forming a semiconductor device providing a silicon-on-insulator structure comprising a substrate with a silicon layer overlying the substrate and a first insulating layer interposed therebetween is provided. An opening is formed in a first region of the silicon-on-insulator structure by removing a portion of the silicon layer and the first insulating layer to expose a portion of the substrate layer. Selective epitaxial silicon is grown in the opening. A second insulating layer is formed in the silicon grown in the opening to provide an insulating layer between the grown silicon in the opening and the substrate.
摘要翻译：提供了包括具有第一晶体取向的衬底和覆盖在衬底上的绝缘层的半导体器件。在绝缘层上形成多个硅层。第一硅层包括具有第一晶体取向的硅，而第二硅层包含具有第二晶体取向的硅。此外，提供一种形成提供绝缘体上硅结构的半导体器件的方法，该半导体器件包括具有覆盖在衬底上的硅层的衬底和插入其间的第一绝缘层。通过去除硅层和第一绝缘层的一部分以露出衬底层的一部分，在绝缘体上硅结构的第一区域中形成开口。选择性外延硅在开口中生长。在开口中生长的硅中形成第二绝缘层，以在开口中的生长的硅和衬底之间提供绝缘层。

29. 发明申请

US20050104140A1 Low-power multiple-channel fully depleted quantum well CMOSFETs 有权
标题翻译：低功耗多通道全耗尽量子阱CMOSFET
公开(公告)号：US20050104140A1
公开(公告)日：2005-05-19
申请号：US10706948
申请日：2003-11-14
申请人： James Pan , John Pellerin , Jon Cheek
发明人： James Pan , John Pellerin , Jon Cheek
IPC分类号： H01L29/786 , H01L31/062
CPC分类号： H01L29/78696 , H01L29/78639
摘要： A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.
摘要翻译：多通道半导体器件具有完全或部分耗尽的量子阱，并且在超大规模集成器件（例如CMOSFET）中特别有用。多个通道区域设置在基板上，其栅电极形成在最上通道区域上，例如由栅极氧化物分隔开。多通道和栅电极的垂直堆叠允许增加半导体器件中的驱动电流，而不增加器件占用的硅面积。

30. 发明授权

US06300205B1 Method of making a semiconductor device with self-aligned active, lightly-doped drain, and halo regions 有权
标题翻译：制造具有自对准有源，轻掺杂漏极和卤区的半导体器件的方法
公开(公告)号：US06300205B1
公开(公告)日：2001-10-09
申请号：US09193262
申请日：1998-11-18
申请人： H. Jim Fulford , Jon Cheek , Derick J. Wristers , James Buller
发明人： H. Jim Fulford , Jon Cheek , Derick J. Wristers , James Buller
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L21/26586 , H01L29/1083 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： One method of making a semiconductor device includes forming a gate electrode on a substrate and forming a spacer on a sidewall of the gate electrode. An active region is then formed in the substrate and adjacent to the spacer, but spaced apart from the gate electrode, using a first dopant material. A halo region is formed in the substrate under the spacer and adjacent to the active region using a second dopant material of a conductivity type different than the first dopant material. The halo region may be formed by implanting the second dopant region into the substrate at an angle substantially less than 90° relative to a surface of the substrate. A portion of the spacer is then removed and a lightly-doped region is formed in the substrate adjacent to the active region and the gate electrode and shallower than the halo region using a third dopant material of a same conductivity type as the first dopant material.
摘要翻译：制造半导体器件的一种方法包括在衬底上形成栅电极并在栅电极的侧壁上形成间隔物。然后，使用第一掺杂剂材料，在衬底中形成有源区并与间隔物相邻，但与栅电极间隔开。使用不同于第一掺杂剂材料的导电类型的第二掺杂剂材料，在间隔物下方的衬底中形成晕圈区域并与有源区相邻。可以通过相对于衬底的表面以相对小于90°的角度将第二掺杂剂区域注入到衬底中来形成晕圈区域。然后去除间隔物的一部分，并且使用与第一掺杂剂材料相同的导电类型的第三掺杂剂材料，在邻近有源区和栅电极的衬底中形成轻掺杂区域，并且比晕区浅。

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