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1. 发明申请

US20060278938A1 Low-power multiple-channel fully depleted quantum well CMOSFETs 有权
公开(公告)号：US20060278938A1
公开(公告)日：2006-12-14
申请号：US11445345
申请日：2006-06-02
申请人： James Pan , John Pellerin , Jon Cheek
发明人： James Pan , John Pellerin , Jon Cheek
IPC分类号： H01L29/76
CPC分类号： H01L29/78696 , H01L29/78639
摘要： A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.

2. 发明申请

US20050104140A1 Low-power multiple-channel fully depleted quantum well CMOSFETs 有权
标题翻译：低功耗多通道全耗尽量子阱CMOSFET
公开(公告)号：US20050104140A1
公开(公告)日：2005-05-19
申请号：US10706948
申请日：2003-11-14
申请人： James Pan , John Pellerin , Jon Cheek
发明人： James Pan , John Pellerin , Jon Cheek
IPC分类号： H01L29/786 , H01L31/062
CPC分类号： H01L29/78696 , H01L29/78639
摘要： A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.
摘要翻译：多通道半导体器件具有完全或部分耗尽的量子阱，并且在超大规模集成器件（例如CMOSFET）中特别有用。多个通道区域设置在基板上，其栅电极形成在最上通道区域上，例如由栅极氧化物分隔开。多通道和栅电极的垂直堆叠允许增加半导体器件中的驱动电流，而不增加器件占用的硅面积。

3. 发明申请

US20050196928A1 Method of reducing STI divot formation during semiconductor device fabrication 有权
标题翻译：在半导体器件制造期间减少STI纹路形成的方法
公开(公告)号：US20050196928A1
公开(公告)日：2005-09-08
申请号：US10791759
申请日：2004-03-04
申请人： Douglas Bonser , Johannes Groschopf , Srikanteswara Dakshina-Murthy , John Pellerin , Jon Cheek
发明人： Douglas Bonser , Johannes Groschopf , Srikanteswara Dakshina-Murthy , John Pellerin , Jon Cheek
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/336
CPC分类号： H01L21/76224
摘要： STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g., no thicker than 400 Å. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions, and is removed prior to gate oxide and gate electrode formation.
摘要翻译：通过使用非常薄的氮化物抛光停止层例如不厚于400来消除或显着降低STI纹线形成。非常薄的氮化物抛光停止层在随后的掩模，注入和清洁步骤中保持就位以形成掺杂剂区域，并且在栅极氧化物和栅电极形成之前被去除。

4. 发明授权

US07091118B1 Replacement metal gate transistor with metal-rich silicon layer and method for making the same 有权
标题翻译：具有富金属硅层的替代金属栅极晶体管及其制造方法
公开(公告)号：US07091118B1
公开(公告)日：2006-08-15
申请号：US10988532
申请日：2004-11-16
申请人： James Pan , John Pellerin , Linda R. Black , Michael Chudzik , Rajarao Jammy
发明人： James Pan , John Pellerin , Linda R. Black , Michael Chudzik , Rajarao Jammy
IPC分类号： H01L21/3205 , H01L21/338
CPC分类号： H01L29/7833 , H01L21/28052 , H01L29/66545 , H01L29/66583
摘要： A semiconductor device with a replacement metal gate and the process for making the same removes a dummy gate from a semiconductor device. Within the recess left by the dummy gate is a silicon layer on a gate dielectric layer. A replacement metal is deposited on the thin silicon layer and then reacted with the silicon layer to form a metal-rich silicon layer on the gate dielectric layer.
摘要翻译：具有替换金属栅极的半导体器件及其制造方法从半导体器件中去除虚拟栅极。在虚拟栅极留下的凹槽内是栅介质层上的硅层。替代金属沉积在薄硅层上，然后与硅层反应，以在栅极介电层上形成富含金属的硅层。

5. 发明授权

US07544572B2 Multi-operational mode transistor with multiple-channel device structure 失效
标题翻译：具有多通道器件结构的多工作晶体管
公开(公告)号：US07544572B2
公开(公告)日：2009-06-09
申请号：US11289682
申请日：2005-11-30
申请人： James Pan , John Pellerin
发明人： James Pan , John Pellerin
IPC分类号： H01L21/336
CPC分类号： H01L29/7838 , H01L29/66628 , H01L29/7834
摘要： A multiple operating mode transistor is provided in which multiple channels having different respective operational characteristics are employed. Multiple channels have threshold voltages that are independently adjustable. The independent adjustment of the threshold voltage includes providing at least one of different respective doping concentrations in the different channels, different respective gate dielectric thicknesses for the different gate dielectrics separating the channels, and different respective silicon channel thicknesses for the different channels.
摘要翻译：提供了一种多工作模式晶体管，其中采用具有不同相应操作特性的多个通道。多个通道具有可独立调节的阈值电压。阈值电压的独立调整包括在不同通道中提供不同的相应掺杂浓度中的至少一个，用于不同栅极电介质分离沟道的各自的栅介质厚度以及用于不同通道的不同的相应的硅沟道厚度。

6. 发明授权

US08053849B2 Replacement metal gate transistors with reduced gate oxide leakage 有权
标题翻译：替代金属栅极晶体管，栅极氧化物泄漏减少
公开(公告)号：US08053849B2
公开(公告)日：2011-11-08
申请号：US11269745
申请日：2005-11-09
申请人： James Pan , John Pellerin
发明人： James Pan , John Pellerin
IPC分类号： H01L21/02
CPC分类号： H01L21/28008 , H01L21/28088 , H01L21/28238 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： Thin effective gate oxide thickness with reduced leakage for replacement metal gate transistors is achieved by forming a protective layer between the gate oxide layer and metal gate electrode, thereby reducing stress. Embodiments include forming a protective layer of amorphous carbon containing metal carbides decreasing in concentration from the metal gate electrode toward the gate oxide layer across the protective layer. Embodiments of methodology include removing the removable gate, depositing a layer of amorphous carbon on the gate oxide layer, forming the metal gate electrode and then heating at an elevated temperature to diffuse metal from the metal gate electrode into the amorphous carbon layer, thereby forming the metal carbides. Embodiments also include metal gate transistors with a gate oxide layer having a high dielectric constant and silicon concentrated at the interfaces with the metal gate electrode and substrate.
摘要翻译：通过在栅极氧化层和金属栅电极之间形成保护层来实现用于替换金属栅极晶体管的具有减小的泄漏的薄的有效栅极氧化物厚度，从而降低应力。实施例包括形成从金属栅电极朝向保护层的栅极氧化物层浓缩的含有金属碳化物的非晶碳保护层。方法的实施例包括去除可移除栅极，在栅极氧化物层上沉积无定形碳层，形成金属栅电极，然后在升高的温度下加热以使金属从金属栅电极扩散到无定形碳层中，从而形成金属碳化物。实施例还包括具有高介电常数的栅极氧化物层和在与金属栅电极和衬底的界面处集中的硅的金属栅极晶体管。

7. 发明授权

US08445975B2 Replacement metal gate transistors with reduced gate oxide leakage 有权
标题翻译：替代金属栅极晶体管，栅极氧化物泄漏减少
公开(公告)号：US08445975B2
公开(公告)日：2013-05-21
申请号：US13290275
申请日：2011-11-07
申请人： James Pan , John Pellerin
发明人： James Pan , John Pellerin
IPC分类号： H01L21/02
CPC分类号： H01L21/28008 , H01L21/28088 , H01L21/28238 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor device has a substrate, a gate dielectric layer, and a metal gate electrode on the gate dielectric layer. The gate dielectric layer includes an oxide layer having a dielectric constant (k) greater than 4, and silicon concentrated at interfaces of the oxide layer with the substrate and with the metal gate electrode. A method of fabricating a semiconductor device includes forming a removable gate over a substrate with a gate dielectric layer between the removable gate and the substrate, forming a dielectric layer over the substrate and exposing an upper surface of the removable gate, removing the removable gate leaving an opening in the dielectric layer, forming a protective layer on the gate dielectric layer and lining the opening, and forming a metal gate electrode in the opening. The protective layer has a graded composition between the gate dielectric layer and the metal gate electrode.
摘要翻译：半导体器件在栅极电介质层上具有衬底，栅极电介质层和金属栅电极。栅极电介质层包括介电常数（k）大于4的氧化物层，并且硅集中在氧化物层与衬底和金属栅电极的界面处。一种制造半导体器件的方法包括在衬底上形成可移除栅极，在可移除栅极和衬底之间具有栅极电介质层，在衬底上形成电介质层并露出可移除栅极的上表面，去除可移除栅极离开在电介质层中形成开口，在栅极电介质层上形成保护层并衬套开口，并在开口中形成金属栅电极。保护层在栅极电介质层和金属栅电极之间具有渐变组成。

8. 发明申请

US20120049196A1 REPLACEMENT METAL GATE TRANSISTORS WITH REDUCED GATE OXIDE LEAKAGE 有权
标题翻译：更换具有减少栅极氧化物泄漏的金属栅极晶体管
公开(公告)号：US20120049196A1
公开(公告)日：2012-03-01
申请号：US13290275
申请日：2011-11-07
申请人： James Pan , John Pellerin
发明人： James Pan , John Pellerin
IPC分类号： H01L29/786 , H01L21/28
CPC分类号： H01L21/28008 , H01L21/28088 , H01L21/28238 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： A semiconductor device has a substrate, a gate dielectric layer, and a metal gate electrode on the gate dielectric layer. The gate dielectric layer includes an oxide layer having a dielectric constant (k) greater than 4, and silicon concentrated at interfaces of the oxide layer with the substrate and with the metal gate electrode. A method of fabricating a semiconductor device includes forming a removable gate over a substrate with a gate dielectric layer between the removable gate and the substrate, forming a dielectric layer over the substrate and exposing an upper surface of the removable gate, removing the removable gate leaving an opening in the dielectric layer, forming a protective layer on the gate dielectric layer and lining the opening, and forming a metal gate electrode in the opening. The protective layer has a graded composition between the gate dielectric layer and the metal gate electrode.
摘要翻译：半导体器件在栅极电介质层上具有衬底，栅极电介质层和金属栅电极。栅极电介质层包括介电常数（k）大于4的氧化物层，并且硅集中在氧化物层与衬底和金属栅电极的界面处。一种制造半导体器件的方法包括在衬底上形成可移除栅极，在可移除栅极和衬底之间具有栅极电介质层，在衬底上形成电介质层并露出可移除栅极的上表面，去除可移除栅极离开在电介质层中形成开口，在栅极电介质层上形成保护层并衬套开口，并在开口中形成金属栅电极。保护层在栅极电介质层和金属栅电极之间具有渐变组成。

9. 发明申请

US20070122983A1 Multi-operational mode transistor with multiple-channel device structure 失效
标题翻译：具有多通道器件结构的多工作晶体管
公开(公告)号：US20070122983A1
公开(公告)日：2007-05-31
申请号：US11289682
申请日：2005-11-30
申请人： James Pan , John Pellerin
发明人： James Pan , John Pellerin
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/7838 , H01L29/66628 , H01L29/7834
摘要： A multiple operating mode transistor is provided in which multiple channels having different respective operational characteristics are employed. Multiple channels have threshold voltages that are independently adjustable. The independent adjustment of the threshold voltage includes providing at least one of different respective doping concentrations in the different channels, different respective gate dielectric thicknesses for the different gate dielectrics separating the channels, and different respective silicon channel thicknesses for the different channels.
摘要翻译：提供了一种多工作模式晶体管，其中采用具有不同相应操作特性的多个通道。多个通道具有可独立调节的阈值电压。阈值电压的独立调整包括在不同通道中提供不同的相应掺杂浓度中的至少一个，用于不同栅极电介质分离沟道的各自的栅介质厚度以及用于不同通道的不同的相应的硅沟道厚度。

10. 发明申请

US20070102776A1 Replacement metal gate transistors with reduced gate oxide leakage 有权
标题翻译：替代金属栅极晶体管，栅极氧化物泄漏减少
公开(公告)号：US20070102776A1
公开(公告)日：2007-05-10
申请号：US11269745
申请日：2005-11-09
申请人： James Pan , John Pellerin
发明人： James Pan , John Pellerin
IPC分类号： H01L29/78 , H01L21/4763
CPC分类号： H01L21/28008 , H01L21/28088 , H01L21/28238 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： Thin effective gate oxide thickness with reduced leakage for replacement metal gate transistors is achieved by forming a protective layer between the gate oxide layer and metal gate electrode, thereby reducing stress. Embodiments include forming a protective layer of amorphous carbon containing metal carbides decreasing in concentration from the metal gate electrode toward the gate oxide layer across the protective layer. Embodiments of methodology include removing the removable gate, depositing a layer of amorphous carbon on the gate oxide layer, forming the metal gate electrode and then heating at an elevated temperature to diffuse metal from the metal gate electrode into the amorphous carbon layer, thereby forming the metal carbides. Embodiments also include metal gate transistors with a gate oxide layer having a high dielectric constant and silicon concentrated at the interfaces with the metal gate electrode and substrate.
摘要翻译：通过在栅极氧化层和金属栅电极之间形成保护层来实现用于替换金属栅极晶体管的具有减小的泄漏的薄的有效栅极氧化物厚度，从而降低应力。实施例包括形成从金属栅电极朝向保护层的栅极氧化物层浓缩的含有金属碳化物的非晶碳保护层。方法的实施例包括去除可移除栅极，在栅极氧化物层上沉积无定形碳层，形成金属栅电极，然后在升高的温度下加热以使金属从金属栅电极扩散到无定形碳层中，从而形成金属碳化物。实施例还包括具有高介电常数的栅极氧化物层和在与金属栅电极和衬底的界面处集中的硅的金属栅极晶体管。

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