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21. 发明授权

US07573300B2 Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same 有权
标题翻译：集成电路中动态逻辑门控电路的电流控制机制及其调节方法
公开(公告)号：US07573300B2
公开(公告)日：2009-08-11
申请号：US11623112
申请日：2007-01-15
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译：一种集成电路，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。

22. 发明申请

US20090179670A1 PERFORMANCE INVERSION DETECTION CIRCUIT AND A DESIGN STRUCTURE FOR THE SAME 审中-公开
标题翻译：性能反相检测电路及其设计结构
公开(公告)号：US20090179670A1
公开(公告)日：2009-07-16
申请号：US12014430
申请日：2008-01-15
申请人： Albert M. Chu , John A. Fifield , Daryl M. Seitzer , Hongfei Wu
发明人： Albert M. Chu , John A. Fifield , Daryl M. Seitzer , Hongfei Wu
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F2200/447 , H03F2203/45586 , H03F2203/45618 , H03F2203/45622
摘要： A circuit containing a parallel connection of a first sub-circuit and a second sub-circuit is provided. The first sub-circuit comprises a serial connection of a first field effect transistor having a first threshold voltage and a first voltage dividing device. The second sub-circuit comprises a serial connection of a second field effect transistor having a second threshold voltage, which is different from the first threshold voltage, and a second voltage dividing device. The voltage between the first field effect transistor and the first voltage dividing device is compared with the voltage between the second field effect transistor and the second voltage dividing device so that a signal may be generated at a temperature at which the ratio of a performance parameter such as on-current between the first and second field effect transistors crosses over a predefined value. The signal may be advantageously employed to actively control circuit characteristics.
摘要翻译：提供了包含第一子电路和第二子电路的并联连接的电路。第一子电路包括具有第一阈值电压的第一场效应晶体管和第一分压装置的串联连接。第二子电路包括具有与第一阈值电压不同的第二阈值电压的第二场效应晶体管的串联连接和第二分压装置。将第一场效应晶体管和第一分压装置之间的电压与第二场效应晶体管和第二分压装置之间的电压进行比较，使得可以在这样的温度下产生信号，因为第一和第二场效应晶体管之间的导通电流跨越预定值。可以有利地使用该信号来主动地控制电路特性。

23. 发明申请

US20090033408A1 Voltage Pump Circuit with an Oxide Stress Control Mechanism for use in High-Voltage Applications in an Integrated Circuit 审中-公开
标题翻译：具有用于集成电路中的高压应用的氧化物应力控制机构的电压泵电路
公开(公告)号：US20090033408A1
公开(公告)日：2009-02-05
申请号：US12242233
申请日：2008-09-30
申请人： John A. Fifield
发明人： John A. Fifield
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , H03K17/063 , H03K17/08142 , H03K17/6872 , H03K2217/0027
摘要： A voltage pump circuit that has an oxide stress control mechanism is disclosed. In particular, the oxide stress control mechanism of the voltage pump circuit ensures a safe transistor gate-to-source voltage in high-voltage applications in an integrated circuit. In particular, the down level of the gate voltage of the output transistor may be conditionally limited. For example, an offset in the down level of the gate voltage is created by conditionally developing an offset voltage in the lower rail voltage of the gate driver. The offset voltage is created by directing a predetermined current through a resistance. The current is conditional such that the current is about zero when the power supply voltage is less than or equal to a predetermined level, and the current is greater than zero when the power supply voltage is greater than a predetermined level.
摘要翻译：公开了具有氧化物应力控制机构的电压泵电路。特别地，电压泵电路的氧化物应力控制机构确保在集成电路中的高压应用中的安全的晶体管栅极 - 源极电压。特别地，可以有条件地限制输出晶体管的栅极电压的下降电平。例如，栅极电压的下降电平的偏移是通过有选择地在栅极驱动器的较低轨道电压中产生偏移电压来产生的。通过引导预定电流通过电阻产生偏移电压。电流是有条件的，使得当电源电压小于或等于预定电平时电流约为零，当电源电压大于预定电平时，电流大于零。

24. 发明授权

US07471114B2 Design structure for a current control mechanism for power networks and dynamic logic keeper circuits 失效
标题翻译：用于电力网络和动态逻辑门控电路的电流控制机构的设计结构
公开(公告)号：US07471114B2
公开(公告)日：2008-12-30
申请号：US11851133
申请日：2007-09-06
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译：一种用于集成电路的设计结构，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。

25. 发明授权

US07442583B2 Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable 有权
标题翻译：使用电可编程保险丝隐藏架构，防止逆向工程，并使设备无法工作
公开(公告)号：US07442583B2
公开(公告)日：2008-10-28
申请号：US11016219
申请日：2004-12-17
申请人： Anthony R. Bonaccio , Karl R. Erickson , John A. Fifield , Chandrasekharan Kothandaraman , Phil C. Paone , William R. Tonti
发明人： Anthony R. Bonaccio , Karl R. Erickson , John A. Fifield , Chandrasekharan Kothandaraman , Phil C. Paone , William R. Tonti
IPC分类号： H01L21/82
CPC分类号： G06F12/1433 , G06F21/6245
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
摘要翻译：提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。可以基于存储在诸如电可编程融合（eFUSES）的非易失性存储元件中的值来提供操作和/或访问。

26. 发明申请

US20080155151A1 Programmable Locking Mechanism For Secure Applications In An Integrated Circuit 审中-公开
标题翻译：可编程锁定机制，用于集成电路中的安全应用
公开(公告)号：US20080155151A1
公开(公告)日：2008-06-26
申请号：US11615137
申请日：2006-12-22
申请人： John A. Fifield , Steven F. Oakland , Michael R. Ouellette
发明人： John A. Fifield , Steven F. Oakland , Michael R. Ouellette
IPC分类号： G06F21/00
CPC分类号： G06K19/073 , G06K19/07309
摘要： A programmable locking mechanism for use in an integrated circuit is disclosed. In particular, the programmable locking mechanism may include an access code storage circuit for storing a security access code and a code input register whose outputs feed a comparator circuit that generates a locking signal. The state of the locking signal depends on whether the contents of the access code storage circuit and the code input register match. Additionally, a blocking circuit is provided that interrupts a programming input to the access code storage circuit and, thus, allows or denies access via the programming input to the access code storage circuit depending on the state of the locking signal. Additionally, the locking signal is distributed to sensitive logic circuits within the integrated circuit for preventing and/or allowing (depending on state) access thereto.
摘要翻译：公开了一种用于集成电路的可编程锁定机构。特别地，可编程锁定机构可以包括用于存储安全访问代码的访问代码存储电路和其输出馈送产生锁定信号的比较器电路的代码输入寄存器。锁定信号的状态取决于访问代码存储电路和代码输入寄存器的内容是否匹配。此外，提供一种阻塞电路，其中断对访问代码存储电路的编程输入，并且因此根据锁定信号的状态允许或拒绝通过对访问代码存储电路的编程输入的访问。此外，锁定信号被分配到集成电路内的敏感逻辑电路，用于防止和/或允许（取决于状态）对其的访问。

27. 发明申请

US20080129271A1 Low Voltage Reference System 审中-公开
标题翻译：低电压参考系统
公开(公告)号：US20080129271A1
公开(公告)日：2008-06-05
申请号：US11566503
申请日：2006-12-04
申请人： John A. Fifield
发明人： John A. Fifield
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： A voltage reference system that generates a stable reference voltage at varying supply voltages. The system receiving an input voltage and having a voltage pumping circuit that provides a power supply, regulated by a regulator circuit, to a bandgap reference circuit. The bandgap reference circuit generating a first output as a stable voltage value and delivering the first output to a clamping circuit which outputs the lesser of the stable voltage value and a fraction of the input voltage.
摘要翻译：电压参考系统，可在变化的电源电压下产生稳定的参考电压。该系统接收一输入电压，并具有电压泵电路，提供了一个电源，由一个调节器电路调节，以带隙基准电路。带隙基准电路产生第一输出作为一个稳定的电压值和所述第一输出输送到钳位电路，其输出稳定电压值和所述输入电压的一小部分中的较小者。

28. 发明授权

US07336102B2 Error correcting logic system 有权
公开(公告)号：US07336102B2
公开(公告)日：2008-02-26
申请号：US10710641
申请日：2004-07-27
申请人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
发明人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
IPC分类号： H03K19/20 , H03K19/094 , H03K19/003
CPC分类号： H03K19/007
摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.

29. 发明授权

US07307457B2 Apparatus for implementing dynamic data path with interlocked keeper and restore devices 有权
标题翻译：用于实现动态数据路径的装置，具有联锁保持器和恢复装置
公开(公告)号：US07307457B2
公开(公告)日：2007-12-11
申请号：US11278169
申请日：2006-03-31
申请人： George M. Braceras , John A. Fifield , Harold Pilo
发明人： George M. Braceras , John A. Fifield , Harold Pilo
IPC分类号： H03K19/096 , H03K19/094 , G11C7/00
CPC分类号： G11C7/1051 , G11C7/1057
摘要： A keeper device for dynamic logic includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during an evaluation thereof, and a second keeper path selectively coupled to the dynamic data path. The second keeper path is configured to maintain the dynamic data path at a nominal precharge level prior to an evaluation thereof, wherein the second keeper path is decoupled from the dynamic data path during the evaluation.
摘要翻译：用于动态逻辑的保持器装置包括静态耦合到动态数据路径的第一保持器路径，第一保持器路径被配置为在其评估期间防止动态数据路径的假放电，以及选择性地耦合到动态数据路径的第二保持器路径。第二保持器路径被配置为在其评估之前将动态数据路径保持在标称预充电水平，其中在评估期间第二保持器路径与动态数据路径解耦。

30. 发明授权

US07262987B2 SRAM cell using tunnel current loading devices 失效
标题翻译： SRAM单元采用隧道电流加载装置
公开(公告)号：US07262987B2
公开(公告)日：2007-08-28
申请号：US10906056
申请日：2005-02-01
申请人： Wagdi W. Abadeer , John A. Fifield , Harold Pilo
发明人： Wagdi W. Abadeer , John A. Fifield , Harold Pilo
IPC分类号： G11C11/00
CPC分类号： H01L27/1104 , G11C11/412
摘要： An SRAM cell with gate tunneling load devices. The SRAM cell uses PFET wordline transistors and NFET cross-coupled transistors. The PFET wordline transistors are fully conductive during read operations, thus a full voltage level is passed through the PFET to the high node of the cell from the bitline. Tunnel current load devices maintain the high node of the cell at full voltage level during standby state.
摘要翻译：具有栅极隧道负载装置的SRAM单元。 SRAM单元使用PFET字线晶体管和NFET交叉耦合晶体管。 PFET字线晶体管在读取操作期间是完全导电的，因此，整个电压电平从位线通过PFET到电池的高节点。隧道电流负载设备在待机状态下将电池的高节点保持在全电压电平。

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