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1. 发明授权

US07573300B2 Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same 有权
标题翻译：集成电路中动态逻辑门控电路的电流控制机制及其调节方法
公开(公告)号：US07573300B2
公开(公告)日：2009-08-11
申请号：US11623112
申请日：2007-01-15
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译：一种集成电路，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。

2. 发明授权

US07471114B2 Design structure for a current control mechanism for power networks and dynamic logic keeper circuits 失效
标题翻译：用于电力网络和动态逻辑门控电路的电流控制机构的设计结构
公开(公告)号：US07471114B2
公开(公告)日：2008-12-30
申请号：US11851133
申请日：2007-09-06
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译：一种用于集成电路的设计结构，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。

3. 发明授权

US07262987B2 SRAM cell using tunnel current loading devices 失效
标题翻译： SRAM单元采用隧道电流加载装置
公开(公告)号：US07262987B2
公开(公告)日：2007-08-28
申请号：US10906056
申请日：2005-02-01
申请人： Wagdi W. Abadeer , John A. Fifield , Harold Pilo
发明人： Wagdi W. Abadeer , John A. Fifield , Harold Pilo
IPC分类号： G11C11/00
CPC分类号： H01L27/1104 , G11C11/412
摘要： An SRAM cell with gate tunneling load devices. The SRAM cell uses PFET wordline transistors and NFET cross-coupled transistors. The PFET wordline transistors are fully conductive during read operations, thus a full voltage level is passed through the PFET to the high node of the cell from the bitline. Tunnel current load devices maintain the high node of the cell at full voltage level during standby state.
摘要翻译：具有栅极隧道负载装置的SRAM单元。 SRAM单元使用PFET字线晶体管和NFET交叉耦合晶体管。 PFET字线晶体管在读取操作期间是完全导电的，因此，整个电压电平从位线通过PFET到电池的高节点。隧道电流负载设备在待机状态下将电池的高节点保持在全电压电平。

4. 发明授权

US07904658B2 Structure for power-efficient cache memory 有权
标题翻译：高效能高效缓存的结构
公开(公告)号：US07904658B2
公开(公告)日：2011-03-08
申请号：US11851128
申请日：2007-09-06
申请人： Wagdi W. Abadeer , George M. Braceras , John A. Fifield , Harold Pilo
发明人： Wagdi W. Abadeer , George M. Braceras , John A. Fifield , Harold Pilo
IPC分类号： G06F12/00 , G06F1/00 , G06F1/26 , G11C5/14
CPC分类号： G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13
摘要： A design structure for a cache memory system (200) having a cache memory (204) partitioned into a number of banks, or “ways” (204A, 204B). The memory system includes a power controller (244) that selectively powers up and down the ways depending upon which way contains the data being sought by each incoming address (232) coming into the memory system.
摘要翻译：具有高速缓冲存储器（204）的高速缓冲存储器系统（200）的设计结构，所述高速缓冲存储器系统（200）被划分成多个存储体，或“路径”（204A，204B）。存储器系统包括功率控制器（244），功率控制器（244）根据包含正在进入存储器系统的每个输入地址（232）寻找的数据的方式选择性地向上和向下加电。

5. 发明申请

US20080169839A1 STRUCTURE FOR A CURRENT CONTROL MECHANISM FOR DYNAMIC LOGIC KEEPER CIRCUITS 失效
标题翻译：用于动态逻辑保护电路的电流控制机构的结构
公开(公告)号：US20080169839A1
公开(公告)日：2008-07-17
申请号：US11851133
申请日：2007-09-06
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/0175
CPC分类号： H03K19/0963
摘要： A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译：一种用于集成电路的设计结构，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。

6. 发明申请

US20080169837A1 Current Control Mechanism For Dynamic Logic Keeper Circuits In An Integrated Circuit And Method Of Regulating Same 有权
标题翻译：一种集成电路中动态逻辑控制器电路的电流控制机制及其调节方法
公开(公告)号：US20080169837A1
公开(公告)日：2008-07-17
申请号：US11623112
申请日：2007-01-15
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/0175
CPC分类号： H03K19/0963
摘要： An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译：一种集成电路，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。

7. 发明授权

US07548080B2 Method and apparatus for burn-in optimization 失效
标题翻译：老化优化的方法和装置
公开(公告)号：US07548080B2
公开(公告)日：2009-06-16
申请号：US11538833
申请日：2006-10-05
申请人： Wagdi W. Abadeer , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , Harold Pilo , Daryl M. Seitzer
IPC分类号： G01R31/02
CPC分类号： G01R31/287 , G01R31/2874
摘要： The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.
摘要翻译：本发明提供一种用于优化集成电路的老化的方法和装置。该方法的一个实施例包括：执行集成电路的老化过程的第一部分; 在老化过程的第一部分期间监测集成电路的功耗; 增加老化温度，直到集成电路的功耗达到预定的最大功耗; 以及在增加的老化温度下执行集成电路的老化过程的后续部分。

8. 发明授权

US07141998B1 Method and apparatus for burn-in optimization 失效
公开(公告)号：US07141998B1
公开(公告)日：2006-11-28
申请号：US10908620
申请日：2005-05-19
申请人： Wagdi W. Abadeer , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , Harold Pilo , Daryl M. Seitzer
IPC分类号： G01R31/02
CPC分类号： G01R31/287 , G01R31/2874
摘要： The present invention provides a method and apparatus for optimizing the burn-in of integrated circuits. One embodiment of the method comprises: performing a first portion of the burn-in process of the integrated circuit; monitoring a power dissipation of the integrated circuit during the first portion of the burn-in process; increasing a burn-in temperature until the power dissipation of the integrated circuit reaches a predetermined maximum power dissipation; and performing a subsequent portion of the burn-in process of the integrated circuit at the increased burn-in temperature.

9. 发明授权

US07894291B2 Circuit and method for controlling a standby voltage level of a memory 有权
标题翻译：用于控制存储器的待机电压电平的电路和方法
公开(公告)号：US07894291B2
公开(公告)日：2011-02-22
申请号：US11162847
申请日：2005-09-26
申请人： George M. Braceras , John A. Fifield , Harold Pilo
发明人： George M. Braceras , John A. Fifield , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147
摘要： A memory is provided which can be operated at an active rate of power consumption in an active operational mode and at a predetermined reduced rate of power consumption in a standby operational mode. The memory includes a current generating circuit which is operable to supply a predetermined magnitude of current to a sample power supply input terminal of a sample memory cell representative of memory cells of the memory, the predetermined magnitude of current corresponding to the predetermined reduced rate of power consumption. A voltage follower circuit is operable to output a standby voltage level equal to a voltage level at the sample power supply input terminal when the predetermined magnitude of current is supplied thereto. A memory cell array of the memory is operable to store data. In the standby operational mode, a switching circuit is operable to supply power at the standby voltage level to a power supply input terminal of the memory cell array. This permits data to remain stored in the memory during the standby mode. During an active operational mode, the switching circuit is operable to connect the power supply input terminal at the power supply to supply power at the active voltage level to the memory cell array. During the active operational mode, data can be stored into the memory cell array and retrieved from the memory cell array.
摘要翻译：提供一种存储器，其可以在主动操作模式中以在备用操作模式中以预定的降低的功率消耗速率以有效的功率消耗速率操作。存储器包括电流产生电路，其可操作以向代表存储器的存储器单元的采样存储单元的采样电源输入端提供预定大小的电流，与预定的降低的功率比相对应的预定电流值消费。电压跟随器电路可操作以当提供预定电流大小时输出等于采样电源输入端的电压电平的备用电压电平。存储器的存储单元阵列可操作以存储数据。在待机操作模式中，切换电路可操作以将备用电压电平的电力提供给存储单元阵列的电源输入端。这在待机模式期间允许数据保存在存储器中。在有效操作模式期间，开关电路可操作地连接电源处的电源输入端，以将有源电压电平的电力提供给存储单元阵列。在主动操作模式期间，可将数据存储到存储单元阵列中并从存储单元阵列检索。

10. 发明授权

US07495950B2 Voltage controlled static random access memory 失效
标题翻译：电压控制静态随机存取存储器
公开(公告)号：US07495950B2
公开(公告)日：2009-02-24
申请号：US11926689
申请日：2007-10-29
申请人： John A. Fifield , Harold Pilo
发明人： John A. Fifield , Harold Pilo
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C11/413
摘要： A static random access memory (SRAM) comprising a plurality of SRAM cells, a plurality of wordlines (WL0-WLN) and a voltage regulator for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood of occurrence of read-disturbances and other memory instabilities. In one embodiment, the wordline voltage signal is determined as a function of the metastability voltage (VMETA) of the SRAM cells and an adjusted most positive down level voltage (VAMPDL) that is a function of a predetermined voltage margin (VM) and a most positive down level voltage (VMPDL) that corresponds to the read-disturb voltage of the SRAM cells.
摘要翻译：包括多个SRAM单元，多个字线（WL0-WLN）和用于用字线电压信号（VWLP）驱动字线的电压调节器的静态随机存取存储器（SRAM）。确定字线电压信号以便减少发生读取干扰和其它存储器不稳定性的可能性。在一个实施例中，字线电压信号被确定为SRAM单元的亚稳态电压（VMETA）的函数，以及作为预定电压余量（VM）的函数的经调整的最正向下电平电压（VAMPDL）对应于SRAM单元的读取 - 干扰电压的正向下电平电压（VMPDL）。

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