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1. 发明申请

US20080169839A1 STRUCTURE FOR A CURRENT CONTROL MECHANISM FOR DYNAMIC LOGIC KEEPER CIRCUITS 失效
标题翻译：用于动态逻辑保护电路的电流控制机构的结构
公开(公告)号：US20080169839A1
公开(公告)日：2008-07-17
申请号：US11851133
申请日：2007-09-06
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/0175
CPC分类号： H03K19/0963
摘要： A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译：一种用于集成电路的设计结构，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。

2. 发明申请

US20080169837A1 Current Control Mechanism For Dynamic Logic Keeper Circuits In An Integrated Circuit And Method Of Regulating Same 有权
标题翻译：一种集成电路中动态逻辑控制器电路的电流控制机制及其调节方法
公开(公告)号：US20080169837A1
公开(公告)日：2008-07-17
申请号：US11623112
申请日：2007-01-15
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/0175
CPC分类号： H03K19/0963
摘要： An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译：一种集成电路，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。

3. 发明授权

US07573300B2 Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating same 有权
标题翻译：集成电路中动态逻辑门控电路的电流控制机制及其调节方法
公开(公告)号：US07573300B2
公开(公告)日：2009-08-11
申请号：US11623112
申请日：2007-01-15
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译：一种集成电路，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。

4. 发明授权

US07471114B2 Design structure for a current control mechanism for power networks and dynamic logic keeper circuits 失效
标题翻译：用于电力网络和动态逻辑门控电路的电流控制机构的设计结构
公开(公告)号：US07471114B2
公开(公告)日：2008-12-30
申请号：US11851133
申请日：2007-09-06
申请人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
发明人： Wagdi W. Abadeer , George M. Braceras , Albert M. Chu , John A. Fifield , Harold Pilo , Daryl M. Seitzer
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
摘要翻译：一种用于集成电路的设计结构，其包括栅极控制电压发生器，其将电流控制栅极电压提供给各自具有保持电路的相应多个动态逻辑电路的多个电流控制装置。栅极控制电压发生器通过电流控制栅极电压提供流过保持器电路的保持器电流量的全局控制，以便增强动态逻辑电路的性能。

5. 发明授权

US07904658B2 Structure for power-efficient cache memory 有权
标题翻译：高效能高效缓存的结构
公开(公告)号：US07904658B2
公开(公告)日：2011-03-08
申请号：US11851128
申请日：2007-09-06
申请人： Wagdi W. Abadeer , George M. Braceras , John A. Fifield , Harold Pilo
发明人： Wagdi W. Abadeer , George M. Braceras , John A. Fifield , Harold Pilo
IPC分类号： G06F12/00 , G06F1/00 , G06F1/26 , G11C5/14
CPC分类号： G06F12/0864 , G06F2212/1028 , G06F2212/601 , Y02D10/13
摘要： A design structure for a cache memory system (200) having a cache memory (204) partitioned into a number of banks, or “ways” (204A, 204B). The memory system includes a power controller (244) that selectively powers up and down the ways depending upon which way contains the data being sought by each incoming address (232) coming into the memory system.
摘要翻译：具有高速缓冲存储器（204）的高速缓冲存储器系统（200）的设计结构，所述高速缓冲存储器系统（200）被划分成多个存储体，或“路径”（204A，204B）。存储器系统包括功率控制器（244），功率控制器（244）根据包含正在进入存储器系统的每个输入地址（232）寻找的数据的方式选择性地向上和向下加电。

6. 发明授权

US08839054B2 Read only memory (ROM) with redundancy 有权
标题翻译：只读存储器（ROM）冗余
公开(公告)号：US08839054B2
公开(公告)日：2014-09-16
申请号：US13445187
申请日：2012-04-12
申请人： George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
发明人： George M. Braceras , Albert M. Chu , Kevin W. Gorman , Michael R. Ouellette , Ronald A. Piro , Daryl M. Seitzer , Rohit Shetty , Thomas W. Wyckoff
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G06F11/0793 , G11C17/00 , G11C29/4401 , G11C29/822
摘要： A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.
摘要翻译：提供了具有冗余性和使用方法的只读存储器（ROM）。具有冗余的ROM包括耦合到具有一个或多个冗余修复的修复电路的可编程阵列。一个或多个冗余修复包括字地址匹配逻辑块，数据I / O地址和三态缓冲器。字地址匹配逻辑块作为控制输入提供给三态缓冲器，并且将数据I / O地址作为输入提供给三态缓冲器。提供每个冗余修复的三态缓冲器的输出作为一个或多个逻辑器件的第一输入。提供ROM位单元阵列的一个或多个数据输出作为一个或多个逻辑器件中的相应一个的第二输入。

7. 发明授权

US07894291B2 Circuit and method for controlling a standby voltage level of a memory 有权
标题翻译：用于控制存储器的待机电压电平的电路和方法
公开(公告)号：US07894291B2
公开(公告)日：2011-02-22
申请号：US11162847
申请日：2005-09-26
申请人： George M. Braceras , John A. Fifield , Harold Pilo
发明人： George M. Braceras , John A. Fifield , Harold Pilo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147
摘要： A memory is provided which can be operated at an active rate of power consumption in an active operational mode and at a predetermined reduced rate of power consumption in a standby operational mode. The memory includes a current generating circuit which is operable to supply a predetermined magnitude of current to a sample power supply input terminal of a sample memory cell representative of memory cells of the memory, the predetermined magnitude of current corresponding to the predetermined reduced rate of power consumption. A voltage follower circuit is operable to output a standby voltage level equal to a voltage level at the sample power supply input terminal when the predetermined magnitude of current is supplied thereto. A memory cell array of the memory is operable to store data. In the standby operational mode, a switching circuit is operable to supply power at the standby voltage level to a power supply input terminal of the memory cell array. This permits data to remain stored in the memory during the standby mode. During an active operational mode, the switching circuit is operable to connect the power supply input terminal at the power supply to supply power at the active voltage level to the memory cell array. During the active operational mode, data can be stored into the memory cell array and retrieved from the memory cell array.
摘要翻译：提供一种存储器，其可以在主动操作模式中以在备用操作模式中以预定的降低的功率消耗速率以有效的功率消耗速率操作。存储器包括电流产生电路，其可操作以向代表存储器的存储器单元的采样存储单元的采样电源输入端提供预定大小的电流，与预定的降低的功率比相对应的预定电流值消费。电压跟随器电路可操作以当提供预定电流大小时输出等于采样电源输入端的电压电平的备用电压电平。存储器的存储单元阵列可操作以存储数据。在待机操作模式中，切换电路可操作以将备用电压电平的电力提供给存储单元阵列的电源输入端。这在待机模式期间允许数据保存在存储器中。在有效操作模式期间，开关电路可操作地连接电源处的电源输入端，以将有源电压电平的电力提供给存储单元阵列。在主动操作模式期间，可将数据存储到存储单元阵列中并从存储单元阵列检索。

8. 发明授权

US07307457B2 Apparatus for implementing dynamic data path with interlocked keeper and restore devices 有权
标题翻译：用于实现动态数据路径的装置，具有联锁保持器和恢复装置
公开(公告)号：US07307457B2
公开(公告)日：2007-12-11
申请号：US11278169
申请日：2006-03-31
申请人： George M. Braceras , John A. Fifield , Harold Pilo
发明人： George M. Braceras , John A. Fifield , Harold Pilo
IPC分类号： H03K19/096 , H03K19/094 , G11C7/00
CPC分类号： G11C7/1051 , G11C7/1057
摘要： A keeper device for dynamic logic includes a first keeper path statically coupled to a dynamic data path, the first keeper path configured to prevent false discharge of the dynamic data path during an evaluation thereof, and a second keeper path selectively coupled to the dynamic data path. The second keeper path is configured to maintain the dynamic data path at a nominal precharge level prior to an evaluation thereof, wherein the second keeper path is decoupled from the dynamic data path during the evaluation.
摘要翻译：用于动态逻辑的保持器装置包括静态耦合到动态数据路径的第一保持器路径，第一保持器路径被配置为在其评估期间防止动态数据路径的假放电，以及选择性地耦合到动态数据路径的第二保持器路径。第二保持器路径被配置为在其评估之前将动态数据路径保持在标称预充电水平，其中在评估期间第二保持器路径与动态数据路径解耦。

9. 发明申请

US20120075919A1 Methods and Systems for Adjusting Wordline Up-Level Voltage to Improve Production Yield Relative to SRAM-Cell Stability 有权
标题翻译：用于调整字面上升电压的方法和系统，以提高相对于SRAM单元稳定性的产量
公开(公告)号：US20120075919A1
公开(公告)日：2012-03-29
申请号：US12892191
申请日：2010-09-28
申请人： Igor Arsovski , George M. Braceras , Kevin W. Gorman , Robert M. Houle , Harold Pilo
发明人： Igor Arsovski , George M. Braceras , Kevin W. Gorman , Robert M. Houle , Harold Pilo
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C8/08
摘要： Methods of setting wordline up-level voltage in as-fabricated SRAM. In one example, the method includes determining the relative speed, or strength, of 1) the combination of the pass-gate and pull-down devices and 2) the pull-up devices in the bitcells of the SRAM. These relative strengths are then used to adjust the wordline up-level voltage, if needed, to decrease the likelihood of the SRAM experiencing a stability failure. Corresponding systems are provided for determining the relative strengths of the devices of interest, for determining the amount of up-level voltage adjustment needed, and for selecting and setting the up-level voltage.
摘要翻译：在制造的SRAM中设置字线上电压的方法。在一个示例中，该方法包括确定1）通过栅极和下拉器件的组合的相对速度或强度，以及2）SRAM的位单元中的上拉器件。然后，如果需要，这些相对强度可用于调整字线上电压，以降低SRAM遇到稳定性故障的可能性。提供相应的系统用于确定感兴趣的装置的相对强度，用于确定所需的上限电压调整量以及用于选择和设定上限电压。

10. 发明授权

US06967861B2 Method and apparatus for improving cycle time in a quad data rate SRAM device 有权
标题翻译：用于改善四倍数据速率SRAM器件中的周期时间的方法和装置
公开(公告)号：US06967861B2
公开(公告)日：2005-11-22
申请号：US10708379
申请日：2004-02-27
申请人： George M. Braceras , Harold Pilo
发明人： George M. Braceras , Harold Pilo
IPC分类号： G11C8/00 , G11C11/00 , G11C11/413
CPC分类号： G11C11/413
摘要： A method for implementing a self-timed, read to write operation in a memory storage device. In an exemplary embodiment, the method includes capturing a read address during a first half of a current clock cycle, and commencing a read operation so as to read data corresponding to the captured read address onto a pair of bit lines. A write operation is commenced for the current clock cycle so as to cause write data to appear on the pair of bit lines as soon as the read data from the captured read address is amplified by a sense amplifier, wherein the write operation uses a previous write address captured during a preceding clock cycle. A current write address is captured during a second half of the current clock cycle, said current write address used for a write operation implemented during a subsequent clock cycle, wherein the write operation for the current clock cycle is timed independent of the current write address captured during said second half of the current clock cycle.
摘要翻译：一种用于在存储器存储设备中实现自定时的读写操作的方法。在一个示例性实施例中，该方法包括在当前时钟周期的前半部分期间捕获读取地址，并开始读取操作，以便将对应于所捕获的读取地址的数据读取到一对位线上。一旦当前时钟周期开始写入操作，以便一旦来自捕获的读取地址的读取数据被读出放大器放大，就会使写入数据出现在该对位线上，其中写入操作使用先前的写入在前一个时钟周期捕获的地址。在当前时钟周期的后半段期间捕获当前写入地址，所述当前写入地址用于在随后的时钟周期期间实现的写入操作，其中当前时钟周期的写入操作被独立于捕获的当前写入地址在当前时钟周期的后半段。

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