专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US5973397A Semiconductor device and fabrication method which advantageously combine wire bonding and tab techniques to increase integrated circuit I/O pad density 失效
标题翻译：有利地组合引线键合和制图技术以增加集成电路I / O焊盘密度的半导体器件和制造方法
公开(公告)号：US5973397A
公开(公告)日：1999-10-26
申请号：US955929
申请日：1997-10-22
申请人： Qwai H. Low , Chok J. Chia , Seng-Sooi Lim
发明人： Qwai H. Low , Chok J. Chia , Seng-Sooi Lim
IPC分类号： H01L23/498 , H01L23/04
CPC分类号： H01L24/91 , H01L23/49811 , H01L23/49833 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L24/45 , H01L24/48 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/14
摘要： A semiconductor device and fabrication method are presented which advantageously combine TAB and wire bonding techniques to increase integrated circuit I/O pad density. The semiconductor device includes an integrated circuit, a substrate, and a carrier film (i.e., a TAB tape). The integrated circuit has a set of input/output (I/O) pads arranged upon an upper surface. The substrate has a die cavity within an upper surface and a set of bond traces arranged about the die cavity. An underside surface of the integrated circuit is attached to the substrate within the die cavity. The carrier film is positioned over the upper surface of the substrate such that the upper surface of the integrated circuit is exposed through a die aperture and portions of the members of the set of bond traces are exposed through corresponding members of a set of bond trace apertures. Each conductor has a first end connected to a member of the set of bond traces and an opposed second end connected to a corresponding member of a portion of the set of I/O pads. Each of the remaining members of the I/O pads are connected to respective bond traces adjacent to the die cavity by bonding wires. By combining TAB and wire bonding techniques, the number of I/O pads per unit of upper surface area of the integrated circuit may be increased.
摘要翻译：提出了一种半导体器件和制造方法，其有利地组合TAB和引线键合技术以增加集成电路I / O焊盘密度。半导体器件包括集成电路，衬底和载体膜（即，TAB带）。集成电路具有布置在上表面上的一组输入/输出（I / O）焊盘。衬底在上表面内具有模腔，并且在模腔周围设置一组粘合迹线。集成电路的下表面附着在模腔内的基板上。载体膜位于衬底的上表面上，使得集成电路的上表面通过裸片孔露出，并且该组接合迹线的部件的一部分通过一组接合轨迹孔的相应构件暴露。每个导体具有连接到该组接合迹线的构件的第一端和连接到该组I / O焊盘的一部分的对应构件的相对的第二端。 I / O焊盘的每个剩余部件通过接合线连接到与模腔相邻的各个焊接迹线。通过组合TAB和引线键合技术，可以增加集成电路的每单位上表面积的I / O焊盘的数量。

22. 发明授权

US5841191A Ball grid array package employing raised metal contact rings 失效
标题翻译：使用凸起金属接触环的球栅阵列封装
公开(公告)号：US5841191A
公开(公告)日：1998-11-24
申请号：US837530
申请日：1997-04-21
申请人： Chok J. Chia , Qwai H. Low , Maniam Alagaratnam
发明人： Chok J. Chia , Qwai H. Low , Maniam Alagaratnam
IPC分类号： H01L23/12 , H01L21/60 , H01L23/50 , H01L23/52 , H01L23/48
CPC分类号： H01L24/49 , H01L23/50 , H01L2224/45147 , H01L2224/48091 , H01L2224/49109 , H01L2224/4911 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01029 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19107
摘要： A ball grid array package in which one or more conductive rings are positioned on a surface of the package substrate along with solder bond contacts on the surface of the substrate to facilitate the interconnection of wire bonds to an integrated circuit chip on the surface of the substrate. The use of rings allows for better distribution of power to the chip since a plurality of wires can be connected between the chip and the conductive rings for power distribution. The rings create a different shelf for the power and ground bonds on the substrate, and by providing a vertical separation between the surfaces of the rings and bonding pads on the surface of the substrate more bonds in the package can be accommodated.
摘要翻译：一种球栅阵列封装，其中一个或多个导电环与衬底表面上的焊料接合位置一起定位在封装衬底的表面上，以便于引线键合到衬底表面上的集成电路芯片。由于可以在芯片和用于配电的导电环之间连接多根导线，所以使用环允许更好地将功率分配到芯片。这些环形成不同的搁板，用于基板上的电源和接地键，并且通过在环的表面和衬底表面上的接合焊盘之间提供垂直间隔，可以容纳封装中更多的接合。

23. 发明授权

US5814881A Stacked integrated chip package and method of making same 失效
标题翻译：堆叠集成芯片封装及其制作方法
公开(公告)号：US5814881A
公开(公告)日：1998-09-29
申请号：US770872
申请日：1996-12-20
申请人： Maniam Alagaratnam , Qwai H. Low , Chok J. Chia
发明人： Maniam Alagaratnam , Qwai H. Low , Chok J. Chia
IPC分类号： H01L21/98 , H01L23/495 , H01L23/02
CPC分类号： H01L24/32 , H01L23/4951 , H01L23/49575 , H01L25/50 , H01L2224/32014 , H01L2224/32145 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/73215 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181
摘要： A single leadframe package having stacked integrated chips mounted therein provides multiple electrical functions. The leadframe package construction includes a leadframe die having a substantially smaller outer peripheral dimension than a first integrated circuit chip mounted face down thereon for supporting from below the first integrated chip without obstructing its bond pads. A second integrated circuit is supported from below in a backside to backside configuration by the first integrated circuit without obstructing the bond pads of the second integrated circuit. A plurality of substantially short conductive wires interconnect electrically the first and second integrated circuit chips with selective ones of a plurality of leadframe conductors. An encapsulating material molds the construction into the single leadframe package.
摘要翻译：具有安装在其中的堆叠集成芯片的单个引线框封装提供多个电功能。引线框封装结构包括引线框模具，该引线框模具具有比面向下安装的第一集成电路芯片更小的外周尺寸，用于从第一集成芯片的下方支撑而不阻碍其键合焊盘。第二集成电路在下面被第一集成电路的背面配置支持，而不会阻碍第二集成电路的接合焊盘。多个基本上短的导电线将第一和第二集成电路芯片与多个引线框架导体中的选择性导体互连。封装材料将结构模制成单引线框封装。

24. 发明授权

US5353193A High power dissipating packages with matched heatspreader heatsink assemblies 失效
标题翻译：具有匹配散热器散热器组件的大功率消散封装
公开(公告)号：US5353193A
公开(公告)日：1994-10-04
申请号：US023981
申请日：1993-02-26
申请人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
发明人： Chok J. Chia , Manian Alagaratnam , Qwai H. Low , Seng-Sooi Lim
IPC分类号： F02F7/00 , H01L23/367 , H01L23/40 , H05K7/20
CPC分类号： H01L23/40 , F02F7/00 , H01L23/3675 , H01L2924/0002 , Y10T29/4913
摘要： A removable heatsink assembly comprised of a heatsink unit and a heatspreader is provided. The heatsink unit has at least one fin and a coupling collar for radiating heat away from a packaged electronic device. The heatspreader includes a platform attached to an inner collar in thermal contact with the packaged electronic device. The platform has one or more tabs suitable for mating with one or more flanges located on the coupling collar of the heatsink unit. Coupling grooves within the flanges engage the platform of the heatspreader when the flanges are mated with the heatspreader tabs and the heatsink is turned. The heatsink can therefore be quickly and conveniently attached to or removed from the heatspreader. The present invention thus permits a wide variety of different heatsinks to be interchangeably used with a single heatspreader attached to an electronic device package.
摘要翻译：提供了由散热器单元和散热器组成的可拆卸的散热器组件。散热器单元具有至少一个翅片和用于从封装的电子设备辐射热量的联接套环。散热器包括附接到与封装的电子设备热接触的内部套环的平台。该平台具有一个或多个适合于与位于散热器单元的联接环上的一个或多个凸缘相配合的凸片。当凸缘与散热片接头配合并且散热片转动时，凸缘内的耦合凹槽接合散热器的平台。因此，散热器可以快速方便地附接到散热器或从散热器移除。因此，本发明允许各种不同的散热器与附接到电子设备封装的单个散热器可互换地使用。

25. 发明授权

US06781150B2 Test structure for detecting bonding-induced cracks 有权
标题翻译：用于检测接合引起的裂纹的测试结构
公开(公告)号：US06781150B2
公开(公告)日：2004-08-24
申请号：US10229601
申请日：2002-08-28
申请人： Qwai H. Low , Ramaswamy Ranganathan , Anwar Ali , Tauman T. Lau
发明人： Qwai H. Low , Ramaswamy Ranganathan , Anwar Ali , Tauman T. Lau
IPC分类号： H01L2358
CPC分类号： H01L24/05 , H01L22/34 , H01L24/48 , H01L2224/04042 , H01L2224/05001 , H01L2224/05073 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer. The sensing layer immediately underlies the at least one of the non electrically conductive layers in the test structure that has no vias formed therein. Thus, a crack in the at least one of the non electrically conductive layers in the test structure that has no vias formed therein is detectable as a leakage current between the bonding pad of the test structure and a top most electrically conductive layer of the control structure.
摘要翻译：具有裂纹检测结构的集成电路。形成具有垂直取向的交错导电层和非导电层的控制结构。导电通孔垂直地设置在所有非导电层上，通孔将所有的导电层彼此电连接。形成具有用于探测和结合的接合焊盘的测试结构，其中底层交错的导电层和以垂直取向设置的非导电层。非导电层中的至少一个在其中没有形成通孔，模拟集成电路的其它接合焊盘下的有源电路。控制结构的交错导电层中的至少一个从控制结构内延伸到作为感测层的测试结构内。感测层紧邻在其中形成有通孔的测试结构中的非导电层中的至少一个之上。因此，测试结构中没有形成通孔的非导电层中的至少一个的裂纹可以被检测为在测试结构的焊盘与控制结构的最高导电层之间的漏电流。

26. 发明授权

US06798035B1 Bonding pad for low k dielectric 有权
标题翻译：低k电介质接合垫
公开(公告)号：US06798035B1
公开(公告)日：2004-09-28
申请号：US10600255
申请日：2003-06-20
申请人： Qwai H. Low , Ramaswamy Ranganathan , Edwin M. Fulcher
发明人： Qwai H. Low , Ramaswamy Ranganathan , Edwin M. Fulcher
IPC分类号： H01L3100
CPC分类号： H01L24/05 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： A bonding pad structure having an electrically conductive capping layer. An electrically conductive first supporting layer is disposed immediately under the electrically conductive capping layer, without any intervening layers between the electrically conductive capping layer and the electrically conductive first supporting layer. The electrically conductive first supporting layer is configured as one of a sheet having no voids and a sheet having slotted voids in a first direction. An electrically conductive second supporting layer is disposed under the electrically conductive first supporting layer. The electrically conductive second supporting layer is configured as one of a sheet having slotted voids in the first direction, a sheet having slotted voids in a second direction, and a sheet having checkerboard voids.
摘要翻译：一种具有导电覆盖层的焊盘结构。导电的第一支撑层设置在导电覆盖层的正下方，在导电覆盖层和导电的第一支撑层之间没有任何中间层。导电性第一支撑层被构造为没有空隙的片材之一和在第一方向上具有开槽空隙的片材。导电的第二支撑层设置在导电的第一支撑层之下。导电性第二支撑层被构造为在第一方向上具有开槽空隙的片材之一，在第二方向上具有开槽空隙的片材和具有棋盘空隙的片材。

27. 发明授权

US06486002B1 Tape design to reduce warpage 有权
标题翻译：胶带设计减少翘曲
公开(公告)号：US06486002B1
公开(公告)日：2002-11-26
申请号：US09894718
申请日：2001-06-27
申请人： Qwai H. Low , Ramaswamy Ranganathan , Sengsooi Lim
发明人： Qwai H. Low , Ramaswamy Ranganathan , Sengsooi Lim
IPC分类号： H01L2144
CPC分类号： H01L23/4985 , H01L23/49838 , H01L2924/0002 , H01L2924/00
摘要： An improved tape substrate design for a semiconductor package is disclosed. The tape substrate semiconductor package includes a plurality of die pads, a plurality of vias, and a pattern of metal traces interconnected between the die pads and the vias to form circuitry on the tape substrate. According to the method and apparatus of the present invention an extra metal layer is added at the circuitry to increase rigidity of the tape substrate, thereby reducing warpage without adding to the thickness of the tape substrate package.
摘要翻译：公开了用于半导体封装的改进的带基片设计。带衬底半导体封装包括多个管芯焊盘，多个通孔和在管芯焊盘和通孔之间互连的金属迹线图案，以在带基片上形成电路。根据本发明的方法和装置，在电路处添加额外的金属层以增加带基材的刚性，从而减少翘曲而不增加带基材封装的厚度。

28. 发明授权

US06998638B2 Test structure for detecting bonding-induced cracks 有权
标题翻译：用于检测接合引起的裂纹的测试结构
公开(公告)号：US06998638B2
公开(公告)日：2006-02-14
申请号：US10856213
申请日：2004-05-28
申请人： Qwai H. Low , Ramaswamy Ranganathan , Anwar Ali , Tauman T. Lau
发明人： Qwai H. Low , Ramaswamy Ranganathan , Anwar Ali , Tauman T. Lau
IPC分类号： H01L23/58
CPC分类号： H01L24/05 , H01L22/34 , H01L24/48 , H01L2224/04042 , H01L2224/05001 , H01L2224/05073 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer. The sensing layer immediately underlies the at least one of the non electrically conductive layers in the test structure that has no vias formed therein. Thus, a crack in the at least one of the non electrically conductive layers in the test structure that has no vias formed therein is detectable as a leakage current between the bonding pad of the test structure and a top most electrically conductive layer of the control structure.
摘要翻译：具有裂纹检测结构的集成电路。形成具有垂直取向的交错导电层和非导电层的控制结构。导电通孔垂直地设置在所有非导电层上，通孔将所有的导电层彼此电连接。形成具有用于探测和结合的接合焊盘的测试结构，其中底层交错的导电层和以垂直取向设置的非导电层。非导电层中的至少一个在其中没有形成通孔，模拟集成电路的其它接合焊盘下的有源电路。控制结构的交错导电层中的至少一个从控制结构内延伸到作为感测层的测试结构内。感测层紧邻在其中形成有通孔的测试结构中的非导电层中的至少一个之上。因此，测试结构中没有形成通孔的非导电层中的至少一个的裂纹可以被检测为在测试结构的焊盘与控制结构的最高导电层之间的漏电流。

29. 发明授权

US06825563B1 Slotted bonding pad 有权
标题翻译：开槽接合垫
公开(公告)号：US06825563B1
公开(公告)日：2004-11-30
申请号：US10683101
申请日：2003-10-09
申请人： Ramaswamy Ranganathan , Maurice Othieno , Qwai H. Low
发明人： Ramaswamy Ranganathan , Maurice Othieno , Qwai H. Low
IPC分类号： H01L2348
CPC分类号： H01L24/05 , H01L2224/05556 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： A bonding pad structure having an electrically conductive capping layer. An electrically conductive first supporting layer having major orthogonal sides is disposed under the electrically conductive capping layer. The electrically conductive first supporting layer is configured as a sheet having slotted voids in a first direction. An electrically conductive second supporting layer having major orthogonal sides is disposed under the electrically conductive first supporting layer. The electrically conductive second supporting layer is configured as a sheet having slotted voids in a second direction. The first direction and the second direction are associated one with another by being disposed at a positive value and a negative value of an angle, where the angle is neither zero nor ninety degrees with respect to the major orthogonal sides of the electrically conductive first supporting layer and the electrically conductive second supporting layer.
摘要翻译：一种具有导电覆盖层的焊盘结构。具有主正交侧面的导电的第一支撑层设置在导电覆盖层的下方。导电性第一支撑层被构造成在第一方向上具有开槽空隙的片材。具有主要正交侧面的导电的第二支撑层设置在导电的第一支撑层的下方。导电的第二支撑层被构造成在第二方向上具有开槽空隙的片材。第一方向和第二方向通过以相对于导电的第一支撑层的主正交侧的角度不为零也不是九十度的角度的正值和负值设置而彼此相关联和导电的第二支撑层。

30. 发明授权

US06573113B1 Integrated circuit having dedicated probe pads for use in testing densely patterned bonding pads 有权
标题翻译：具有用于测试密集图案化焊盘的专用探针焊盘的集成电路
公开(公告)号：US06573113B1
公开(公告)日：2003-06-03
申请号：US09946033
申请日：2001-09-04
申请人： Qwai H. Low , William T. Bright, II , Ramaswamy Ranganathan
发明人： Qwai H. Low , William T. Bright, II , Ramaswamy Ranganathan
IPC分类号： H01L2166
CPC分类号： H01L22/32 , G01R31/2886 , H01L24/05 , H01L2224/0392 , H01L2224/05552 , H01L2224/05554 , H01L2224/45144 , H01L2924/14 , H01L2924/00
摘要： An integrated circuit topography is provided which includes at least two rows of bonding pads. Each row of bonding pads is attributed a row of probe pads. One row of probe pads is contained within the scribe area and suffices as a sacrificial row of probe pads. The other row of probe pads is placed toward the interior of the integrated circuit. The rows of bonding pads and probe pads extend along parallel axis around all four sides of the integrated circuit. Every other bonding pad within one row of bonding pads is connected to every other probe pad within the scribe area, and every other bonding pad within the other rows of bonding pads is connected to every probe pad within the row of probe pads interior to the integrated circuit. This allows a fan-out configuration of the bonding pads to probe pads for purposes of probing electrical performance of the integrated circuit without having to use selected ones of the bonding pads. This prevents jeopardizing the integrity of the bonding pad by gouging out the bonding pad during probe operation. Moreover, thicker probe needles can be used, and placed in a less dense fashion around the outer perimeter of the integrated circuit.
摘要翻译：提供了一种集成电路形貌，其包括至少两排接合焊盘。每排接合焊盘归因于一排探针焊盘。一排探针垫被包含在划线区域内，并且足以作为牺牲排的探针垫。另一排探针垫朝向集成电路的内部放置。接合焊盘和探针焊盘的行围绕集成电路的所有四个边沿平行轴延伸。一排接合焊盘内的每个其他接合焊盘都连接到划线区内的每隔一个探头焊盘，另一排接合焊盘内的每个其他接合焊盘连接到集成的内部的探针焊盘内的每个探针焊盘电路。为了探测集成电路的电气性能而不必使用选定的接合焊盘，这允许焊盘的扇出配置探针焊盘。这可以防止在探针操作期间通过焊接焊盘来破坏接合焊盘的完整性。此外，可以使用较厚的探针，并且围绕集成电路的外周边以较不密集的方式放置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式