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1. 发明授权

US06798035B1 Bonding pad for low k dielectric 有权
标题翻译：低k电介质接合垫
公开(公告)号：US06798035B1
公开(公告)日：2004-09-28
申请号：US10600255
申请日：2003-06-20
申请人： Qwai H. Low , Ramaswamy Ranganathan , Edwin M. Fulcher
发明人： Qwai H. Low , Ramaswamy Ranganathan , Edwin M. Fulcher
IPC分类号： H01L3100
CPC分类号： H01L24/05 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： A bonding pad structure having an electrically conductive capping layer. An electrically conductive first supporting layer is disposed immediately under the electrically conductive capping layer, without any intervening layers between the electrically conductive capping layer and the electrically conductive first supporting layer. The electrically conductive first supporting layer is configured as one of a sheet having no voids and a sheet having slotted voids in a first direction. An electrically conductive second supporting layer is disposed under the electrically conductive first supporting layer. The electrically conductive second supporting layer is configured as one of a sheet having slotted voids in the first direction, a sheet having slotted voids in a second direction, and a sheet having checkerboard voids.
摘要翻译：一种具有导电覆盖层的焊盘结构。导电的第一支撑层设置在导电覆盖层的正下方，在导电覆盖层和导电的第一支撑层之间没有任何中间层。导电性第一支撑层被构造为没有空隙的片材之一和在第一方向上具有开槽空隙的片材。导电的第二支撑层设置在导电的第一支撑层之下。导电性第二支撑层被构造为在第一方向上具有开槽空隙的片材之一，在第二方向上具有开槽空隙的片材和具有棋盘空隙的片材。

2. 发明授权

US06781150B2 Test structure for detecting bonding-induced cracks 有权
标题翻译：用于检测接合引起的裂纹的测试结构
公开(公告)号：US06781150B2
公开(公告)日：2004-08-24
申请号：US10229601
申请日：2002-08-28
申请人： Qwai H. Low , Ramaswamy Ranganathan , Anwar Ali , Tauman T. Lau
发明人： Qwai H. Low , Ramaswamy Ranganathan , Anwar Ali , Tauman T. Lau
IPC分类号： H01L2358
CPC分类号： H01L24/05 , H01L22/34 , H01L24/48 , H01L2224/04042 , H01L2224/05001 , H01L2224/05073 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer. The sensing layer immediately underlies the at least one of the non electrically conductive layers in the test structure that has no vias formed therein. Thus, a crack in the at least one of the non electrically conductive layers in the test structure that has no vias formed therein is detectable as a leakage current between the bonding pad of the test structure and a top most electrically conductive layer of the control structure.
摘要翻译：具有裂纹检测结构的集成电路。形成具有垂直取向的交错导电层和非导电层的控制结构。导电通孔垂直地设置在所有非导电层上，通孔将所有的导电层彼此电连接。形成具有用于探测和结合的接合焊盘的测试结构，其中底层交错的导电层和以垂直取向设置的非导电层。非导电层中的至少一个在其中没有形成通孔，模拟集成电路的其它接合焊盘下的有源电路。控制结构的交错导电层中的至少一个从控制结构内延伸到作为感测层的测试结构内。感测层紧邻在其中形成有通孔的测试结构中的非导电层中的至少一个之上。因此，测试结构中没有形成通孔的非导电层中的至少一个的裂纹可以被检测为在测试结构的焊盘与控制结构的最高导电层之间的漏电流。

3. 发明授权

US06963138B2 Dielectric stack 有权
标题翻译：电介质堆
公开(公告)号：US06963138B2
公开(公告)日：2005-11-08
申请号：US10357142
申请日：2003-02-03
申请人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan , Tauman T. Lau
发明人： Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan , Tauman T. Lau
IPC分类号： H01L23/485 , H01L23/532 , H01L23/48
CPC分类号： H01L24/05 , H01L23/53295 , H01L2224/05093 , H01L2224/05556 , H01L2224/05624 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2924/00
摘要： An integrated circuit with a pressure resistant current carrying structure having electrically conductive layers for carrying current. A first electrically nonconductive material at least partially surrounds the electrically conductive layers, and provides electrical insulation between the electrically conductive layers. The first electrically nonconductive material has a first degree of fragility and a first dielectric constant. A second electrically nonconductive material is disposed in a pattern within the first electrically nonconductive material and between the electrically conductive layers, and provides structural support for the first electrically nonconductive material between the electrically conductive layers. The second electrically nonconductive material has a second degree of fragility that is less than the first degree of fragility and a second dielectric constant that is greater than the first dielectric constant.
摘要翻译：一种具有耐压载流结构的集成电路，其具有用于承载电流的导电层。第一非导电材料至少部分地围绕导电层，并且在导电层之间提供电绝缘。第一非导电材料具有第一程度的脆性和第一介电常数。第二非导电材料以第一非导电材料内部和导电层之间的图案设置，并为导电层之间的第一非导电材料提供结构支撑。第二非导电材料具有小于第一脆性程度的第二脆性程度和大于第一介电常数的第二介电常数。

4. 发明授权

US06486002B1 Tape design to reduce warpage 有权
标题翻译：胶带设计减少翘曲
公开(公告)号：US06486002B1
公开(公告)日：2002-11-26
申请号：US09894718
申请日：2001-06-27
申请人： Qwai H. Low , Ramaswamy Ranganathan , Sengsooi Lim
发明人： Qwai H. Low , Ramaswamy Ranganathan , Sengsooi Lim
IPC分类号： H01L2144
CPC分类号： H01L23/4985 , H01L23/49838 , H01L2924/0002 , H01L2924/00
摘要： An improved tape substrate design for a semiconductor package is disclosed. The tape substrate semiconductor package includes a plurality of die pads, a plurality of vias, and a pattern of metal traces interconnected between the die pads and the vias to form circuitry on the tape substrate. According to the method and apparatus of the present invention an extra metal layer is added at the circuitry to increase rigidity of the tape substrate, thereby reducing warpage without adding to the thickness of the tape substrate package.
摘要翻译：公开了用于半导体封装的改进的带基片设计。带衬底半导体封装包括多个管芯焊盘，多个通孔和在管芯焊盘和通孔之间互连的金属迹线图案，以在带基片上形成电路。根据本发明的方法和装置，在电路处添加额外的金属层以增加带基材的刚性，从而减少翘曲而不增加带基材封装的厚度。

5. 发明授权

US06998638B2 Test structure for detecting bonding-induced cracks 有权
标题翻译：用于检测接合引起的裂纹的测试结构
公开(公告)号：US06998638B2
公开(公告)日：2006-02-14
申请号：US10856213
申请日：2004-05-28
申请人： Qwai H. Low , Ramaswamy Ranganathan , Anwar Ali , Tauman T. Lau
发明人： Qwai H. Low , Ramaswamy Ranganathan , Anwar Ali , Tauman T. Lau
IPC分类号： H01L23/58
CPC分类号： H01L24/05 , H01L22/34 , H01L24/48 , H01L2224/04042 , H01L2224/05001 , H01L2224/05073 , H01L2224/05093 , H01L2224/05095 , H01L2224/05624 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer. The sensing layer immediately underlies the at least one of the non electrically conductive layers in the test structure that has no vias formed therein. Thus, a crack in the at least one of the non electrically conductive layers in the test structure that has no vias formed therein is detectable as a leakage current between the bonding pad of the test structure and a top most electrically conductive layer of the control structure.
摘要翻译：具有裂纹检测结构的集成电路。形成具有垂直取向的交错导电层和非导电层的控制结构。导电通孔垂直地设置在所有非导电层上，通孔将所有的导电层彼此电连接。形成具有用于探测和结合的接合焊盘的测试结构，其中底层交错的导电层和以垂直取向设置的非导电层。非导电层中的至少一个在其中没有形成通孔，模拟集成电路的其它接合焊盘下的有源电路。控制结构的交错导电层中的至少一个从控制结构内延伸到作为感测层的测试结构内。感测层紧邻在其中形成有通孔的测试结构中的非导电层中的至少一个之上。因此，测试结构中没有形成通孔的非导电层中的至少一个的裂纹可以被检测为在测试结构的焊盘与控制结构的最高导电层之间的漏电流。

6. 发明授权

US06825563B1 Slotted bonding pad 有权
标题翻译：开槽接合垫
公开(公告)号：US06825563B1
公开(公告)日：2004-11-30
申请号：US10683101
申请日：2003-10-09
申请人： Ramaswamy Ranganathan , Maurice Othieno , Qwai H. Low
发明人： Ramaswamy Ranganathan , Maurice Othieno , Qwai H. Low
IPC分类号： H01L2348
CPC分类号： H01L24/05 , H01L2224/05556 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： A bonding pad structure having an electrically conductive capping layer. An electrically conductive first supporting layer having major orthogonal sides is disposed under the electrically conductive capping layer. The electrically conductive first supporting layer is configured as a sheet having slotted voids in a first direction. An electrically conductive second supporting layer having major orthogonal sides is disposed under the electrically conductive first supporting layer. The electrically conductive second supporting layer is configured as a sheet having slotted voids in a second direction. The first direction and the second direction are associated one with another by being disposed at a positive value and a negative value of an angle, where the angle is neither zero nor ninety degrees with respect to the major orthogonal sides of the electrically conductive first supporting layer and the electrically conductive second supporting layer.
摘要翻译：一种具有导电覆盖层的焊盘结构。具有主正交侧面的导电的第一支撑层设置在导电覆盖层的下方。导电性第一支撑层被构造成在第一方向上具有开槽空隙的片材。具有主要正交侧面的导电的第二支撑层设置在导电的第一支撑层的下方。导电的第二支撑层被构造成在第二方向上具有开槽空隙的片材。第一方向和第二方向通过以相对于导电的第一支撑层的主正交侧的角度不为零也不是九十度的角度的正值和负值设置而彼此相关联和导电的第二支撑层。

7. 发明授权

US06743979B1 Bonding pad isolation 有权
标题翻译：粘接垫隔离
公开(公告)号：US06743979B1
公开(公告)日：2004-06-01
申请号：US10652453
申请日：2003-08-29
申请人： Michael J. Berman , Aftab Ahmad , Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
发明人： Michael J. Berman , Aftab Ahmad , Qwai H. Low , Chok J. Chia , Ramaswamy Ranganathan
IPC分类号： H05K506
CPC分类号： H01L24/06 , H01L24/05 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48463 , H01L2224/49431 , H01L2224/85399 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2224/45099 , H01L2924/00012
摘要： An integrated circuit, including a substrate with circuitry formed therein, where the substrate has a peripheral edge. Also included are a top most electrically conductive layer and an underlying electrically conductive layer. Outer bonding pads are disposed in an outer ring, and are formed within the top most layer. Inner bonding pads are disposed in an inner ring, and are formed within the top most layer. Inner connectors electrically connect the inner bonding pads to the circuitry. The inner connectors are formed within the underlying layer, and have a width that is less than the width of the inner bonding pads, thereby defining a gap between the inner connectors. Outer connectors electrically connect the outer bonding pads to the circuitry. The outer connectors are formed within the underlying layer, and have a width that is less than the width of the gap between the inner connectors.
摘要翻译：一种集成电路，包括其中形成有电路的衬底，其中衬底具有外围边缘。还包括最顶层的导电层和底层导电层。外部接合焊盘设置在外圈中，并形成在最上层。内部接合焊盘设置在内圈中，并且形成在最顶层内。内部连接器将内部接合焊盘电连接到电路。内部连接器形成在下面的层中，并且具有小于内部焊盘的宽度的宽度，由此限定内部连接器之间的间隙。外部连接器将外部接合焊盘电连接到电路。外部连接器形成在下面的层中，并且具有小于内部连接器之间的间隙的宽度的宽度。

8. 发明授权

US06573113B1 Integrated circuit having dedicated probe pads for use in testing densely patterned bonding pads 有权
标题翻译：具有用于测试密集图案化焊盘的专用探针焊盘的集成电路
公开(公告)号：US06573113B1
公开(公告)日：2003-06-03
申请号：US09946033
申请日：2001-09-04
申请人： Qwai H. Low , William T. Bright, II , Ramaswamy Ranganathan
发明人： Qwai H. Low , William T. Bright, II , Ramaswamy Ranganathan
IPC分类号： H01L2166
CPC分类号： H01L22/32 , G01R31/2886 , H01L24/05 , H01L2224/0392 , H01L2224/05552 , H01L2224/05554 , H01L2224/45144 , H01L2924/14 , H01L2924/00
摘要： An integrated circuit topography is provided which includes at least two rows of bonding pads. Each row of bonding pads is attributed a row of probe pads. One row of probe pads is contained within the scribe area and suffices as a sacrificial row of probe pads. The other row of probe pads is placed toward the interior of the integrated circuit. The rows of bonding pads and probe pads extend along parallel axis around all four sides of the integrated circuit. Every other bonding pad within one row of bonding pads is connected to every other probe pad within the scribe area, and every other bonding pad within the other rows of bonding pads is connected to every probe pad within the row of probe pads interior to the integrated circuit. This allows a fan-out configuration of the bonding pads to probe pads for purposes of probing electrical performance of the integrated circuit without having to use selected ones of the bonding pads. This prevents jeopardizing the integrity of the bonding pad by gouging out the bonding pad during probe operation. Moreover, thicker probe needles can be used, and placed in a less dense fashion around the outer perimeter of the integrated circuit.
摘要翻译：提供了一种集成电路形貌，其包括至少两排接合焊盘。每排接合焊盘归因于一排探针焊盘。一排探针垫被包含在划线区域内，并且足以作为牺牲排的探针垫。另一排探针垫朝向集成电路的内部放置。接合焊盘和探针焊盘的行围绕集成电路的所有四个边沿平行轴延伸。一排接合焊盘内的每个其他接合焊盘都连接到划线区内的每隔一个探头焊盘，另一排接合焊盘内的每个其他接合焊盘连接到集成的内部的探针焊盘内的每个探针焊盘电路。为了探测集成电路的电气性能而不必使用选定的接合焊盘，这允许焊盘的扇出配置探针焊盘。这可以防止在探针操作期间通过焊接焊盘来破坏接合焊盘的完整性。此外，可以使用较厚的探针，并且围绕集成电路的外周边以较不密集的方式放置。

9. 发明授权

US06329278B1 Multiple row wire bonding with ball bonds of outer bond pads bonded on the leads 有权
标题翻译：多引线接合，焊接在引线上的外键合焊盘的球键
公开(公告)号：US06329278B1
公开(公告)日：2001-12-11
申请号：US09476958
申请日：2000-01-03
申请人： Qwai H. Low , Ramaswamy Ranganathan , Rey Torcuato
发明人： Qwai H. Low , Ramaswamy Ranganathan , Rey Torcuato
IPC分类号： H01L2144
CPC分类号： H01L24/85 , H01L24/05 , H01L24/06 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/32225 , H01L2224/4809 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/49171 , H01L2224/49431 , H01L2224/4945 , H01L2224/73265 , H01L2224/85191 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/78 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A method of forming a low loop height wire interconnection in a semiconductor package including a die having a multiple row bond pad layout, and a wire bonded electrical interconnection formed using the method consists of the steps: forming a first ball bond from a first wire at a first bonding location; looping the first wire to a first bond pad of a die; forming a first stitch bond between the first wire and the first bond pad; forming a second ball bond from a second wire at a second bond pad of the die; looping the second wire to a second bonding location, wherein the second wire does not contact the first wire; and forming a second stitch bond between the second wire and the second bonding location.
摘要翻译：在包括具有多排接合焊盘布局的管芯的半导体封装中形成低回路高度布线互连的方法以及使用该方法形成的引线接合电互连的方法包括以下步骤：从第一布线形成第一球焊第一粘合位置; 将第一导线环绕到模具的第一接合焊盘; 在所述第一线和所述第一接合焊盘之间形成第一缝合; 在所述模具的第二接合焊盘处从第二线形成第二球接合; 将所述第二线圈环绕到第二接合位置，其中所述第二线不接触所述第一线; 以及在所述第二线和所述第二接合位置之间形成第二线圈接合。

10. 发明授权

US06861748B2 Test structure 失效
标题翻译：测试结构
公开(公告)号：US06861748B2
公开(公告)日：2005-03-01
申请号：US10298971
申请日：2002-11-18
申请人： Qwai H. Low , Ramaswamy Ranganathan , Rey Torcuato
发明人： Qwai H. Low , Ramaswamy Ranganathan , Rey Torcuato
IPC分类号： H01L23/544 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L22/34 , H01L2224/45144 , H01L2224/48463 , H01L2924/00
摘要： A test structure for an integrated circuit having a first underlying conductive layer. A first nonconductive layer is disposed over the first underlying conductive layer, and a first overlying conductive layer is disposed over the first nonconductive layer. First conductive vias form electrical connections between the first underlying conductive layer and the first overlying conductive layer. A second overlying conductive layer is disposed over the first nonconductive layer, but the second overlying conductive layer does not make electrical connections to the first underlying conductive layer. The test structure also has a second underlying conductive layer. A second nonconductive layer is disposed over the second underlying conductive layer, with a third overlying conductive layer disposed over the second nonconductive layer. The third overlying conductive layer does not make electrical connections to the second underlying conductive layer. A fourth overlying conductive layer is disposed over the second nonconductive layer, and second conductive vias form electrical connections between the second underlying conductive layer and the fourth overlying conductive layer. First conductive traces form electrical connections between the first overlying conductive layer and the third conductive layer, and second conductive traces form electrical connections between the second overlying conductive layer and the fourth conductive layer.
摘要翻译：一种用于具有第一底层导电层的集成电路的测试结构。第一非导电层设置在第一下导电层上，并且第一上覆导电层设置在第一非导电层上。第一导电通孔在第一底层导电层和第一上覆导电层之间形成电连接。第二覆盖导电层设置在第一非导电层上，但是第二覆盖导电层不与第一下面的导电层形成电连接。测试结构还具有第二底层导电层。第二非导电层设置在第二下导电层之上，第三覆盖导电层设置在第二非导电层上。第三覆盖导电层不与第二底层导电层形成电连接。第四覆盖导电层设置在第二非导电层上，第二导电通孔在第二下导电层和第四覆盖导电层之间形成电连接。第一导电迹线在第一覆盖导电层和第三导电层之间形成电连接，第二导电迹线在第二覆盖导电层和第四导电层之间形成电连接。

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