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21. 发明授权

US07853632B2 Architectural floorplan for a digital signal processing circuit 有权
标题翻译：数字信号处理电路的建筑平面布置图
公开(公告)号：US07853632B2
公开(公告)日：2010-12-14
申请号：US11433369
申请日：2006-05-12
申请人： Alvin Y. Ching , Jennifer Wong , Bernard J. New , James M. Simkins , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
发明人： Alvin Y. Ching , Jennifer Wong , Bernard J. New , James M. Simkins , John M. Thendean , Anna Wing Wah Wong , Vasisht Mantra Vadi
IPC分类号： G06F7/38
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： A physical floorplan for a digital signal processing (DSP) block including; an interconnect column having a plurality of programmable interconnect elements; a first DSP element having a plurality of first columns, a first output register column of the plurality of first columns positioned adjacent to the interconnect column; and a second DSP element, having a plurality of second columns a second output register column of the plurality of second columns positioned adjacent to the interconnect column.
摘要翻译：数字信号处理（DSP）块的物理平面图，包括：具有多个可编程互连元件的互连柱; 具有多个第一列的第一DSP元件，与所述互连列相邻定位的所述多个第一列中的第一输出寄存器列; 以及第二DSP元件，具有多个第二列，所述多个第二列的第二输出寄存器列与所述互连列相邻。

22. 发明授权

US07840630B2 Arithmetic logic unit circuit 有权
标题翻译：算术逻辑单元电路
公开(公告)号：US07840630B2
公开(公告)日：2010-11-23
申请号：US11433333
申请日：2006-05-12
申请人： Anna Wing Wah Wong , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , James M. Simkins , Vasisht Mantra Vadi , David P. Schultz
发明人： Anna Wing Wah Wong , Jennifer Wong , Bernard J. New , Alvin Y. Ching , John M. Thendean , James M. Simkins , Vasisht Mantra Vadi , David P. Schultz
IPC分类号： G06F7/38
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： An Arithmetic Logic Unit that includes first multiplexers coupled to a first adder, the first multiplexers controlled by a first opcode register; second multiplexers receiving input from the first adder and coupled to a second adder; and a second opcode register for controlling one or more of the second multiplexers, the first adder, or the second adder. A combination of the bits in the first and second opcode registers configures the ALU to perform one or more arithmetic operations or one or more logic operations or any combination thereof.
摘要翻译：一种算术逻辑单元，包括耦合到第一加法器的第一多路复用器，由第一操作码寄存器控制的第一多路复用器; 第二多路复用器，从第一加法器接收输入并耦合到第二加法器; 以及用于控制第二多路复用器，第一加法器或第二加法器中的一个或多个的第二操作码寄存器。第一和第二操作码寄存器中的位的组合构成ALU以执行一个或多个算术运算或一个或多个逻辑运算或其任何组合。

23. 发明申请

US20100092534A1 Combination Local Delivery Using a Stent 审中-公开
标题翻译：组合使用支架本地交付
公开(公告)号：US20100092534A1
公开(公告)日：2010-04-15
申请号：US12249576
申请日：2008-10-10
申请人： Ayala Hezi-Yamit , Iskender Matt Bilge , Jennifer Wong , Carol Sullivan , Natividad Vasquez
发明人： Ayala Hezi-Yamit , Iskender Matt Bilge , Jennifer Wong , Carol Sullivan , Natividad Vasquez
IPC分类号： A61F2/04 , A61K31/58 , A61K31/4355
CPC分类号： A61L31/10 , A61L31/16 , A61L2300/222 , A61L2300/416 , A61L2300/45
摘要： Described herein are implantable medical devices useful in treating vascular conditions such as restenosis. In one embodiment, stents are described in which a combination of bioactive agents is described for local delivery in the vasculature. The combination of bioactive agents comprises at least one compound capable of inhibiting smooth muscle cell proliferation and at least one compound capable of mitigating MCP- and/or TF induction. For example, a compound capable of inhibiting smooth muscle cell proliferation is a mTOR inhibitor and a compound capable of mitigating MCP-1 and/or TF induction is a corticosteroid.
摘要翻译：本文描述了可用于治疗诸如再狭窄的血管病变的可植入医疗装置。在一个实施方案中，描述了支架，其中描述了生物活性剂的组合用于脉管系统中的局部递送。生物活性剂的组合包含至少一种能够抑制平滑肌细胞增殖的化合物和至少一种能够减轻MCP-和/或TF诱导的化合物。例如，能够抑制平滑肌细胞增殖的化合物是mTOR抑制剂，能够缓解MCP-1和/或TF诱导的化合物是皮质类固醇。

24. 发明授权

US07480690B2 Arithmetic circuit with multiplexed addend inputs 有权
标题翻译：具有复用加法输入的算术电路
公开(公告)号：US07480690B2
公开(公告)日：2009-01-20
申请号：US11019854
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/48
CPC分类号： G06F7/509
摘要： Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.
摘要翻译：描述的是算术电路，逻辑上分为乘积发生器和加法器。逻辑上位于产品发生器和加法器之间的多路复用电路通过提供来自产品发生器的部分乘积到加法器的末端来支持常规功能。还可以控制复用电路以将多个外部添加的输入引导到加法器。附加加数输入可以包括从其他算术电路级联的输入和输出。

25. 发明授权

US07467177B2 Mathematical circuit with dynamic rounding 有权
标题翻译：具有动态四舍五入的数学电路
公开(公告)号：US07467177B2
公开(公告)日：2008-12-16
申请号：US11019853
申请日：2004-12-21
申请人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
发明人： James M. Simkins , Steven P. Young , Jennifer Wong , Bernard J. New , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： G06F7/49963
摘要： Described are mathematical circuits that perform flexible rounding schemes. The circuits require few additional resources and can be adjusted dynamically to change the number of bits involved in the rounding. In one embodiment, a DSP circuit stores a rounding constant selected from the group of binary numbers 2(M−1) and 2(M−1)−1, calculates a correction factor, and sums the rounding constant, the correction factor, and a data item to obtain a rounded data item.
摘要翻译：描述了执行灵活舍入方案的数学电路。这些电路需要很少的额外资源，并且可以动态调整以改变舍入所涉及的位数。在一个实施例中，DSP电路存储从二进制数2（M-1）和2（M-1）-1组中选择的舍入常数，计算校正因子，并将舍入常数，校正因子和一个数据项以获得舍入的数据项。

26. 发明授权

US07038519B1 Digital clock manager having cascade voltage switch logic clock paths 有权
标题翻译：数字时钟管理器具有级联电压开关逻辑时钟路径
公开(公告)号：US07038519B1
公开(公告)日：2006-05-02
申请号：US10837324
申请日：2004-04-30
申请人： Raymond C. Pang , Jennifer Wong
发明人： Raymond C. Pang , Jennifer Wong
IPC分类号： H03H11/26
CPC分类号： H03K19/1738 , H03H11/26 , H03K2005/00195 , H03K2005/00228 , H03K2005/00234
摘要： A digital clock manager having differential clock signal paths is provided. The differential clock signal paths are provided by replacing single-ended circuit elements of a conventional digital clock manager with symmetrical cascade voltage switch logic (CVSL) circuit elements, including CVSL delay buffers, CVSL multiplexers, CVSL AND gates, CVSL OR gates and CVSL set-reset latches. These symmetrical CVSL AND gates, CVSL OR gates and CVSL set-reset latches represent new circuit elements.
摘要翻译：提供具有差分时钟信号路径的数字时钟管理器。差分时钟信号路径通过用传统数字时钟管理器的单端电路元件替代对称级联电压开关逻辑（CVSL）电路元件来提供，包括CVSL延迟缓冲器，CVSL多路复用器，CVSL与门，CVSL或门和CVSL组 - 锁存器。这些对称的CVSL与门，CVSL或门和CVSL设置复位锁存器代表新的电路元件。

27. 发明授权

US06803786B1 Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks 有权
标题翻译：在逻辑块阵列中提供紧密耦合的处理器和RAM块列的结构和方法
公开(公告)号：US06803786B1
公开(公告)日：2004-10-12
申请号：US10386955
申请日：2003-03-11
申请人： Goran Bilski , Ralph D. Wittig , Jennifer Wong , David B. Squires
发明人： Goran Bilski , Ralph D. Wittig , Jennifer Wong , David B. Squires
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , G06F15/7867 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.
摘要翻译：在现有PLD架构中包含处理器能力的结构和方法，对现有的一般互连结构的影响最小。在包括块RAM（BRAM）块列的PLD中，BRAM块被修改以创建专用的逻辑块，包括RAM，处理器和耦合在RAM，处理器和通用互连结构之间的专用接口 PLD。通过增加BRAM块的列的宽度来获得附加区域。因为互连结构几乎保持不变，所以专用逻辑块和相邻的瓦片之间的互连已经就位，并且修改不影响PLD路由软件。在一些实施例中，处理器可以可选地被禁用，对于用户变得透明。其他实施例提供了修改PLD以包括结构并提供上述能力的方法。

28. 发明授权

US06441641B1 Programmable logic device with partial battery backup 有权
标题翻译：具有部分电池备份的可编程逻辑器件
公开(公告)号：US06441641B1
公开(公告)日：2002-08-27
申请号：US09724735
申请日：2000-11-28
申请人： Raymond C. Pang , Venu M. Kondapalli , Jane W. Sowards , Scott O. Frake , Jennifer Wong , F. Erich Goetting , Peter H. Alfke , Schuyler E. Shimanek
发明人： Raymond C. Pang , Venu M. Kondapalli , Jane W. Sowards , Scott O. Frake , Jennifer Wong , F. Erich Goetting , Peter H. Alfke , Schuyler E. Shimanek
IPC分类号： H01L2500
CPC分类号： G06F21/76
摘要： A PLD can be manufactured to include power supply lines from two sources so that a portion of the PLD can be backed up with a battery when power to the PLD is removed. A switch that supplies power to the backed up portion of the PLD receives power from both an external power supply and from the battery, and detects voltage level of the external power supply, switching to battery power when voltage from the external power supply is not sufficient.
摘要翻译：可以制造PLD以包括来自两个源的电源线，使得当PLD的电源被去除时，一部分PLD可以用电池备份。向PLD的备用部分供电的开关从外部电源和电池两者接收电力，并检测外部电源的电压，当来自外部电源的电压不足时切换到电池电力。

29. 发明授权

US5784313A Programmable logic device including configuration data or user data memory slices 失效
公开(公告)号：US5784313A
公开(公告)日：1998-07-21
申请号：US516808
申请日：1995-08-18
申请人： Stephen M. Trimberger , Richard A. Carberry , Robert Anders Johnson , Jennifer Wong
发明人： Stephen M. Trimberger , Richard A. Carberry , Robert Anders Johnson , Jennifer Wong
IPC分类号： G06F17/50 , G11C5/00 , H03K19/177 , G11C13/00
CPC分类号： H03K19/17776 , G06F17/5054 , H03K19/17752 , H03K19/17756 , H03K19/1776
摘要： A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.

30. 发明授权

US07844653B2 Digital signal processing circuit having a pre-adder circuit 有权
标题翻译：具有预加法器电路的数字信号处理电路
公开(公告)号：US07844653B2
公开(公告)日：2010-11-30
申请号：US11432848
申请日：2006-05-12
申请人： James M. Simkins , John M. Thendean , Vasisht Mantra Vadi , Bernard J. New , Jennifer Wong , Anna Wing Wah Wong , Alvin Y. Ching
发明人： James M. Simkins , John M. Thendean , Vasisht Mantra Vadi , Bernard J. New , Jennifer Wong , Anna Wing Wah Wong , Alvin Y. Ching
IPC分类号： G06F7/38
CPC分类号： G06F7/02 , G06F7/5443 , G06F7/57 , G06F7/575 , G06F2207/025 , G06F2207/3828 , G06K9/00986 , H03K19/1737
摘要： A digital signal processing circuit having a pre-adder circuit includes; a first register block and a pre-adder circuit coupled to a multiplier circuit and to a set of multiplexers, where the set of multiplexers are controlled by an opcode, and where the pre-adder circuit has a first adder circuit; and an arithmetic logic unit (ALU) having a second adder circuit and coupled to the set of multiplexers.
摘要翻译：具有预加法器电路的数字信号处理电路包括：耦合到乘法器电路和一组多路复用器的第一寄存器块和预加法器电路，其中多路复用器组由操作码控制，并且其中预加法器电路具有第一加法器电路; 以及具有第二加法器电路并耦合到所述多路复用器组的算术逻辑单元（ALU）。

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