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1. 发明授权

US06946874B1 Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks 有权
标题翻译：在逻辑块阵列中提供紧密耦合的处理器和RAM块列的结构和方法
公开(公告)号：US06946874B1
公开(公告)日：2005-09-20
申请号：US10927750
申请日：2004-08-27
申请人： Goran Bilski , Ralph D. Wittig , Jennifer Wong , David B. Squires
发明人： Goran Bilski , Ralph D. Wittig , Jennifer Wong , David B. Squires
IPC分类号： G06F15/78 , H03K19/177 , H03K19/0177
CPC分类号： H03K19/1776 , G06F15/7867 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.
摘要翻译：在现有PLD架构中包含处理器能力的结构和方法，对现有的一般互连结构的影响最小。在包括块RAM（BRAM）块的PLD中，BRAM块被修改以创建专用逻辑块，包括RAM，处理器和耦合在RAM，处理器和通用互连结构之间的专用接口 PLD。通过增加BRAM块的列的宽度来获得附加区域。由于互连结构几乎保持不变，所以专用逻辑块和相邻的瓦片之间的互连已经就位，并且修改不会影响PLD路由软件。在一些实施例中，处理器可以可选地被禁用，对于用户变得透明。其他实施例提供了修改PLD以包括结构并提供上述能力的方法。

2. 发明授权

US06803786B1 Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks 有权
标题翻译：在逻辑块阵列中提供紧密耦合的处理器和RAM块列的结构和方法
公开(公告)号：US06803786B1
公开(公告)日：2004-10-12
申请号：US10386955
申请日：2003-03-11
申请人： Goran Bilski , Ralph D. Wittig , Jennifer Wong , David B. Squires
发明人： Goran Bilski , Ralph D. Wittig , Jennifer Wong , David B. Squires
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , G06F15/7867 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.
摘要翻译：在现有PLD架构中包含处理器能力的结构和方法，对现有的一般互连结构的影响最小。在包括块RAM（BRAM）块列的PLD中，BRAM块被修改以创建专用的逻辑块，包括RAM，处理器和耦合在RAM，处理器和通用互连结构之间的专用接口 PLD。通过增加BRAM块的列的宽度来获得附加区域。因为互连结构几乎保持不变，所以专用逻辑块和相邻的瓦片之间的互连已经就位，并且修改不影响PLD路由软件。在一些实施例中，处理器可以可选地被禁用，对于用户变得透明。其他实施例提供了修改PLD以包括结构并提供上述能力的方法。

3. 发明授权

US07181718B1 Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks 有权
标题翻译：在逻辑块阵列中提供紧密耦合的处理器和RAM块列的结构和方法
公开(公告)号：US07181718B1
公开(公告)日：2007-02-20
申请号：US10928599
申请日：2004-08-27
申请人： Goran Bilski , Ralph D. Wittig , Jennifer Wong , David B. Squires
发明人： Goran Bilski , Ralph D. Wittig , Jennifer Wong , David B. Squires
IPC分类号： G06F17/50
CPC分类号： H03K19/1776 , G06F15/7867 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.
摘要翻译：在现有PLD架构中包含处理器能力的结构和方法，对现有的一般互连结构的影响最小。在包括块RAM（BRAM）块的PLD中，BRAM块被修改以创建专用逻辑块，包括RAM，处理器和耦合在RAM，处理器和一般互连结构之间的专用接口 PLD。通过增加BRAM块的列的宽度来获得附加区域。因为互连结构几乎保持不变，所以专用逻辑块和相邻的瓦片之间的互连已经就位，并且修改不影响PLD路由软件。在一些实施例中，处理器可以可选地被禁用，对于用户变得透明。其他实施例提供了修改PLD以包括结构并提供上述能力的方法。

4. 发明授权

US07340585B1 Method and system for fast linked processor in a system on a chip (SoC) 有权
标题翻译：芯片系统中快速链接处理器的方法与系统（SoC）
公开(公告)号：US07340585B1
公开(公告)日：2008-03-04
申请号：US10229543
申请日：2002-08-27
申请人： Satish R. Ganesan , Goran Bilski , Usha Prabhu , Ralph D. Wittig
发明人： Satish R. Ganesan , Goran Bilski , Usha Prabhu , Ralph D. Wittig
IPC分类号： G06F15/17 , G06F15/80
CPC分类号： G06F15/7867
摘要： A fast linked multiprocessor network (22) including a plurality of processing modules (24, 26, 28, 30, 32, and 34) implemented on a field programmable gate array (10) and a plurality of configurable uni-directional links (21, 23, 25, 27, 29, 31) coupled among at least two of the plurality processing modules providing a streaming communication channel between at least two of the plurality of processing modules.
摘要翻译：一种快速链接多处理器网络（22），包括在现场可编程门阵列（10）上实现的多个处理模块（24,26,28,30,32,34）和多个可配置单向链路（21， 23,25,27,29,31），其耦合到所述多个处理模块中的至少两个处理模块中，以提供所述多个处理模块中的至少两个之间的流传输通信信道。

5. 发明授权

US06477699B1 Electronic circuit designs adaptable for applications having different binary data formats 失效
标题翻译：电子电路设计适用于具有不同二进制数据格式的应用
公开(公告)号：US06477699B1
公开(公告)日：2002-11-05
申请号：US09884559
申请日：2001-06-19
申请人： Goran Bilski
发明人： Goran Bilski
IPC分类号： G06F1750
CPC分类号： B65D81/05 , B65D85/505 , G06F17/5045
摘要： Method for implementing electronic circuit designs that are adaptable to different binary data formats. Separate packages are provided for the different binary data formats. The names of the constants and subtypes are identical as between the packages, and the values associated with the constants and subtypes in each of the packages are particular to the associated data format. A selected one of the packages is imported into the. design, and selected references in the design to binary data are made using the names of the constants and subtypes set forth in the packages. The circuit design is then implemented by synthesizing and mapping the design to the selected device.
摘要翻译：实现适应不同二进制数据格式的电子电路设计的方法。为不同的二进制数据格式提供单独的包。常量和子类型的名称在包之间是相同的，并且与每个包中的常量和子类型相关联的值对于相关联的数据格式是特定的。所选的一个包被导入到。设计和选择的引用在二进制数据的设计中使用在包中列出的常数和子类型的名称。然后通过将设计合成并映射到所选择的设备来实现电路设计。

6. 发明授权

US07490227B1 Method and system to recreate instruction and data traces in an embedded processor 有权
标题翻译：在嵌入式处理器中重新创建指令和数据跟踪的方法和系统
公开(公告)号：US07490227B1
公开(公告)日：2009-02-10
申请号：US10930437
申请日：2004-08-31
申请人： Goran Bilski , Jorge Ernesto Carrillo , Usha Prabhu , Navaneethan Sundaramoorthy
发明人： Goran Bilski , Jorge Ernesto Carrillo , Usha Prabhu , Navaneethan Sundaramoorthy
IPC分类号： G06F11/25
CPC分类号： G06F11/3476
摘要： A method of recreating instructions and data traces in a processor can include the step of fetching an instruction from an executable program in an order corresponding to sequential program counter (PC) values, obtaining a destination register from the fetched instruction and updating the destination register in a data structure with a value from a collected destination register corresponding to the PC value. The steps above can be repeated until all desired PC values and destination values are obtained.
摘要翻译：在处理器中重建指令和数据迹线的方法可以包括以与顺序程序计数器（PC）值相对应的顺序从可执行程序获取指令的步骤，从获取的指令获取目的地寄存器并且更新目的地寄存器具有来自与PC值相对应的收集的目的地寄存器的值的数据结构。可以重复上述步骤，直到获得所有期望的PC值和目标值。

7. 发明授权

US06703862B1 Efficient loadable registers in programmable logic devices 有权
标题翻译：可编程逻辑器件中的高效可加载寄存器
公开(公告)号：US06703862B1
公开(公告)日：2004-03-09
申请号：US10253095
申请日：2002-09-24
申请人： Goran Bilski
发明人： Goran Bilski
IPC分类号： A03K19173
CPC分类号： H03K19/1776
摘要： Efficient register circuits allow the loading of data values into a memory element using set and reset terminals in addition to loading via the data input terminal. A register circuit includes a memory element and a logical AND gate. A load command input terminal enables the load, and a load value input terminal provides the new value to be loaded. The memory element has set and reset terminals. In one embodiment, the reset function overrides the set function when both terminals provide active signals. The set terminal is coupled to the load command input terminal. The logical AND gate has input terminals coupled to the load command and load value input terminals, and an output terminal coupled to the reset terminal of the memory element. In another embodiment, the set function overrides the reset function, and the signals driving the set and reset terminals are reversed.
摘要翻译：有效的寄存器电路允许使用设置和复位端子将数据值加载到存储器元件中，而且通过数据输入端子进行加载。寄存器电路包括存储器元件和逻辑与门。负载指令输入端子使能负载，负载值输入端子提供要加载的新值。存储器元件具有置位和复位端子。在一个实施例中，当两个端子提供有源信号时，复位功能覆盖设定功能。设置端子耦合到负载命令输入端子。逻辑与门具有耦合到负载命令和负载值输入端的输入端，以及耦合到存储元件的复位端的输出端。在另一个实施例中，设定功能覆盖复位功能，驱动设定和复位端子的信号相反。

8. 发明授权

US06476634B1 ALU implementation in single PLD logic cell 失效
标题翻译：单个PLD逻辑单元中的ALU实现
公开(公告)号：US06476634B1
公开(公告)日：2002-11-05
申请号：US10061571
申请日：2002-02-01
申请人： Goran Bilski
发明人： Goran Bilski
IPC分类号： G06F738
CPC分类号： G06F17/5054
摘要： Structures and methods that implement an ALU (Arithmetic Logic Unit) circuit in a PLD (Programmable Logic Device) while using only one PLD logic cell to implement a one-bit ALU circuit. The ALU circuit has two data input signals and two operator input signals that select between the adder, subtractor, and other logical functions. A result bit provides the result of the addition, subtraction, or other logical function as selected by the values of the two operator input signals. A carry chain is provided for combining the one-bit ALU circuits to generate multi-bit ALUs. All of this functionality is implemented in a single PLD logic cell per ALU bit.
摘要翻译：在PLD（可编程逻辑器件）中实现ALU（算术逻辑单元）电路的结构和方法，同时只使用一个PLD逻辑单元来实现一位ALU电路。 ALU电路具有两个数据输入信号和两个操作员输入信号，在加法器，减法器和其他逻辑功能之间进行选择。结果位提供由两个操作员输入信号的值选择的加法，减法或其他逻辑功能的结果。提供进位链用于组合一位ALU电路以产生多位ALU。所有这些功能在每个ALU位的单个PLD逻辑单元中实现。

9. 发明授权

US07676661B1 Method and system for function acceleration using custom instructions 有权
标题翻译：使用定制指令进行功能加速的方法和系统
公开(公告)号：US07676661B1
公开(公告)日：2010-03-09
申请号：US10958962
申请日：2004-10-05
申请人： Sundararajarao Mohan , Satish R. Ganesan , Goran Bilski
发明人： Sundararajarao Mohan , Satish R. Ganesan , Goran Bilski
IPC分类号： G06F7/36 , G06F15/00
CPC分类号： G06F15/7867 , G06F9/30003 , G06F9/30181
摘要： A fast linked multiprocessor network including a plurality of processing modules implemented on a field programmable gate array and a plurality of configurable uni-directional links coupled among at least two of the plurality processing modules provide a streaming communication channel between at least two of the plurality of processing modules. Such configuration provides a function accelerator that can feed at least one processor with data values using one custom instruction to put data values on at least one uni-directional serial link and that can extract data values from at least one processor using one custom instruction to get data values from the at least one uni-directional serial link.
摘要翻译：包括实现在现场可编程门阵列上的多个处理模块和耦合在所述多个处理模块中的至少两个之间的多个可配置单向链路的快速链接多处理器网络在多个处理模块中的至少两个之间提供流传输通信信道处理模块。这种配置提供了一种功能加速器，其可以使用一个自定义指令向至少一个处理器馈送数据值，以将数据值放置在至少一个单向串行链路上，并且可以使用一个定制指令从至少一个处理器中提取数据值以获得来自至少一个单向串行链路的数据值。

10. 发明授权

US07426583B1 Method and circuit for decoding an address of an address space 有权
标题翻译：解码地址空间地址的方法和电路
公开(公告)号：US07426583B1
公开(公告)日：2008-09-16
申请号：US11238431
申请日：2005-09-28
申请人： Paulo L. Dutra , Jorge Ernesto Carrillo , Goran Bilski
发明人： Paulo L. Dutra , Jorge Ernesto Carrillo , Goran Bilski
IPC分类号： G06F3/00 , G06F13/00 , G06F5/00
CPC分类号： G06F12/1081
摘要： Decoding an address in an address space including a plurality of local ranges and a plurality of peripheral ranges is described. Various approaches for decoding an input address include determining decoder address bits of the address space that distinguish local ranges from each other and that distinguish local ranges from peripheral ranges. The local and peripheral ranges are interleaved and have a plurality of sizes. The number of decoder address bits is less than the number of address bits in the address space and less than the number of local ranges plus the number of peripheral ranges. Using the decoder address bits of an input address, it is determined whether the input address is within a portion of the address space that includes one of the local ranges and does not include any of the peripheral ranges nor the local ranges other than the one of the local ranges.
摘要翻译：描述包括多个局部范围和多个外围范围的地址空间中的地址的解码。用于对输入地址进行解码的各种方法包括确定区分本地范围的地址空间的解码器地址位，并且区分本地范围与周边范围。本地和外围范围是交错的并且具有多个尺寸。解码器地址位的数量小于地址空间中的地址位数，小于本地范围的数量以及周边数量。使用输入地址的解码器地址位，确定输入地址是否在包括本地范围之一的地址空间的一部分内，并且不包括任何外围范围和除了当地范围。

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