专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US5542053A Bridge interface between two buses of a computer system with a direct memory access controller programmed by a scatter/gather programmer 失效
标题翻译：计算机系统的两条总线之间的桥接口，具有由分散/集合编程器编程的直接存储器访问控制器
公开(公告)号：US5542053A
公开(公告)日：1996-07-30
申请号：US350184
申请日：1994-11-30
申请人： Patrick M. Bland , Daniel R. Cronin, III , Richard G. Hofmann , Dennis Moeller , Lance M. Venarchick
发明人： Patrick M. Bland , Daniel R. Cronin, III , Richard G. Hofmann , Dennis Moeller , Lance M. Venarchick
IPC分类号： G06F13/40 , H04N7/15 , G06F13/00
CPC分类号： H04N7/152 , G06F13/4027
摘要： A bridge interface for a computer system having an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus is coupled between the ISA and PCI buses. The bridge has a direct memory access (DMA) control circuit programmable by programming signals to perform a DMA transfer, and a scatter/gather unit coupled between the ISA bus and the DMA control circuit. The scatter/gather unit selectively provides the programming signals to the DMA control circuit directly or causes the programming signals to be provided over the ISA bus. Providing the programming signals to the DMA control circuit directly from the programming controller of the scatter/gather unit takes advantage of the location of both the DMA control circuit and the scatter/gather unit on the bridge chip. The program controller is able to program the DMA control circuit with I/O write cycles that take only one 33 MHz clock, instead of a plurality of 8 MHz clocks if the DMA control circuit is programmed with signals sent over the ISA bus. This provides an order of magnitude reduction is the time required to program the DMA control circuit.
摘要翻译：具有工业标准架构（ISA）总线和外围控制器互连（PCI）总线的计算机系统的桥接口耦合在ISA和PCI总线之间。桥接器具有通过编程信号进行DMA传输的可编程的直接存储器存取（DMA）控制电路，以及耦合在ISA总线和DMA控制电路之间的散射/收集单元。散射/收集单元选择性地将编程信号提供给DMA控制电路，或者使编程信号通过ISA总线提供。将编程信号直接从分散/收集单元的编程控制器提供给DMA控制电路，利用了DMA控制电路和散射/聚集单元在桥芯片上的位置。如果DMA控制电路通过ISA总线发送的信号进行编程，则程序控制器能够对仅具有一个33 MHz时钟的I / O写周期来编程DMA控制电路，而不是多个8 MHz时钟。这提供了对DMA控制电路进行编程所需的时间的数量级。

22. 发明授权

US5499346A Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus 失效
标题翻译：用于多总线信息处理系统的总线到总线桥，可优化系统总线和外设总线之间的数据传输
公开(公告)号：US5499346A
公开(公告)日：1996-03-12
申请号：US69230
申请日：1993-05-28
申请人： Nader Amini , Patrick M. Bland , Bechara F. Boury , Robert T. Jackson
发明人： Nader Amini , Patrick M. Bland , Bechara F. Boury , Robert T. Jackson
IPC分类号： G06F11/00 , G06F11/10 , G06F11/30 , G06F13/00 , G06F13/36
CPC分类号： G06F11/10 , G06F11/0793 , G06F11/3027 , G06F11/3055
摘要： An information processing system, comprising a central processing unit (CPU); a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; a second system bus connected to the CPU; a host bridge connecting the second system bus to a peripheral bus having at least one peripheral device attached thereto, the host bridge including register space for storing information related to transactions occurring over the peripheral bus; and error capture logic incorporated into the host bridge. The error capture logic monitors the transactions occurring over the peripheral bus, detects parity errors occurring during any of the transactions, and generates an interrupt routine over the second system bus to the CPU. The CPU reads the register space and performs necessary recovery operations.
摘要翻译：一种信息处理系统，包括中央处理单元（CPU）; 第一系统总线，其将CPU连接到系统存储器，使得CPU可以从系统存储器读取数据和向其写入数据; 连接到CPU的第二系统总线; 将所述第二系统总线连接到具有连接至少一个外围设备的外围总线的主桥，所述主桥包括用于存储与所述外围总线上发生的事务有关的信息的寄存器空间; 并将错误捕获逻辑并入主桥。错误捕获逻辑监视通过外设总线发生的事务，检测在任何事务期间发生的奇偶校验错误，并通过第二个系统总线生成中断程序到CPU。 CPU读取寄存器空间并执行必要的恢复操作。

23. 发明授权

US5446906A Method and apparatus for suspending and resuming a keyboard controller 失效
标题翻译：用于暂停和恢复键盘控制器的方法和装置
公开(公告)号：US5446906A
公开(公告)日：1995-08-29
申请号：US85647
申请日：1993-06-30
申请人： James P. Kardach , Jayesh M. Joshi , Patrick M. Bland , Grant L. Clarke, Jr.
发明人： James P. Kardach , Jayesh M. Joshi , Patrick M. Bland , Grant L. Clarke, Jr.
IPC分类号： G06F21/00 , G06F1/32
CPC分类号： G06F21/83
摘要： A method and mechanism for suspending and resuming a keyboard controller. The present invention includes a method and mechanism for saving the state of an input device, such as a keyboard and/or mouse, such that the power to those devices may be removed. The keyboard controller of the present invention is capable of performing a password security function. The present invention allows the keyboard controller to be suspended and resumed without jeopardizing the password security function.
摘要翻译：一种用于暂停和恢复键盘控制器的方法和机构。本发明包括一种用于保存诸如键盘和/或鼠标的输入设备的状态的方法和机构，使得可以去除对这些设备的电力。本发明的键盘控制器能够执行口令安全功能。本发明允许键盘控制器被暂停和恢复，而不会危及密码安全功能。

24. 发明授权

US5129090A System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration 失效
标题翻译： 80386在80386/82385微处理器系统运行时的系统总线预设
公开(公告)号：US5129090A
公开(公告)日：1992-07-07
申请号：US198895
申请日：1988-05-26
申请人： Patrick M. Bland , Mark E. Dean , Philip E. Milling
发明人： Patrick M. Bland , Mark E. Dean , Philip E. Milling
IPC分类号： G06F13/36 , G06F13/362
CPC分类号： G06F13/36 , G06F13/362
摘要： A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.

25. 发明授权

US5107507A Bidirectional buffer with latch and parity capability 失效
标题翻译：双向缓冲器具有锁定和极性能力
公开(公告)号：US5107507A
公开(公告)日：1992-04-21
申请号：US198961
申请日：1988-05-26
申请人： Patrick M. Bland , Mark E. Dean , Gene J. Gaudenzi , Kevin G. Kramer , Susan L. Tempest
发明人： Patrick M. Bland , Mark E. Dean , Gene J. Gaudenzi , Kevin G. Kramer , Susan L. Tempest
IPC分类号： G06F11/10 , G06F13/38 , G06F13/40 , H03K3/288 , H03K19/082
CPC分类号： G06F11/10 , G06F13/4027 , G06F13/4059 , G06F13/4072 , H03K19/0826 , H03K3/288
摘要： A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent latch and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.

26. 发明申请

US20110080700A1 Airflow Barriers for Efficient Cooling of Memory Modules 有权
标题翻译：用于高效冷却内存模块的气流障碍
公开(公告)号：US20110080700A1
公开(公告)日：2011-04-07
申请号：US12572301
申请日：2009-10-02
申请人： Patrick M. Bland , Vinod Kamath , Jimmy G. Foster, SR. , Ivan R. Zapata
发明人： Patrick M. Bland , Vinod Kamath , Jimmy G. Foster, SR. , Ivan R. Zapata
IPC分类号： G06F1/20
CPC分类号： G06F1/20
摘要： Method and apparatus providing airflow through a chassis including an upstream column of memory modules and a downstream column of memory modules. The airflow is divided into first and second separate airflow streams extending from an upstream end of the upstream column to a downstream end of the downstream column. The first airflow stream is guided into contact with a single memory module operably-installed in the upstream column and to avoid contact with any memory module in the downstream column. The second airflow stream is guided to avoid contact with any memory module in the upstream column and into contact with a single memory module operably-installed in the downstream column. The improved cooling enables the extended use of a single memory module per channel, even though the thermal load on such a memory module is greater. The result is an overall savings of power, since cooling requirements no longer dictate the installation of additional memory modules per channel in order to share and distribute the thermal load.
摘要翻译：提供通过包括存储器模块的上游列和存储器模块的下游列的底盘的气流的方法和装置。气流被分为从上游塔的上游端延伸到下游塔的下游端的第一和第二分开的气流。第一气流引导与可操作地安装在上游塔中的单个存储器模块接触，并且避免与下游塔中的任何存储器模块接触。引导第二气流流以避免与上游塔中的任何存储器模块接触并与可操作地安装在下游塔中的单个存储器模块接触。即使在这样的存储器模块上的热负载较大，改进的冷却也能够每通道扩展使用单个存储器模块。结果是总体上节省了电力，因为冷却要求不再要求每个通道安装额外的内存模块，以便共享和分配热负载。

27. 发明授权

US07694055B2 Directing interrupts to currently idle processors 有权
标题翻译：将中断定向到当前空闲的处理器
公开(公告)号：US07694055B2
公开(公告)日：2010-04-06
申请号：US11251334
申请日：2005-10-15
申请人： Ryuji Orita , Susumu Arai , Brian D. Allison , Patrick M. Bland
发明人： Ryuji Orita , Susumu Arai , Brian D. Allison , Patrick M. Bland
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.
摘要翻译：中断针对当前空闲的处理器。确定当前空闲的计算系统的多个处理器中的哪一个。接收到中断并将其定向到当前空闲处理器之一进行处理。确定哪些处理器当前处于空闲状态可以通过监视每个处理器来确定它是否进入空闲状态。当处理器进入空闲状态时，因此确定处理器当前处于空闲状态。当一个处理器当前处于空闲状态时，一个中断就被指向这个处理器。当多个处理器当前空闲时，选择这些处理器之一来传送中断，例如以循环方式。在没有处理器当前空闲的情况下，选择一个处理器来传送中断。

28. 发明申请

US20090006673A1 DETECTING A PRESENCE OF A DEVICE 审中-公开
标题翻译：检测设备的存在
公开(公告)号：US20090006673A1
公开(公告)日：2009-01-01
申请号：US12206352
申请日：2008-09-08
申请人： Patrick M. Bland , Randoph S. Kolvick
发明人： Patrick M. Bland , Randoph S. Kolvick
IPC分类号： G06F3/00
CPC分类号： G06F13/4068
摘要： Methods and systems are disclosed for detecting a presence of a device that includes providing a clock driver having a pair of differential clock signal lines capable of connection to a device, providing a presence detection signal for transmission through the pair of differential clock signal lines, determining whether the presence detection signal is received through the pair of differential clock signal lines, and identifying the presence of the device if the presence detection signal is received through the pair of differential clock signal lines.
摘要翻译：公开了用于检测设备存在的方法和系统，该设备包括提供具有能够连接到设备的一对差分时钟信号线的时钟驱动器，提供用于通过该对差分时钟信号线传输的存在检测信号，确定通过一对差分时钟信号线是否接收到存在检测信号，以及如果通过一对差分时钟信号线接收到存在检测信号，则识别设备的存在。

29. 发明申请

US20070294561A1 Providing independent clock failover for scalable blade servers 有权
标题翻译：为可扩展的刀片服务器提供独立的时钟故障切换
公开(公告)号：US20070294561A1
公开(公告)日：2007-12-20
申请号：US11434611
申请日：2006-05-16
申请人： Marcus A. Baker , Justin P. Bandholz , Patrick M. Bland , Andrew S. Heinzmann
发明人： Marcus A. Baker , Justin P. Bandholz , Patrick M. Bland , Andrew S. Heinzmann
IPC分类号： G06F11/00
CPC分类号： G06F11/1604 , G06F11/20
摘要： Methods and systems are disclosed for providing independent clock failover for scalable blade servers that include assigning a server blade to one of a plurality of clock failover groups, providing a plurality of independent clock signals to the clock generator of the server blade, wherein one of the plurality of independent clock signals is an active clock signal, detecting a failover condition for the clock failover group assigned to the server blade, and switching the active clock signal, in response to the detected failover condition, from one independent clock signal to another independent clock signal.
摘要翻译：公开了用于为可伸缩刀片服务器提供独立的时钟故障切换的方法和系统，包括将服务器刀片分配给多个时钟故障转移组中的一个，向服务器刀片的时钟发生器提供多个独立的时钟信号，其中，多个独立时钟信号是活动时钟信号，检测分配给服务器刀片的时钟故障切换组的故障转移条件，并响应于检测到的故障转移条件将活动时钟信号从一个独立时钟信号切换到另一独立时钟信号。

30. 发明授权

US06330656B1 PCI slot control apparatus with dynamic configuration for partitioned systems 失效
标题翻译：用于分区系统的具有动态配置的PCI插槽控制装置
公开(公告)号：US06330656B1
公开(公告)日：2001-12-11
申请号：US09283363
申请日：1999-03-31
申请人： Richard Bealkowski , Patrick M. Bland
发明人： Richard Bealkowski , Patrick M. Bland
IPC分类号： G06F1314
CPC分类号： G06F9/5077
摘要： A system for partitioning and allocating individual PCI slots within a Primary Host Bridge (PHB) in a partitioned computer system is provided. An innovative PHB system is included which allows a PCI slot to be dynamically assigned to one or more partitions at a given time, allowing for more efficient allocation of system resources.
摘要翻译：提供了一种用于在分区计算机系统中的主主机桥（PHB）内划分和分配各个PCI时隙的系统。包括创新的PHB系统，允许在给定时间将PCI插槽动态分配给一个或多个分区，从而更有效地分配系统资源。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式