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1. 发明授权

US08103884B2 Managing power consumption of a computer 有权
标题翻译：管理电脑的功耗
公开(公告)号：US08103884B2
公开(公告)日：2012-01-24
申请号：US12146085
申请日：2008-06-25
申请人： Thomas M. Brey , Wesley M. Felter , Sumeet Kochar , Charles R. Lefurgy , Ryuji Orita , Freeman L. Rawson, III , Malcolm S. Ware
发明人： Thomas M. Brey , Wesley M. Felter , Sumeet Kochar , Charles R. Lefurgy , Ryuji Orita , Freeman L. Rawson, III , Malcolm S. Ware
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/206 , Y02D10/16
摘要： Methods and products for managing power consumption of a computer and computers for which power consumption is managed. The computer includes the computer including a computer processor and embodiments of the present invention include providing, by an in-band power manger to an out-of-band power manager, a proposed performance state (‘p-state’) for the computer processor; determining, by the out-of-band power manager, in dependence upon a power setpoint and currently-measured operating metrics of the computer processor, whether to approve the proposed p-state; and if the out-of-band power manager approves the proposed p-state, setting operating parameters of the computer processor according to the approved p-state.
摘要翻译：用于管理计算机和功耗管理的计算机的功耗的方法和产品。计算机包括包括计算机处理器的计算机，并且本发明的实施例包括通过带内功率管理器向带外功率管理器提供用于计算机处理器的建议的性能状态（“p状态”） ; 由带外功率管理器根据功率设定点和计算机处理器的当前测量的操作度量来确定是否批准所提出的p状态; 并且如果带外功率管理器批准所提出的p状态，则根据批准的p状态来设置计算机处理器的操作参数。

2. 发明申请

US20110161736A1 Debugging module to load error decoding logic from firmware and to execute logic in response to an error 有权
标题翻译：调试模块从固件加载错误解码逻辑，并响应错误执行逻辑
公开(公告)号：US20110161736A1
公开(公告)日：2011-06-30
申请号：US12647828
申请日：2009-12-28
申请人： Ryuji Orita , Barry A. Kritt , Charles D. Bauman , Sumeet Kochar , Jeremy K. Holland , Karen A. Taylor
发明人： Ryuji Orita , Barry A. Kritt , Charles D. Bauman , Sumeet Kochar , Jeremy K. Holland , Karen A. Taylor
IPC分类号： G06F11/07 , G06F9/44
CPC分类号： G06F11/0793
摘要： A computing device includes a processor, firmware, a hardware component, and a debugging module. The firmware stores error decoding logic particular to the computing device. The hardware component detects an error in the computing device, and responsively issues an interrupt and halts the processor such that the processor cannot execute any more computer-readable code. The debugging module loads the logic from the firmware at reset and executes the logic responsive to the interrupt. The debugging module does not use the processor to execute the logic, the firmware is not part of the debugging module, and the debugging module is not part of the hardware component. The firmware may also store a mapping between registers of the hardware component and field-replaceable hardware units of the computing device, which the debugging module loads at reset and uses when executing the error decoding logic to determine which unit has caused the error.
摘要翻译：计算设备包括处理器，固件，硬件组件和调试模块。固件存储特定于计算设备的错误解码逻辑。硬件组件检测计算设备中的错误，并且响应地发出中断并停止处理器，使得处理器不能执行任何更多的计算机可读代码。调试模块在复位时从固件加载逻辑，并响应中断执行逻辑。调试模块不使用处理器执行逻辑，固件不是调试模块的一部分，调试模块不是硬件组件的一部分。固件还可以存储硬件组件的寄存器和计算设备的现场可替换硬件单元之间的映射，调试模块在执行错误解码逻辑以确定哪个单元已经引起错误时在复位时加载并使用。

3. 发明授权

US07447934B2 System and method for using hot plug configuration for PCI error recovery 失效
标题翻译：使用热插拔配置进行PCI错误恢复的系统和方法
公开(公告)号：US07447934B2
公开(公告)日：2008-11-04
申请号：US11168145
申请日：2005-06-27
申请人： Shiva R. Dasari , Sudhir Dhawan , Ryuji Orita , Wingcheung T. Tam
发明人： Shiva R. Dasari , Sudhir Dhawan , Ryuji Orita , Wingcheung T. Tam
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0745
摘要： A method, system, and program product for recovering from a bus error in a computer system having a hot plug interface. In accordance with the method of the present invention, an operating system transparent interrupt, such as a system management interrupt, is generated in response to a bus error. Responsive to the operating system transparent interrupt, the hot pluggable bus is scanned and a device associated with the error is identified by an interrupt handler invoked by the interrupt. Finally, a hot plug configuration manager, such as an advanced configuration and power interface is utilized to remove the identified device from system operations without having to restart the system.
摘要翻译：一种用于从具有热插拔接口的计算机系统中的总线错误中恢复的方法，系统和程序产品。根据本发明的方法，响应总线错误产生诸如系统管理中断的操作系统透明中断。响应于操作系统透明中断，热插拔总线被扫描，并且与该错误相关联的设备由中断调用的中断处理程序识别。最后，使用诸如高级配置和电源接口之类的热插拔配置管理器来将所识别的设备从系统操作中移除，而不必重新启动系统。

4. 发明申请

US20070088888A1 Directing interrupts to currently idle processors 有权
标题翻译：将中断定向到当前空闲的处理器
公开(公告)号：US20070088888A1
公开(公告)日：2007-04-19
申请号：US11251334
申请日：2005-10-15
申请人： Ryuji Orita , Susumu Arai , Brian Allison , Patrick Bland
发明人： Ryuji Orita , Susumu Arai , Brian Allison , Patrick Bland
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.
摘要翻译：中断针对当前空闲的处理器。确定当前空闲的计算系统的多个处理器中的哪一个。接收到中断并将其定向到当前空闲处理器之一进行处理。确定哪些处理器当前处于空闲状态可以通过监视每个处理器来确定它是否进入空闲状态。当处理器进入空闲状态时，因此确定处理器当前处于空闲状态。当一个处理器当前处于空闲状态时，一个中断就被指向这个处理器。当多个处理器当前空闲时，选择这些处理器之一来传送中断，例如以循环方式。在没有处理器当前空闲的情况下，选择一个处理器来传送中断。

5. 发明申请

US20070011500A1 System and method for using hot plug configuration for PCI error recovery 失效
标题翻译：使用热插拔配置进行PCI错误恢复的系统和方法
公开(公告)号：US20070011500A1
公开(公告)日：2007-01-11
申请号：US11168145
申请日：2005-06-27
申请人： Shiva Dasari , Sudhir Dhawan , Ryuji Orita , Wingcheung Tam
发明人： Shiva Dasari , Sudhir Dhawan , Ryuji Orita , Wingcheung Tam
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0745
摘要： A method, system, and program product for recovering from a bus error in a computer system having a hot plug interface. In accordance with the method of the present invention, an operating system transparent interrupt, such as a system management interrupt, is generated in response to a bus error. Responsive to the operating system transparent interrupt, the hot pluggable bus is scanned and a device associated with the error is identified by an interrupt handler invoked by the interrupt. Finally, a hot plug configuration manager, such as an advanced configuration and power interface is utilized to remove the identified device from system operations without having to restart the system.
摘要翻译：一种用于从具有热插拔接口的计算机系统中的总线错误中恢复的方法，系统和程序产品。根据本发明的方法，响应总线错误产生诸如系统管理中断的操作系统透明中断。响应于操作系统透明中断，热插拔总线被扫描，并且与该错误相关联的设备由中断调用的中断处理程序识别。最后，使用诸如高级配置和电源接口之类的热插拔配置管理器来将所识别的设备从系统操作中移除，而不必重新启动系统。

6. 发明申请

US20120284540A1 Managing Power Consumption Of A Computer 失效
标题翻译：管理计算机的功耗
公开(公告)号：US20120284540A1
公开(公告)日：2012-11-08
申请号：US13546090
申请日：2012-07-11
申请人： Thomas M. Brey , Wesley M. Felter , Sumeet Kochar , Charles R. Lefurgy , Ryuji Orita , Freeman L. Rawson, III , Malcom S. Ware
发明人： Thomas M. Brey , Wesley M. Felter , Sumeet Kochar , Charles R. Lefurgy , Ryuji Orita , Freeman L. Rawson, III , Malcom S. Ware
IPC分类号： G06F1/26
CPC分类号： G06F1/3203
摘要： Methods, computers, and products for managing power consumption of a computer, the computer including a computer processor and managing power consumption of a computer includes: dynamically during operation of the computer, setting, by an in-band power manager in dependence upon performance metrics of the computer processor, a current performance state (‘p-state’) of the computer processor; and providing, by the in-band power manager to an out-of-band power manager, the current p-state of the computer processor.
摘要翻译：用于管理计算机的功耗的方法，计算机和产品，包括计算机处理器的计算机和管理计算机的功耗的方法，计算机和产品包括：在计算机运行期间动态地根据性能度量由带内功率管理器进行设置计算机处理器的当前性能状态（p状态）; 以及由所述带内功率管理器向所述带外功率管理器提供所述计算机处理器的当前p状态。

7. 发明授权

US07694055B2 Directing interrupts to currently idle processors 有权
标题翻译：将中断定向到当前空闲的处理器
公开(公告)号：US07694055B2
公开(公告)日：2010-04-06
申请号：US11251334
申请日：2005-10-15
申请人： Ryuji Orita , Susumu Arai , Brian D. Allison , Patrick M. Bland
发明人： Ryuji Orita , Susumu Arai , Brian D. Allison , Patrick M. Bland
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Interrupts are directed to currently idle processors. Which of a number of processors of a computing system that are currently idle is determined. An interrupt is received and directed to one of the currently idle processors for processing. Determining which processors are currently idle can be accomplished by monitoring each processor to determine whether it has entered an idle state. When a processor has entered an idle state, it is thus determined that the processor is currently idle. Where just one processor is currently idle, an interrupt is directed to this processor. Where more than one processor is currently idle, one of these processors is selected to which to deliver an interrupt, such as in a round-robin manner. Where no processor is currently idle, then one of the processors is selected to which to deliver an interrupt.
摘要翻译：中断针对当前空闲的处理器。确定当前空闲的计算系统的多个处理器中的哪一个。接收到中断并将其定向到当前空闲处理器之一进行处理。确定哪些处理器当前处于空闲状态可以通过监视每个处理器来确定它是否进入空闲状态。当处理器进入空闲状态时，因此确定处理器当前处于空闲状态。当一个处理器当前处于空闲状态时，一个中断就被指向这个处理器。当多个处理器当前空闲时，选择这些处理器之一来传送中断，例如以循环方式。在没有处理器当前空闲的情况下，选择一个处理器来传送中断。

8. 发明申请

US20100064080A1 MANAGING PCI-EXPRESS MAX PAYLOAD SIZE FOR LEGACY OPERATING SYSTEMS 审中-公开
标题翻译：管理用于LEGACY操作系统的PCI-EXPRESS MAX PAYLOAD SIZE
公开(公告)号：US20100064080A1
公开(公告)日：2010-03-11
申请号：US12208640
申请日：2008-09-11
申请人： Mehul Shah , Ryuji Orita , Sandra D. Rhodes
发明人： Mehul Shah , Ryuji Orita , Sandra D. Rhodes
IPC分类号： G06F13/42
CPC分类号： G06F13/4221
摘要： The present disclosure is directed to a method for balancing latency versus bandwidth trade-offs in packet transmission utilizing PCI-Express. The method may comprise identifying at least one system element along a path of a packet to be transmitted; determining and storing an optimum payload size for each one of the at least one system element; configuring a Max Payload Size parameter for each one of the at least one system element, wherein the Max Payload Size parameter is configured based on the optimum payload size for each one of the at least one system element.
摘要翻译：本公开涉及一种利用PCI-Express在分组传输中平衡等待时间与带宽折衷的方法。该方法可以包括沿着待发送的分组的路径识别至少一个系统元件; 确定和存储所述至少一个系统元件中的每一个的最佳有效载荷大小; 为所述至少一个系统元件中的每个系统元件配置最大有效载荷大小参数，其中所述最大有效载荷大小参数基于所述至少一个系统元件中的每个系统元件的最佳有效载荷大小来配置。

9. 发明授权

US08504875B2 Debugging module to load error decoding logic from firmware and to execute logic in response to an error 有权
标题翻译：调试模块从固件加载错误解码逻辑，并响应错误执行逻辑
公开(公告)号：US08504875B2
公开(公告)日：2013-08-06
申请号：US12647828
申请日：2009-12-28
申请人： Ryuji Orita , Barry A. Kritt , Charles D. Bauman , Sumeet Kochar , Jeremy K. Holland , Karen A. Taylor
发明人： Ryuji Orita , Barry A. Kritt , Charles D. Bauman , Sumeet Kochar , Jeremy K. Holland , Karen A. Taylor
IPC分类号： G06F11/00
CPC分类号： G06F11/0793
摘要： A computing device includes a processor, firmware, a hardware component, and a debugging module. The firmware stores error decoding logic particular to the computing device. The hardware component detects an error in the computing device, and responsively issues an interrupt and halts the processor such that the processor cannot execute any more computer-readable code. The debugging module loads the logic from the firmware at reset and executes the logic responsive to the interrupt. The debugging module does not use the processor to execute the logic, the firmware is not part of the debugging module, and the debugging module is not part of the hardware component. The firmware may also store a mapping between registers of the hardware component and field-replaceable hardware units of the computing device, which the debugging module loads at reset and uses when executing the error decoding logic to determine which unit has caused the error.
摘要翻译：计算设备包括处理器，固件，硬件组件和调试模块。固件存储特定于计算设备的错误解码逻辑。硬件组件检测计算设备中的错误，并且响应地发出中断并停止处理器，使得处理器不能执行任何更多的计算机可读代码。调试模块在复位时从固件加载逻辑，并响应中断执行逻辑。调试模块不使用处理器执行逻辑，固件不是调试模块的一部分，调试模块不是硬件组件的一部分。固件还可以存储硬件组件的寄存器和计算设备的现场可替换硬件单元之间的映射，调试模块在执行错误解码逻辑以确定哪个单元已经引起错误时在复位时加载并使用。

10. 发明申请

US20090113194A1 Persisting value relevant to debugging of computer system during reset of computer system 有权
标题翻译：计算机系统复位期间与计算机系统调试相关的持久价值
公开(公告)号：US20090113194A1
公开(公告)日：2009-04-30
申请号：US11926083
申请日：2007-10-28
申请人： Ryuji Orita , Mark A. Brandyberry , Mehul M. Shah , Sean P. Brogan
发明人： Ryuji Orita , Mark A. Brandyberry , Mehul M. Shah , Sean P. Brogan
IPC分类号： G06F15/177
CPC分类号： G06F11/1417 , G06F11/0787
摘要： The last value of an element of a computing system is continually stored within a first register. The element is cleared during any restart or reset of the computing system. The last value is relevant to debugging of the computing system when the computing system fails to perform as expected and/or as desired. Upon receiving an instruction to reset the computing system via a first reset signal corresponding to pressing of a reset button or a second reset signal corresponding to a baseboard management controller issuing a reset command, the last value of the element as stored within the first register is copied to a second register. The computing system is then reset. The last value of the element as stored within the second register persists within the second register during this type of reset, but is cleared during any other reset or restart of the computing system.
摘要翻译：计算系统的元素的最后一个值被连续地存储在第一寄存器中。该元素在计算系统的任何重新启动或重置期间被清除。最后一个值与计算系统在计算系统按预期和/或需要时无法执行的调试相关。当接收到通过对应于复位按钮的按下的第一复位信号或对应于发出复位命令的基板管理控制器的第二复位信号来重置计算系统的指令时，存储在第一寄存器内的元件的最后值是复制到第二个寄存器。然后重新计算系统。在这种类型的复位期间，存储在第二寄存器内的元素的最后一个值在第二个寄存器内仍然存在，但在计算系统的任何其他复位或重新启动期间都将被清除。

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