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1. 发明授权

US5129090A System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration 失效
标题翻译： 80386在80386/82385微处理器系统运行时的系统总线预设
公开(公告)号：US5129090A
公开(公告)日：1992-07-07
申请号：US198895
申请日：1988-05-26
申请人： Patrick M. Bland , Mark E. Dean , Philip E. Milling
发明人： Patrick M. Bland , Mark E. Dean , Philip E. Milling
IPC分类号： G06F13/36 , G06F13/362
CPC分类号： G06F13/36 , G06F13/362
摘要： A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination of the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state of an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation of the arbitration phase by immediately accessing the system bus.

2. 发明授权

US5182809A Dual bus microcomputer system with programmable control of lock function 失效
标题翻译：具有可编程锁定功能的双总线微型计算机系统
公开(公告)号：US5182809A
公开(公告)日：1993-01-26
申请号：US358810
申请日：1989-05-31
申请人： Ralph M. Begun , Patrick M. Bland , Philip E. Milling
发明人： Ralph M. Begun , Patrick M. Bland , Philip E. Milling
IPC分类号： G06F12/08
CPC分类号： G06F12/0888
摘要： A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

3. 发明授权

US5045998A Method and apparatus for selectively posting write cycles using the 82385 cache controller 失效
标题翻译：使用82385高速缓存控制器选择性地发布写周期的方法和装置
公开(公告)号：US5045998A
公开(公告)日：1991-09-03
申请号：US359794
申请日：1989-06-01
申请人： Ralph M. Begun , Patrick M. Bland , Mark E. Dean
发明人： Ralph M. Begun , Patrick M. Bland , Mark E. Dean
IPC分类号： G06F12/08
CPC分类号： G06F12/0888
摘要： A microprocessor system employing an 80386 CPU and an 82385 cache controller has the capability of functioning with dynamic bus sizing (where the CPU interacts with devices which may or may not be 32-bits wide), as well as posted write capability. Unfortunately, the two capabilities have the possibility of an incompatibility if a write cycle is posted to a device which cannot transfer 32 bits on a single cycle. The present invention provides logic to overcome this incompatibility. An address decoder is provided to decode the tag portion of an address asserted on a CPU bus to determine if the asserted address is inside or outside a range of addresses which define cacheable devices. Any cacheable device is by definition 32 bits wide and therefore posted writes are allowed only to cacheable devices. Accordingly, the microcomputer system employing the invention posts write cycles to cacheable devices; write cycles to non-cacheable devices are inhibited from being posted.
摘要翻译：采用80386 CPU和82385高速缓存控制器的微处理器系统具有动态总线大小调整功能（CPU与可能或不是32位宽的设备交互）以及发布的写入功能。不幸的是，如果将写周期发布到在单个周期内不能传输32位的器件，则这两个功能具有不兼容的可能性。本发明提供了克服这种不兼容性的逻辑。提供地址解码器来解码在CPU总线上断言的地址的标签部分，以确定所断言的地址是否在限定可高速缓存设备的地址范围之内或之外。任何可缓存设备的定义为32位宽，因此发布的写入仅允许可缓存设备。因此，采用本发明的微计算机系统将写入周期写入可高速缓存的设备; 对不可缓存设备的写周期被禁止发布。

4. 发明授权

US5107507A Bidirectional buffer with latch and parity capability 失效
标题翻译：双向缓冲器具有锁定和极性能力
公开(公告)号：US5107507A
公开(公告)日：1992-04-21
申请号：US198961
申请日：1988-05-26
申请人： Patrick M. Bland , Mark E. Dean , Gene J. Gaudenzi , Kevin G. Kramer , Susan L. Tempest
发明人： Patrick M. Bland , Mark E. Dean , Gene J. Gaudenzi , Kevin G. Kramer , Susan L. Tempest
IPC分类号： G06F11/10 , G06F13/38 , G06F13/40 , H03K3/288 , H03K19/082
CPC分类号： G06F11/10 , G06F13/4027 , G06F13/4059 , G06F13/4072 , H03K19/0826 , H03K3/288
摘要： A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent latch and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.

5. 发明授权

US5170481A Microprocessor hold and lock circuitry 失效
标题翻译：微处理器保持和锁定电路
公开(公告)号：US5170481A
公开(公告)日：1992-12-08
申请号：US367828
申请日：1989-06-19
申请人： Ralph M. Begun , Patrick M. Bland , Mark E. Dean
发明人： Ralph M. Begun , Patrick M. Bland , Mark E. Dean
IPC分类号： G06F13/36 , G06F13/28 , G06F13/362
CPC分类号： G06F13/285 , G06F13/362
摘要： A logic circit external to a microprocessor monitors selected processor I/O pins to determine the current processor cycle and, in response to a hold request signal, drives the processor into a hold state at the appropriate time in the cycle. The logic circuit also includes a "lockbus" feature that, when the processor is not idle, "locks" the microprocessor to the local CPU bus for a predetermined period of time immediately after the processor is released from a hold state.

6. 发明授权

US5034917A Computer system including a page mode memory with decreased access time and method of operation thereof 失效
标题翻译：计算机系统包括具有减少访问时间的页面模式存储器及其操作方法
公开(公告)号：US5034917A
公开(公告)日：1991-07-23
申请号：US196721
申请日：1988-05-26
申请人： Patrick M. Bland , Mark E. Dean
发明人： Patrick M. Bland , Mark E. Dean
IPC分类号： G11C11/401 , G11C7/10
CPC分类号： G11C7/1021
摘要： A computer system is provided in which memory access time is substantially reduced. After row address strobe (RAS) and column address strobe (CAS) signals are used to select a particular address in a memory during a first memory cycle, the addressed data is latched for later transfer to a data bus. A CAS precharge of the memory is then conducted after such latching and prior to the end of the first memory cycle before the commencement of the second memory cycle.

7. 发明授权

US5450559A Microcomputer system employing address offset mechanism to increase the supported cache memory capacity 失效
标题翻译：微机系统采用地址偏移机制来增加支持的缓存容量
公开(公告)号：US5450559A
公开(公告)日：1995-09-12
申请号：US771528
申请日：1991-10-07
申请人： Ralph M. Begun , Patrick M. Bland , Mark E. Dean
发明人： Ralph M. Begun , Patrick M. Bland , Mark E. Dean
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0886 , G06F12/0806
摘要： The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.
摘要翻译：通过抵消CPU地址输出端子和高速缓存控制器的地址输入端子之间的关系并相应地使高速缓存行大小加倍，可以增加由高速缓存控制器支持的高速缓冲存储器的容量。在某些情况下，额外的逻辑会产生一个隐藏的内存周期，以便从内存中获取等于新行大小的字节数，而不管数据总线的宽度。隐藏的存储器周期由读取未命中发起，并且进一步的逻辑产生不由CPU产生的存储器地址。通过禁止READY信号的改变直到完成正常的存储器周期和隐藏的存储器周期，隐藏的存储器周期对于CPU和高速缓存控制器是保持透明的。

8. 发明授权

US5327545A Data processing apparatus for selectively posting write cycles using the 82385 cache controller 失效
标题翻译：使用82385高速缓存控制器选择性地发布写周期的数据处理装置
公开(公告)号：US5327545A
公开(公告)日：1994-07-05
申请号：US696809
申请日：1991-05-07
申请人： Ralph M. Begun , Patrick M. Bland , Mark E. Dean
发明人： Ralph M. Begun , Patrick M. Bland , Mark E. Dean
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0888
摘要： A microcomputer system employing an 80386 CPU and an 82385 cache controller has the capability of functioning with dynamic bus sizing (where the CPU interacts with devices which may or may not be 32-bits wide), as well as posted write capability. Unfortunately, the two capabilities have the possibility of an incompatibility if a write cycle is posted to a device which cannot transfer 32 bits on a single cycle. The present invention provides logic to overcome this incompatibility. An address decoder is provided to decode the tag portion of an address asserted on a CPU local bus to determine if the asserted address is inside or outside a range of addresses which define cacheable devices. Any cacheable device is by definition 32 bits wide and therefore posted writes are allowed only to cacheable devices. Accordingly, the microcomputer system employing the invention posts write cycles to cacheable devices; write cycles to non-cacheable devices are inhibited from being posted.
摘要翻译：使用80386 CPU和82385高速缓存控制器的微机系统具有动态总线大小调整功能（CPU与可能或不是32位宽的设备交互）以及发布的写入功能。不幸的是，如果将写周期发布到在单个周期内不能传输32位的器件，则这两个功能具有不兼容的可能性。本发明提供了克服这种不兼容性的逻辑。提供地址解码器来解码在CPU本地总线上断言的地址的标签部分，以确定断言的地址是否在限定可高速缓存设备的地址范围之内或之外。任何可缓存设备的定义为32位宽，因此发布的写入仅允许可缓存设备。因此，采用本发明的微计算机系统将写入周期写入可高速缓存的设备; 对不可缓存设备的写周期被禁止发布。

9. 发明授权

US5175826A Delayed cache write enable circuit for a dual bus microcomputer system with an 80386 and 82385 失效
标题翻译：具有80386和82385的双总线微型计算机系统延迟缓存写入电路
公开(公告)号：US5175826A
公开(公告)日：1992-12-29
申请号：US198890
申请日：1988-05-26
申请人： Ralph M. Begun , Patrick M. Bland , Mark E. Dean
发明人： Ralph M. Begun , Patrick M. Bland , Mark E. Dean
IPC分类号： G06F12/08
CPC分类号： G06F12/0802
摘要： In an 80386/82385 microcomputer system, the timing requirements placed on non-cache memory components by the 82385 are more stringent than the timing requirements placed on the non-cache memory components by the 80386. The present invention operates on the 82385 cache write enable (CWE) signals, and delays those signals in the event of a read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

10. 发明授权

US5125084A Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller 失效
标题翻译：使用80386处理器和82385缓存控制器实现动态总线尺寸的微型计算机系统中的管道操作控制
公开(公告)号：US5125084A
公开(公告)日：1992-06-23
申请号：US198894
申请日：1988-05-26
申请人： Ralph M. Begun , Patrick M. Bland , Mark E. Dean
发明人： Ralph M. Begun , Patrick M. Bland , Mark E. Dean
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3802 , G06F12/0888
摘要： Any incompatibility between pipelined operations (such as is available in the 80386) and dynamic bus sizing (allowing the processor to operate with devices of 8-, 16- and 32-bit sizes) is accommodated by use of an address decoder and ensuring that device addresses for cacheable devices are in a first predetermined range and any device addresses for non-cacheable devices are not in that predetermined range. Since by definition cacheable devices are 32-bit devices, pipelined operation is allowed only if the address decoder indicates the access is to a cacheable device. In that event, a next address signal is provided to the 80386. This allows the 80386 to proceed to a following cycle prior to completion of the previous cycle. For accesses which are to devices whose address indicate they are non-cacheable, a next address signal is withheld until the cycle is completed, i.e. without pipelining. The invention further provides for proper interface between a DMA mechanism (driven by a first clock) and a CPU local bus subsystem (driven by an entirely different clock). Data provided by the DMA mechanism is latched into an interface between the CPU local bus and the system bus, and a DMA cycle completed. Only after completion of the DMA cycle is detected, is the cycle on the CPU local bus allowed to complete. In this fashion, the CPU can go on to a following operation and be assured that the DMA mechanism is no longer driving the system bus.

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