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21. 发明申请

US20120012970A1 CAPACITOR DEVICE USING AN ISOLATED WELL AND METHOD THEREFOR 有权
标题翻译：使用分离井的电容器件及其方法
公开(公告)号：US20120012970A1
公开(公告)日：2012-01-19
申请号：US12835900
申请日：2010-07-14
申请人： HONGZHONG XU , ZHIHONG ZHANG , JIANG-KAI ZUO
发明人： HONGZHONG XU , ZHIHONG ZHANG , JIANG-KAI ZUO
IPC分类号： H01L27/07 , H01L21/02 , H01L29/06
CPC分类号： H01L29/94 , H01L29/66181
摘要： A semiconductor device includes an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device; a capacitor dielectric on the isolated p-type well; a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device; a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode; a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, wherein a portion of the isolated p-type well between the first and second p-type contact regions is under the p-type polysilicon electrode and the capacitor dielectric; and an n-type isolation region surrounding the isolated p-type well. This device may be conveniently coupled to a fringe capacitor.
摘要翻译：半导体器件包括隔离的p型阱，其中隔离的p型阱是电容器器件的第一电极; 隔离p型阱上的电容器电介质; 电容器电介质上的p型多晶硅电极，其中p型多晶硅电极是电容器器件的第二电极; 分离的p型阱中的第一p型接触区，从p型多晶硅电极的第一侧壁横向延伸; 在隔离的p型阱中的第二p型接触区域，从p型多晶硅电极的第二侧壁横向延伸，与p型多晶硅电极的第一侧壁相对，其中一部分隔离的p型第一和第二p型接触区之间的阱在p型多晶硅电极和电容器电介质之下; 以及围绕隔离p型阱的n型隔离区。该装置可以方便地连接到边缘电容器。

22. 发明申请

US20110169078A1 SWITCH MODE CONVERTER EMPLOYING DUAL GATE MOS TRANSISTOR 有权
标题翻译：使用双栅极MOS晶体管的开关模式转换器
公开(公告)号：US20110169078A1
公开(公告)日：2011-07-14
申请号：US13069158
申请日：2011-03-22
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78
CPC分类号： H01L27/0705 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/41775 , H01L29/66659 , H01L29/7831 , H01L29/7835
摘要： A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions.
摘要翻译：适用于可以以超过例如5MHz或更大的开关频率工作的开关模式转换器的公开的功率晶体管包括覆盖在半导体衬底的上表面上的栅极电介质层和覆盖的半导体衬底的第一和第二栅电极栅介质层。第一栅电极横向定位成覆盖在衬底的第一区域上。第一衬底区域具有第一类型的掺杂，其可以是n型或p型。功率晶体管的第二栅电极覆盖栅极电介质，并且横向地位于衬底的第二区域上方。第二衬底区域具有与第一类型不同的第二掺杂类型。晶体管还包括位于衬底内的漂移区域，该漂移区域紧邻衬底的上表面并横向地位于第一和第二衬底区域之间。

23. 发明申请

US20100301403A1 SEMICONDUCTOR DEVICE WITH MULTIPLE GATES AND DOPED REGIONS AND METHOD OF FORMING 有权
标题翻译：具有多个门和多个区域的半导体器件及其形成方法
公开(公告)号：US20100301403A1
公开(公告)日：2010-12-02
申请号：US12475232
申请日：2009-05-29
申请人： WON GI MIN , John L. Huber , Jiang-Kai Zuo
发明人： WON GI MIN , John L. Huber , Jiang-Kai Zuo
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/0619 , H01L29/0696 , H01L29/404
摘要： A semiconductor device includes a source region within a semiconductor substrate, a drain region within the semiconductor substrate, a control gate over the semiconductor substrate and between the source region and the drain region, a first gate between the control gate and the drain region, and a first doped region within the semiconductor region and between the control gate and the first gate. The method of forming the semiconductor device may include depositing an electrode material over the semiconductor substrate, patterning the electrode material to form a control gate and a first gate, implanting a first doped region within the semiconductor substrate between the control gate and the first gate while using the control gate and the first gate as a mask, and implanting a source region within the semiconductor substrate.
摘要翻译：半导体器件包括半导体衬底内的源极区域，半导体衬底内的漏极区域，半导体衬底上的控制栅极以及源极区域和漏极区域之间的控制栅极，控制栅极和漏极区域之间的第一栅极，以及半导体区域内和控制栅极与第一栅极之间的第一掺杂区域。形成半导体器件的方法可以包括在半导体衬底上沉积电极材料，图案化电极材料以形成控制栅极和第一栅极，在控制栅极和第一栅极之间注入半导体衬底内的第一掺杂区域，同时使用控制栅极和第一栅极作为掩模，并且在半导体衬底内注入源极区域。

24. 发明授权

US07795702B2 Microelectronic assemblies with improved isolation voltage performance 有权
标题翻译：具有提高隔离电压性能的微电子组件
公开(公告)号：US07795702B2
公开(公告)日：2010-09-14
申请号：US12717522
申请日：2010-03-04
申请人： Won Gi Min , Veronique C. Macary , Jiang-Kai Zuo
发明人： Won Gi Min , Veronique C. Macary , Jiang-Kai Zuo
IPC分类号： H01L29/00
CPC分类号： H01L21/761 , H01L21/823481 , H01L21/823493
摘要： Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below the first and second semiconductor devices with a gap therebetween. At least one well region is formed over the substrate and between the first and second semiconductor devices. A barrier region having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.
摘要翻译：提供了微电子组件的实施例。第一和第二半导体器件形成在具有第一浓度的第一掺杂剂类型的衬底上。具有第二掺杂剂类型的第一和第二掩埋区分别形成在第一和第二半导体器件的下面，其间具有间隙。至少一个阱区形成在衬底上并且在第一和第二半导体器件之间。具有第二浓度的第一掺杂剂类型的屏障区域形成在第一和第二掩埋区域之间并且与第一和第二掩埋区域相邻，使得至少一部分阻挡区域从第一和第二半导体器件的深度延伸大于或等于埋藏区域的深度。

25. 发明授权

US07776700B2 LDMOS device and method 有权
标题翻译： LDMOS设备和方法
公开(公告)号：US07776700B2
公开(公告)日：2010-08-17
申请号：US11650188
申请日：2007-01-04
申请人： Hongning Yang , Veronique C. Macary , Jiang-Kai Zuo
发明人： Hongning Yang , Veronique C. Macary , Jiang-Kai Zuo
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L21/26586 , H01L21/7624 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/66659 , H01L29/7835
摘要： An N-channel device (40, 60) is described having a very lightly doped substrate (42) in which spaced-apart P (46) and N (44) wells are provided, whose lateral edges (461, 45) extending to the surface (47). The gate (56) overlies the surface (47) between the P (46) and N (44) wells. The P-well edge (461) adjacent the source (50) is substantially aligned with the left gate edge (561). The N-well edge (45) lies at or within the right gate edge (562), which is spaced a first distance (471) from the drain (48). The N-well (44) desirably includes a heavier doped region (62) in ohmic contact with the drain (48) and with its left edge (621) located about half way between the right gate edge (562) and the drain (48). A HALO implant pocket (52) is provided underlying the left gate edge (561) using the gate (56) as a mask. The resulting device (40, 60) operates at higher voltage with lower Rdson, less HCI and very low off-state leakage. P and N dopants are interchanged to provide P-channel devices.
摘要翻译：描述了具有非常轻掺杂的衬底（42）的N沟道器件（40,60），其中设置有间隔开的P（46）和N（44）阱，其侧边缘（461,45）延伸到表面（47）。栅极（56）覆盖在P（46）和N（44）孔之间的表面（47）上。与源极（50）相邻的P阱边缘（461）基本上与左边缘边缘（561）对准。所述N阱边缘（45）位于所述右边缘边缘（562）内或所述右边缘边缘（562）中，所述右边缘边缘（562）与所述漏极（48）间隔开第一距离（471）。 N阱（44）期望地包括与漏极（48）欧姆接触的较重的掺杂区域（62），并且其左边缘（621）位于右栅极边缘（562）和漏极（48）之间的大约一半处）。使用门（56）作为掩模，将HALO注入口袋（52）设置在左门边缘（561）下方。所得到的器件（40,60）在较高电压下工作，Rdson较低，HCI较少，非常低的截止状态泄漏。 P和N掺杂剂互换以提供P沟道器件。

26. 发明授权

US07700405B2 Microelectronic assembly with improved isolation voltage performance and a method for forming the same 有权
标题翻译：具有改进的隔离电压性能的微电子组件及其形成方法
公开(公告)号：US07700405B2
公开(公告)日：2010-04-20
申请号：US11680316
申请日：2007-02-28
申请人： Won Gi Min , Veronique C. Macary , Jiang-Kai Zuo
发明人： Won Gi Min , Veronique C. Macary , Jiang-Kai Zuo
IPC分类号： H01L21/44 , H01L21/48
CPC分类号： H01L21/761 , H01L21/823481 , H01L21/823493
摘要： A method for forming a microelectronic assembly and a microelectronic assembly are provided. First and second semiconductor devices (72) are formed over a substrate (20) having a first dopant type at a first concentration. First and second buried regions (28) having a second dopant type are formed respectively below the first and second semiconductor devices with a gap (34) therebetween. At least one well region (64, 70) is formed over the substrate and between the first and second semiconductor devices. A barrier region (48) having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth (82) from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.
摘要翻译：提供了一种用于形成微电子组件和微电子组件的方法。第一和第二半导体器件（72）形成在具有第一浓度的第一掺杂剂类型的衬底（20）上。具有第二掺杂剂类型的第一和第二埋入区域（28）分别在第一和第二半导体器件的下方形成，其间具有间隙（34）。在衬底上以及第一和第二半导体器件之间形成至少一个阱区（64,70）。具有第二浓度的第一掺杂剂类型的阻挡区域（48）形成在第一和第二掩埋区域之间并且与第一和第二掩埋区域相邻，使得阻挡区域的至少一部分从第一和第二半导体器件延伸深度（82）大于或等于埋藏区域的深度。

27. 发明授权

US07553704B2 Antifuse element and method of manufacture 有权
标题翻译：防腐元件及其制造方法
公开(公告)号：US07553704B2
公开(公告)日：2009-06-30
申请号：US11169951
申请日：2005-06-28
申请人： Won Gi Min , Robert W. Baird , Jiang-Kai Zuo , Gordon P. Lee
发明人： Won Gi Min , Robert W. Baird , Jiang-Kai Zuo , Gordon P. Lee
IPC分类号： H01L21/82 , H01L21/336 , H01L21/31
CPC分类号： H01L23/5252 , H01L27/112 , H01L27/11206 , H01L2924/0002 , Y10S438/981 , H01L2924/00
摘要： An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) and method of fabricating the antifuse element, including a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a gate oxide layer (110) disposed between the gate electrode (104) and the active area (106). The gate oxide layer (110) including the fabrication of one of a gate oxide dip (128) or a gate oxide undercut (614). During operation a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the gate oxide layer (110) and a rupture of the gate oxide layer (110) in a rupture region (130). The rupture region (130) defined by the oxide structure and the gate oxide dip (128) or the gate oxide undercut (614).
摘要翻译：反熔断元件（102,152,252,302,352,402,602,652,702）以及制造反熔丝元件的方法，包括在上表面形成有有效区域（106）的基板材料（101）具有位于有源区（106）上方的至少一部分的栅电极（104）和设置在栅电极（104）和有源区（106）之间的栅极氧化层（110）。栅极氧化物层（110）包括制造栅极氧化物浸渍（128）或栅极氧化物底切（614）之一。在操作期间，施加在栅极电极（104）和有源区域（106）之间的电压产生穿过栅极氧化物层（110）的电流路径以及在破裂区域（130）中的栅极氧化物层（110）的破裂。由氧化物结构和栅极氧化物浸渍（128）或栅极氧化物底切（614）限定的断裂区域（130）。

28. 发明申请

US20080224221A1 CASCODE CURRENT MIRROR AND METHOD 有权
公开(公告)号：US20080224221A1
公开(公告)日：2008-09-18
申请号：US11686439
申请日：2007-03-15
申请人： Hongning Yang , Geoffrey W. Perkins , Jiang-Kai Zuo
发明人： Hongning Yang , Geoffrey W. Perkins , Jiang-Kai Zuo
IPC分类号： H01L29/76
CPC分类号： H01L29/7833 , H01L21/823425 , H01L21/823456 , H01L21/823462 , H01L27/088 , H01L29/6659 , Y10S438/981
摘要： A cascode amplifier (CA) (60) is described having a bottom transistor (T1new) with a relatively thin gate dielectric (67) and higher ratio (RB) of channel length (Lch1new) to width (W1new) and a series coupled top transistor (T2new) with a relatively thick gate dielectric (68) and a lower ratio (RT) of channel length (Lch2new) to width (W2new). An improved cascode current mirror (CCM) (74) is formed using a coupled pair of CAs (60, 60′), one (60) forming the reference current (RC) side (601) and the other (60′) forming the mirror current side (602) of the CCM (74). The gates (65, 65′) of the bottom transistors (T1new, T3new) are tied together and to the common node (21) between the series coupled bottom (T1new) and top (T2new) transistors of the RC side (601), and the gates (66′, 66′) of the top transistors (T2new, T4new) are coupled together and to the top drain node (64) of the RC side (601). The area of the CCM (74) can be substantially shrunk without adverse affect on the matching, noise performance and maximum allowable operating voltage.
摘要翻译：描述了具有相对薄的栅极电介质（67）和沟道长度（Lch 1

29. 发明授权

US09570548B2 Deep trench isolation structures and systems and methods including the same 有权
标题翻译：深沟槽隔离结构及其系统和方法包括相同
公开(公告)号：US09570548B2
公开(公告)日：2017-02-14
申请号：US14831000
申请日：2015-08-20
申请人： Xu Cheng , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Xu Cheng , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L21/336 , H01L29/06 , H01L29/36 , H01L21/762 , H01L21/8234 , H01L27/02
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/823481 , H01L27/0203 , H01L27/0207 , H01L29/36
摘要： Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.
摘要翻译：深沟槽隔离结构及其系统和方法在此公开。该系统包括半导体器件。半导体器件包括半导体本体，器件区域和深沟槽隔离结构。深沟槽隔离结构被配置为将器件区域与在半导体本体内延伸的其它器件区域电隔离。深沟槽隔离结构包括隔离沟槽，在隔离沟槽内延伸的介电材料，第一半导体区域和第二半导体区域。所述方法包括操作集成电路器件的方法，所述集成电路器件包括包括所公开的深沟槽隔离结构的多个半导体器件。

30. 发明授权

US09401412B2 Methods of fabricating diodes with multiple junctions 有权
标题翻译：制造具有多个结的二极管的方法
公开(公告)号：US09401412B2
公开(公告)日：2016-07-26
申请号：US14804097
申请日：2015-07-20
申请人： Xin Lin , Hongning Yang , Jiang-Kai Zuo
发明人： Xin Lin , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L21/336 , H01L29/66 , H01L29/861 , H01L29/06 , H01L21/3205 , H01L21/265 , H01L29/08
CPC分类号： H01L29/66121 , H01L21/265 , H01L21/26513 , H01L21/32053 , H01L29/0649 , H01L29/08 , H01L29/6609 , H01L29/66128 , H01L29/861 , H01L29/8611
摘要： An embodiment of a method of fabricating a diode having a plurality of regions of a first conductivity type and a buried region of a second conductivity type includes performing a first dopant implantation procedure to form the buried region, performing a second dopant implantation procedure to form an intermediate region of the plurality of regions, and performing a third dopant implantation procedure to form a contact region of the plurality of regions. The second and third dopant implantation procedures are configured such that the intermediate region is electrically connected with the contact region. The first, second, and third dopant implantation procedures are configured such that the buried region extends laterally across the contact region and the intermediate region to establish first and second junctions of the diode, respectively, and such that the first junction has a lower breakdown voltage than the second junction.
摘要翻译：制造具有第一导电类型的多个区域和第二导电类型的掩埋区域的二极管的方法的实施例包括执行第一掺杂剂注入步骤以形成掩埋区域，执行第二掺杂剂注入工艺以形成并且执行第三掺杂剂注入过程以形成所述多个区域的接触区域。第二和第三掺杂剂注入程序被配置为使得中间区域与接触区域电连接。第一，第二和第三掺杂剂注入过程被配置为使得掩埋区域横向延伸穿过接触区域和中间区域以分别建立二极管的第一和第二结，并且使得第一结点具有较低的击穿电压比第二交界处。

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