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1. 发明授权

US07608513B2 Dual gate LDMOS device fabrication methods 失效
标题翻译：双栅LDMOS器件制造方法
公开(公告)号：US07608513B2
公开(公告)日：2009-10-27
申请号：US11626928
申请日：2007-01-25
申请人： Hongning Yang , Veronique C. Macary , Won Gi Min , Jiang-Kai Zuo
发明人： Hongning Yang , Veronique C. Macary , Won Gi Min , Jiang-Kai Zuo
IPC分类号： H01L21/336
CPC分类号： H01L29/7835 , H01L21/26586 , H01L29/0692 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/66537 , H01L29/66659 , H01L29/7831
摘要： An N-channel device (40, 60) is described having a lightly doped substrate (42, 42′) in which adjacent or spaced-apart P (46, 46′) and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the substrate (42, 42′) and is spaced apart from the wells (46, 46′, 44). A first gate (G1) (56) overlies the P (46) well or the substrate (42′) between the wells (46′, 44) or partly both. A second gate (G2) (66), spaced apart from G1 (56), overlies the N-well (44). A body contact (74) to the substrate (42, 42′) is spaced apart from the isolation wall (76) by a first distance (745) within the space charge region of the substrate (42, 42′) to isolation wall (76) PN junction. When the body contact (74) is connected to G2 (66), a predetermined static bias Vg2 is provided to G2 (66) depending upon the isolation wall bias (Vbias) and the first distance (745). The resulting device (40, 60) operates at higher voltage with lower Rdson and less HCI.
摘要翻译：描述了具有轻掺杂衬底（42,42'）的N沟道器件（40,60），其中提供相邻或间隔开的P（46,46'）和N（44）阱。横向隔离壁（76）围绕衬底（42,42'）的至少一部分并且与井（46,46'，44）间隔开。第一栅极（G1）（56）覆盖在孔（46'，44）之间的P（46）阱或衬底（42'）上，或者部分覆盖两者。与G1（56）间隔开的第二门（G2）（66）覆盖在N阱（44）上。衬底（42,42'）的主体接触件（74）与隔离壁（76）隔开第一距离（745），在衬底（42,42'）的空间电荷区域内与隔离壁（ 76）PN结。当身体接触（74）连接到G2（66）时，根据隔离壁偏压（Vbias）和第一距离（745），将预定的静态偏压Vg2提供给G2（66）。所得到的装置（40,60）以更低的Rdson和更少的HCI工作在更高的电压。

2. 发明申请

US20100025765A1 DUAL GATE LDMOS DEVICES 有权
标题翻译：双门LDMOS器件
公开(公告)号：US20100025765A1
公开(公告)日：2010-02-04
申请号：US12560588
申请日：2009-09-16
申请人： Hongning Yang , Veronique C. Macary , Won Gi Min , Jiang-Kai Zuo
发明人： Hongning Yang , Veronique C. Macary , Won Gi Min , Jiang-Kai Zuo
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L21/26586 , H01L29/0692 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/66537 , H01L29/66659 , H01L29/7831
摘要： An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vg2 is provided to the second gate, depending upon the isolation wall bias (Vbias) and the first distance.
摘要翻译： N沟道器件的实施例具有轻掺杂衬底，其中提供相邻或间隔开的P和N阱。横向隔离壁围绕衬底的至少一部分并且与孔间隔开。第一个栅极覆盖在井之间的P阱或基底之间，或部分地两者。与第一个门相隔开的第二个栅极覆盖着N阱。与衬底的身体接触在隔离壁PN结处与衬底的空间电荷区域内的隔离壁隔开第一距离。当体接触件连接到第二栅极时，根据隔离壁偏压（Vbias）和第一距离，将预定的静态偏压Vg2提供给第二栅极。

3. 发明申请

US20080182394A1 DUAL GATE LDMOS DEVICE AND METHOD 失效
标题翻译：双门LDMOS器件及方法
公开(公告)号：US20080182394A1
公开(公告)日：2008-07-31
申请号：US11626928
申请日：2007-01-25
申请人： Hongning Yang , Veronique C. Macary , Won Gi Min , Jiang-Kai Zuo
发明人： Hongning Yang , Veronique C. Macary , Won Gi Min , Jiang-Kai Zuo
IPC分类号： H01L21/04
CPC分类号： H01L29/7835 , H01L21/26586 , H01L29/0692 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/66537 , H01L29/66659 , H01L29/7831
摘要： An N-channel device (40, 60) is described having a lightly doped substrate (42, 42′) in which adjacent or spaced-apart P (46, 46′) and N (44) wells are provided. A lateral isolation wall (76) surrounds at least a portion of the substrate (42, 42′) and is spaced apart from the wells (46, 46′, 44). A first gate (G1) (56) overlies the P (46) well or the substrate (42′) between the wells (46′, 44) or partly both. A second gate (G2) (66), spaced apart from G1 (56), overlies the N-well (44). A body contact (74) to the substrate (42, 42′) is spaced apart from the isolation wall (76) by a first distance (745) within the space charge region of the substrate (42, 42′) to isolation wall (76) PN junction. When the body contact (74) is connected to G2 (66), a predetermined static bias Vg2 is provided to G2 (66) depending upon the isolation wall bias (Vbias) and the first distance (745). The resulting device (40, 60) operates at higher voltage with lower Rdson and less HCI.
摘要翻译：描述了具有轻掺杂衬底（42,42'）的N沟道器件（40,60），其中提供相邻或间隔开的P（46,46'）和N（44）阱。横向隔离壁（76）围绕衬底（42,42'）的至少一部分并且与井（46,46'，44）间隔开。第一栅极（G 1）（56）覆盖在孔（46'，44）之间的P（46）阱或衬底（42'）上，或者部分地覆盖两者。与G 1（56）间隔开的第二栅极（G 2）（66）覆盖在N阱（44）上。衬底（42,42'）的主体接触件（74）与隔离壁（76）隔开第一距离（745），在衬底（42,42'）的空间电荷区域内与隔离壁（ 76）PN结。当主体接触件（74）连接到G 2（66）时，根据隔离壁偏压（Vbias）和第一距离（745），将预定的静态偏压Vg 2提供给G 2（66）。所得到的装置（40,60）以更低的Rdson和更少的HCI工作在更高的电压。

4. 发明授权

US07795674B2 Dual gate LDMOS devices 有权
标题翻译：双门LDMOS器件
公开(公告)号：US07795674B2
公开(公告)日：2010-09-14
申请号：US12560588
申请日：2009-09-16
申请人： Hongning Yang , Veronique C. Macary , Won Gi Min , Jiang-Kai Zuo
发明人： Hongning Yang , Veronique C. Macary , Won Gi Min , Jiang-Kai Zuo
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L21/26586 , H01L29/0692 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/66537 , H01L29/66659 , H01L29/7831
摘要： An embodiment of an N-channel device has a lightly doped substrate in which adjacent or spaced-apart P and N wells are provided. A lateral isolation wall surrounds at least a portion of the substrate and is spaced apart from the wells. A first gate overlies the P well or the substrate between the wells or partly both. A second gate, spaced apart from the first gate, overlies the N-well. A body contact to the substrate is spaced apart from the isolation wall by a first distance within the space charge region of the substrate to isolation wall PN junction. When the body contact is connected to the second gate, a predetermined static bias Vg2 is provided to the second gate, depending upon the isolation wall bias (Vbias) and the first distance.
摘要翻译： N沟道器件的一个实施例具有轻掺杂衬底，其中提供相邻或间隔开的P和N阱。横向隔离壁围绕衬底的至少一部分并且与孔间隔开。第一个栅极覆盖在井之间的P阱或基底之间，或部分地两者。与第一个门相隔开的第二个栅极覆盖着N阱。与衬底的身体接触在隔离壁PN结处与衬底的空间电荷区域内的隔离壁隔开第一距离。当体接触件连接到第二栅极时，根据隔离壁偏压（Vbias）和第一距离，将预定的静态偏压Vg2提供给第二栅极。

5. 发明申请

US20100164056A1 MICROELECTRONIC ASSEMBLIES WITH IMPROVED ISOLATION VOLTAGE PERFORMANCE 有权
标题翻译：具有改进隔离电压性能的微电子组件
公开(公告)号：US20100164056A1
公开(公告)日：2010-07-01
申请号：US12717522
申请日：2010-03-04
申请人： Won Gi Min , Veronique C. Macary , Jiang-Kai Zuo
发明人： Won Gi Min , Veronique C. Macary , Jiang-Kai Zuo
IPC分类号： H01L29/06
CPC分类号： H01L21/761 , H01L21/823481 , H01L21/823493
摘要： Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below the first and second semiconductor devices with a gap therebetween. At least one well region is formed over the substrate and between the first and second semiconductor devices. A barrier region having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.
摘要翻译：提供了微电子组件的实施例。第一和第二半导体器件形成在具有第一浓度的第一掺杂剂类型的衬底上。具有第二掺杂剂类型的第一和第二掩埋区分别形成在第一和第二半导体器件的下面，其间具有间隙。至少一个阱区形成在衬底上并且在第一和第二半导体器件之间。具有第二浓度的第一掺杂剂类型的屏障区域形成在第一和第二掩埋区域之间并且与第一和第二掩埋区域相邻，使得至少一部分阻挡区域从第一和第二半导体器件的深度延伸大于或等于埋藏区域的深度。

6. 发明申请

US20080203519A1 MICROELECTRONIC ASSEMBLY WITH IMPROVED ISOLATION VOLTAGE PERFORMANCE AND A METHOD FOR FORMING THE SAME 有权
标题翻译：具有改进的隔离电压性能的微电子组件及其形成方法
公开(公告)号：US20080203519A1
公开(公告)日：2008-08-28
申请号：US11680316
申请日：2007-02-28
申请人： Won Gi Min , Veronique C. Macary , Jiang-Kai Zuo
发明人： Won Gi Min , Veronique C. Macary , Jiang-Kai Zuo
IPC分类号： H01L29/00 , H01L21/00
CPC分类号： H01L21/761 , H01L21/823481 , H01L21/823493
摘要： A method for forming a microelectronic assembly and a microelectronic assembly are provided. First and second semiconductor devices (72) are formed over a substrate (20) having a first dopant type at a first concentration. First and second buried regions (28) having a second dopant type are formed respectively below the first and second semiconductor devices with a gap (34) therebetween. At least one well region (64, 70) is formed over the substrate and between the first and second semiconductor devices. A barrier region (48) having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth (82) from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.
摘要翻译：提供了一种用于形成微电子组件和微电子组件的方法。第一和第二半导体器件（72）形成在具有第一浓度的第一掺杂剂类型的衬底（20）上。具有第二掺杂剂类型的第一和第二埋入区域（28）分别在第一和第二半导体器件的下方形成，其间具有间隙（34）。在衬底上以及第一和第二半导体器件之间形成至少一个阱区（64,70）。具有第二浓度的第一掺杂剂类型的势垒区域（48）形成在第一和第二掩埋区域之间并且与第一和第二掩埋区域相邻，使得阻挡区域的至少一部分从第一和第二半导体器件延伸深度（82）大于或等于埋藏区域的深度。

7. 发明授权

US07795702B2 Microelectronic assemblies with improved isolation voltage performance 有权
标题翻译：具有提高隔离电压性能的微电子组件
公开(公告)号：US07795702B2
公开(公告)日：2010-09-14
申请号：US12717522
申请日：2010-03-04
申请人： Won Gi Min , Veronique C. Macary , Jiang-Kai Zuo
发明人： Won Gi Min , Veronique C. Macary , Jiang-Kai Zuo
IPC分类号： H01L29/00
CPC分类号： H01L21/761 , H01L21/823481 , H01L21/823493
摘要： Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below the first and second semiconductor devices with a gap therebetween. At least one well region is formed over the substrate and between the first and second semiconductor devices. A barrier region having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.
摘要翻译：提供了微电子组件的实施例。第一和第二半导体器件形成在具有第一浓度的第一掺杂剂类型的衬底上。具有第二掺杂剂类型的第一和第二掩埋区分别形成在第一和第二半导体器件的下面，其间具有间隙。至少一个阱区形成在衬底上并且在第一和第二半导体器件之间。具有第二浓度的第一掺杂剂类型的屏障区域形成在第一和第二掩埋区域之间并且与第一和第二掩埋区域相邻，使得至少一部分阻挡区域从第一和第二半导体器件的深度延伸大于或等于埋藏区域的深度。

8. 发明授权

US07700405B2 Microelectronic assembly with improved isolation voltage performance and a method for forming the same 有权
标题翻译：具有改进的隔离电压性能的微电子组件及其形成方法
公开(公告)号：US07700405B2
公开(公告)日：2010-04-20
申请号：US11680316
申请日：2007-02-28
申请人： Won Gi Min , Veronique C. Macary , Jiang-Kai Zuo
发明人： Won Gi Min , Veronique C. Macary , Jiang-Kai Zuo
IPC分类号： H01L21/44 , H01L21/48
CPC分类号： H01L21/761 , H01L21/823481 , H01L21/823493
摘要： A method for forming a microelectronic assembly and a microelectronic assembly are provided. First and second semiconductor devices (72) are formed over a substrate (20) having a first dopant type at a first concentration. First and second buried regions (28) having a second dopant type are formed respectively below the first and second semiconductor devices with a gap (34) therebetween. At least one well region (64, 70) is formed over the substrate and between the first and second semiconductor devices. A barrier region (48) having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth (82) from the first and second semiconductor devices that is greater or equal to the depth of the buried regions.
摘要翻译：提供了一种用于形成微电子组件和微电子组件的方法。第一和第二半导体器件（72）形成在具有第一浓度的第一掺杂剂类型的衬底（20）上。具有第二掺杂剂类型的第一和第二埋入区域（28）分别在第一和第二半导体器件的下方形成，其间具有间隙（34）。在衬底上以及第一和第二半导体器件之间形成至少一个阱区（64,70）。具有第二浓度的第一掺杂剂类型的阻挡区域（48）形成在第一和第二掩埋区域之间并且与第一和第二掩埋区域相邻，使得阻挡区域的至少一部分从第一和第二半导体器件延伸深度（82）大于或等于埋藏区域的深度。

9. 发明授权

US08389366B2 Resurf semiconductor device charge balancing 有权
标题翻译： Resurf半导体器件电荷平衡
公开(公告)号：US08389366B2
公开(公告)日：2013-03-05
申请号：US12129840
申请日：2008-05-30
申请人： Won Gi Min , Hongzhong Xu , Zhihong Zhang , Jiang-Kai Zuo
发明人： Won Gi Min , Hongzhong Xu , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/772
CPC分类号： H01L29/7823 , H01L29/063 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/7816 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices (40, 60, 80, 80′, 80″), e.g., LDMOS transistors, by careful charge balancing, even when body (44, 44′, 84, 84′) and drift (50, 50′, 90, 90′) region charge balance is not ideal, by: (i) providing a plug or sinker (57) near the drain (52, 92) and of the same conductivity type extending through the drift region (50, 50′, 90, 90′) at least into the underlying body region (44, 44′ 84, 84′), and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall (102) coupled to the device buried layer (42, 82), and/or (iii) providing a variable resistance bridge (104) between the isolation wall (102) and the drift region (50, 50′, 90, 90′). The bridge (104) may be a FET (110) whose source-drain (113, 114) couple the isolation wall (102) and drift region (50, 50′, 90, 90′) and whose gate (116) receives control voltage Vc, or a resistor (120) whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer (42, 82) via the isolation wall (102).
摘要翻译：即使当主体（44,44'，84,84“），RESURF装置（40,60,80,80'，80”），例如LDMOS晶体管也通过小心的电荷平衡来增强击穿电压BVdss并导通电阻，）和漂移（50,50'，90,90'）区域电荷平衡不是理想的，通过：（i）在漏极（52,92）附近提供插塞或沉降片（57），并且延伸通过相同的导电类型至少进入下面的主体区域（44,44'，84,84'）中的漂移区域（50,50'，90,90'），和/或（ii）将偏置Viso施加到周围的侧向掺杂隔离壁（102 ）和/或（iii）在所述隔离壁（102）和所述漂移区域（50,50'，90,90'）之间提供可变电阻桥（104）。桥（104）可以是源极漏极（113,114）耦合隔离壁（102）和漂移区（50,50'，90,90'）并且其栅极（116）接收控制电压Vc或其横截面（X，Y，Z）影响其电阻和夹断的电阻器（120），以经由隔离壁（42,82）设置耦合到埋层（42,82）的漏极电压的百分比 102）。

10. 发明申请

US20090294849A1 RESURF SEMICONDUCTOR DEVICE CHARGE BALANCING 有权
标题翻译： RESURF半导体器件充电平衡
公开(公告)号：US20090294849A1
公开(公告)日：2009-12-03
申请号：US12129840
申请日：2008-05-30
申请人： Won Gi Min , Zhihong Zhang , Hongzhong Xu , Jiang-Kai Zuo
发明人： Won Gi Min , Zhihong Zhang , Hongzhong Xu , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L23/58
CPC分类号： H01L29/7823 , H01L29/063 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/7816 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices (40, 60, 80, 80′, 80″), e.g., LDMOS transistors, by careful charge balancing, even when body (44, 44′, 84, 84′) and drift (50, 50′, 90, 90′) region charge balance is not ideal, by: (i) providing a plug or sinker (57) near the drain (52, 92) and of the same conductivity type extending through the drift region (50, 50′, 90, 90′) at least into the underlying body region (44, 44′ 84, 84′), and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall (102) coupled to the device buried layer (42, 82), and/or (iii) providing a variable resistance bridge (104) between the isolation wall (102) and the drift region (50, 50′, 90, 90′). The bridge (104) may be a FET (110) whose source-drain (113, 114) couple the isolation wall (102) and drift region (50, 50′, 90, 90′) and whose gate (116) receives control voltage Vc, or a resistor (120) whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer (42, 82) via the isolation wall (102).
摘要翻译：即使在主体（44,44'，84,84）中，分解电压BVdss被增强，并且RESURF器件（40,60,80,80'，80“）中的导通电阻降低，例如LDMOS晶体管 '）和漂移（50,50'，90,90'）区域电荷平衡不是理想的，通过：（i）在漏极（52,92）附近提供插塞或沉降片（57），并且具有相同的导电类型延伸至少穿过所述漂移区域（50,50'，90,90'）到所述下部体区域（44,44'，84,84'）中，和/或（ii）将偏压Viso施加到周围的侧向掺杂隔离壁 102）和/或（iii）在隔离壁（102）和漂移区域（50,50'，90,90'）之间提供可变电阻桥（104）。桥（104）可以是源极漏极（113,114）耦合隔离壁（102）和漂移区（50,50'，90,90'）并且其栅极（116）接收控制电压Vc或其横截面（X，Y，Z）影响其电阻和夹断的电阻器（120），以经由隔离壁（42,82）设置耦合到埋层（42,82）的漏极电压的百分比 102）。

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