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1. 发明申请

US20080224221A1 CASCODE CURRENT MIRROR AND METHOD 有权
公开(公告)号：US20080224221A1
公开(公告)日：2008-09-18
申请号：US11686439
申请日：2007-03-15
申请人： Hongning Yang , Geoffrey W. Perkins , Jiang-Kai Zuo
发明人： Hongning Yang , Geoffrey W. Perkins , Jiang-Kai Zuo
IPC分类号： H01L29/76
CPC分类号： H01L29/7833 , H01L21/823425 , H01L21/823456 , H01L21/823462 , H01L27/088 , H01L29/6659 , Y10S438/981
摘要： A cascode amplifier (CA) (60) is described having a bottom transistor (T1new) with a relatively thin gate dielectric (67) and higher ratio (RB) of channel length (Lch1new) to width (W1new) and a series coupled top transistor (T2new) with a relatively thick gate dielectric (68) and a lower ratio (RT) of channel length (Lch2new) to width (W2new). An improved cascode current mirror (CCM) (74) is formed using a coupled pair of CAs (60, 60′), one (60) forming the reference current (RC) side (601) and the other (60′) forming the mirror current side (602) of the CCM (74). The gates (65, 65′) of the bottom transistors (T1new, T3new) are tied together and to the common node (21) between the series coupled bottom (T1new) and top (T2new) transistors of the RC side (601), and the gates (66′, 66′) of the top transistors (T2new, T4new) are coupled together and to the top drain node (64) of the RC side (601). The area of the CCM (74) can be substantially shrunk without adverse affect on the matching, noise performance and maximum allowable operating voltage.
摘要翻译：描述了具有相对薄的栅极电介质（67）和沟道长度（Lch 1

2. 发明申请

US20100156388A1 CASCODE CURRENT MIRROR AND METHOD 有权
公开(公告)号：US20100156388A1
公开(公告)日：2010-06-24
申请号：US12715941
申请日：2010-03-02
申请人： Hongning Yang , Geoffrey W. Perkins , Jiang-Kai Zuo
发明人： Hongning Yang , Geoffrey W. Perkins , Jiang-Kai Zuo
IPC分类号： G05F3/16
CPC分类号： H01L29/7833 , H01L21/823425 , H01L21/823456 , H01L21/823462 , H01L27/088 , H01L29/6659 , Y10S438/981
摘要： Embodiments of a cascode amplifier (CA) include a bottom transistor with a relatively thin gate dielectric and higher ratio of channel length to width and a series coupled top transistor with a relatively thick gate dielectric and a lower ratio of channel length to width. A cascode current mirror (CCM) is formed using a coupled pair of CAs, one forming the reference current (RC) side and the other forming the mirror current side of the CCM. The gates of the bottom transistors are tied together and to the common node between the series coupled bottom and top transistors of the RC side, and the gates of the top transistors are coupled together and to the top drain node of the RC side. The area of the CCM can be substantially shrunk without adverse affect on the matching, noise performance and maximum allowable operating voltage.
摘要翻译：共源共栅放大器（CA）的实施例包括具有相对薄的栅极介质和沟道长度与宽度的较高比的底部晶体管和具有相对较厚的栅极电介质和沟道长度与宽度的较小比的串联耦合顶部晶体管。使用耦合的一对CA形成共源共栅电流镜（CCM），一对形成基准电流（RC）侧，另一个形成CCM的反射镜电流侧。底部晶体管的栅极连接在RC侧的串联耦合的底部和顶部晶体管之间的公共节点，并且顶部晶体管的栅极耦合在一起并连接到RC侧的顶部漏极节点。 CCM的面积可以大幅收缩，对匹配，噪声性能和最大允许工作电压没有不利影响。

3. 发明授权

US07700417B2 Methods for forming cascode current mirrors 有权
标题翻译：形成共源共栅电流镜的方法
公开(公告)号：US07700417B2
公开(公告)日：2010-04-20
申请号：US11686439
申请日：2007-03-15
申请人： Hongning Yang , Geoffrey W. Perkins , Jiang-Kai Zuo
发明人： Hongning Yang , Geoffrey W. Perkins , Jiang-Kai Zuo
IPC分类号： H01L21/00
CPC分类号： H01L29/7833 , H01L21/823425 , H01L21/823456 , H01L21/823462 , H01L27/088 , H01L29/6659 , Y10S438/981
摘要： A cascode amplifier (CA) (60) is described having a bottom transistor (T1new) with a relatively thin gate dielectric (67) and higher ratio (RB) of channel length (Lch1new) to width (W1new) and a series coupled top transistor (T2new) with a relatively thick gate dielectric (68) and a lower ratio (RT) of channel length (Lch2new) to width (W2new). An improved cascode current mirror (CCM) (74) is formed using a coupled pair of CAs (60, 60′), one (60) forming the reference current (RC) side (601) and the other (60′) forming the mirror current side (602) of the CCM (74). The gates (65, 65′) of the bottom transistors (T1new, T3new) are tied together and to the common node (21) between the series coupled bottom (T1new) and top (T2new) transistors of the RC side (601), and the gates (66′, 66′) of the top transistors (T2new, T4new) are coupled together and to the top drain node (64) of the RC side (601). The area of the CCM (74) can be substantially shrunk without adverse affect on the matching, noise performance and maximum allowable operating voltage.
摘要翻译：描述了一种级联放大器（CA）（60），其具有具有相对薄的栅极电介质（67）和沟道长度（Lch1new）至宽度（W1new）的更高比率（RB））的底部晶体管（T1new）和串联耦合顶部晶体管（T2new），具有相对较厚的栅极电介质（68）和沟道长度（Lch2new）与宽度（W2new）的较低比率（RT）。使用耦合的一对CA（60,60'），形成基准电流（RC）侧（601）的一个（60）和形成基准电流（RC））的另一个（60'）形成改进的共源共栅电流镜（CC） CCM（74）的镜电流侧（602）。底部晶体管（T1new，T3new）的栅极（65,65'）被连接到RC侧（601）的串联耦合的底部（T1new）和顶部（T2new）晶体管之间的公共节点（21）并且顶部晶体管（T2new，T4new）的栅极（66'，66'）耦合在一起并连接到RC侧（601）的顶部漏极节点（64）。 CCM（74）的面积可以基本上缩小，而不会对匹配，噪声性能和最大允许工作电压产生不利影响。

4. 发明授权

US07851834B2 Cascode current mirror and method 有权
标题翻译： Cascode电流镜和方法
公开(公告)号：US07851834B2
公开(公告)日：2010-12-14
申请号：US12715941
申请日：2010-03-02
申请人： Hongning Yang , Geoffrey W. Perkins , Jiang-Kai Zuo
发明人： Hongning Yang , Geoffrey W. Perkins , Jiang-Kai Zuo
IPC分类号： H01L29/94
CPC分类号： H01L29/7833 , H01L21/823425 , H01L21/823456 , H01L21/823462 , H01L27/088 , H01L29/6659 , Y10S438/981
摘要： Embodiments of a cascode amplifier (CA) include a bottom transistor with a relatively thin gate dielectric and higher ratio of channel length to width and a series coupled top transistor with a relatively thick gate dielectric and a lower ratio of channel length to width. A cascode current mirror (CCM) is formed using a coupled pair of CAs, one forming the reference current (RC) side and the other forming the mirror current side of the CCM. The gates of the bottom transistors are tied together and to the common node between the series coupled bottom and top transistors of the RC side, and the gates of the top transistors are coupled together and to the top drain node of the RC side. The area of the CCM can be substantially shrunk without adverse affect on the matching, noise performance and maximum allowable operating voltage.
摘要翻译：共源共栅放大器（CA）的实施例包括具有相对薄的栅极介质和沟道长度与宽度的较高比的底部晶体管和具有相对较厚的栅极电介质和沟道长度与宽度的较小比的串联耦合顶部晶体管。使用耦合的一对CA形成共源共栅电流镜（CCM），一对形成基准电流（RC）侧，另一个形成CCM的反射镜电流侧。底部晶体管的栅极连接在RC侧的串联耦合的底部和顶部晶体管之间的公共节点，并且顶部晶体管的栅极耦合在一起并连接到RC侧的顶部漏极节点。 CCM的面积可以大幅收缩，对匹配，噪声性能和最大允许工作电压没有不利影响。

5. 发明授权

US09666671B2 Semiconductor device with composite drift region and related fabrication method 有权
公开(公告)号：US09666671B2
公开(公告)日：2017-05-30
申请号：US14279991
申请日：2014-05-16
申请人： Zhihong Zhang , Hongning Yang , Jiang-Kai Zuo
发明人： Zhihong Zhang , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/10 , H01L29/78 , H01L29/66 , H01L29/36 , H01L29/06 , H01L29/08 , H01L21/265
CPC分类号： H01L29/1045 , H01L21/26513 , H01L21/2652 , H01L29/0653 , H01L29/0847 , H01L29/36 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A device includes a semiconductor substrate, a body region in the semiconductor substrate having a first conductivity type and in which a channel is formed during operation, source and drain regions in the semiconductor substrate and having a second conductivity type, the source region being disposed on the body region, and a composite drift region in the semiconductor substrate, having the second conductivity type, and through which charge carriers from the source region drift to reach the drain region after passing through the channel. The composite drift region includes a first section adjacent the channel, a second section adjacent the drain region, and a third section disposed between the first and second sections. The first and second sections have a lower effective dopant concentration level than the third section.

6. 发明授权

US09496333B2 Resurf high voltage diode 有权
公开(公告)号：US09496333B2
公开(公告)日：2016-11-15
申请号：US14622068
申请日：2015-02-13
申请人： Xin Lin , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L29/06 , H01L29/739 , H01L29/861
CPC分类号： H01L29/063 , H01L29/0649 , H01L29/0692 , H01L29/66356 , H01L29/7391 , H01L29/861
摘要： A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a buried cathode extension region (104) formed under a RESURF anode extension region (106, 107) such that the cathode extension region (104) extends beyond the cathode contact (131) to be sandwiched between upper and lower regions (103, 106, 107) of opposite conductivity type.

7. 发明授权

US09478456B2 Semiconductor device with composite drift region 有权
标题翻译：具有复合漂移区的半导体器件
公开(公告)号：US09478456B2
公开(公告)日：2016-10-25
申请号：US13413440
申请日：2012-03-06
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L21/762 , H01L29/66 , H01L29/08 , H01L29/06
CPC分类号： H01L21/76224 , H01L29/0653 , H01L29/0847 , H01L29/66659 , H01L29/7835
摘要： A device includes a semiconductor substrate, a channel region in the semiconductor substrate having a first conductivity type, and a composite drift region in the semiconductor substrate, having a second conductivity type. The composite drift region includes a first drift region and a second drift region spaced from the channel region by the first drift region. The device further includes a drain region in the semiconductor substrate, spaced from the channel region by the composite drain region, and having the second conductivity type. The first drift region has a dopant concentration profile with a first concentration level where adjacent the channel region and a second concentration level where adjacent the second drift region, the first concentration level being higher than the second concentration level. In some embodiments, the first and second drift regions are stacked vertically, with the first drift region being shallower than the second drift region.
摘要翻译：一种器件包括半导体衬底，具有第一导电类型的半导体衬底中的沟道区域和具有第二导电类型的半导体衬底中的复合漂移区域。复合漂移区域包括第一漂移区域和第一漂移区域与沟道区域间隔开的第二漂移区域。该器件还包括在半导体衬底中的漏极区域，通过复合漏极区域与沟道区域间隔开并具有第二导电类型。第一漂移区域具有第一浓度水平的掺杂剂浓度分布，其中邻近通道区域的第一浓度水平和与第二漂移区域相邻的第二浓度水平，第一浓度水平高于第二浓度水平。在一些实施例中，第一漂移区域和第二漂移区域垂直堆叠，其中第一漂移区域比第二漂移区域浅。

8. 发明授权

US09385229B2 Semiconductor device with improved breakdown voltage 有权
标题翻译：具有提高击穿电压的半导体器件
公开(公告)号：US09385229B2
公开(公告)日：2016-07-05
申请号：US14495508
申请日：2014-09-24
申请人： Hongning Yang , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7824 , H01L29/0623 , H01L29/063 , H01L29/0634 , H01L29/0653 , H01L29/1095 , H01L29/4175 , H01L29/66659 , H01L29/66681 , H01L29/7835 , H01L29/78624
摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first region of semiconductor material having a first conductivity type and a first dopant concentration, a second region of semiconductor material having a second conductivity type overlying the first region, a drift region of semiconductor material having the first conductivity type overlying the second region, and a drain region of semiconductor material having the first conductivity type. The drift region and the drain region are electrically connected, with at least a portion of the drift region residing between the drain region and the second region, and at least a portion of the second region residing between that drift region and the first region. In one or more exemplary embodiments, the first region abuts an underlying insulating layer of dielectric material.
摘要翻译：提供半导体器件结构和相关的制造方法。示例性的半导体器件结构包括具有第一导电类型和第一掺杂剂浓度的第一半导体材料区域，具有覆盖第一区域的第二导电类型的第二半导体材料区域，具有第一导电类型的半导体材料的漂移区域覆盖第二区域，以及具有第一导电类型的半导体材料的漏极区域。漂移区域和漏极区域电连接，漂移区域的至少一部分位于漏极区域和第二区域之间，并且第二区域的至少一部分位于该漂移区域和第一区域之间。在一个或多个示例性实施例中，第一区域邻接介电材料的下层绝缘层。

9. 发明授权

US09231083B2 High breakdown voltage LDMOS device 有权
标题翻译：高击穿电压LDMOS器件
公开(公告)号：US09231083B2
公开(公告)日：2016-01-05
申请号：US13537619
申请日：2012-06-29
申请人： Hongning Yang , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66 , H01L29/10 , H01L29/06
CPC分类号： H01L29/66689 , H01L21/76229 , H01L21/76264 , H01L29/0653 , H01L29/1083 , H01L29/66484 , H01L29/66772 , H01L29/7824
摘要： A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep-trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).
摘要翻译：多区域（81,83）横向扩散金属氧化物半导体（LDMOS）器件（40）具有绝缘体上半导体（SOI）支撑结构（21），其上形成有基本上对称的横向内部的第一LDMOS区域（81）和基本不对称的横向边缘邻近的第二LDMOS区域（83）。深沟槽隔离（DTI）壁（60）基本上横向地终止横向边缘邻近的第二LDMOS区域（83）。通过在SOI中提供掺杂的SC掩埋层区域（86）来避免由与DTI壁（60）相关联的横向边缘邻近的第二LDMOS区域（83）表现出的电场增强和较低的源极 - 漏极击穿电压（BVDSS）靠近DTI壁（60）的支撑结构（21），位于横向边缘邻近的第二LDMOS区域（83）的一部分下方并且具有与横向边缘邻近的第二LDMOS区域的漏极区域（31）相反的导电类型 83）。

10. 发明授权

US09165918B1 Composite semiconductor device with multiple threshold voltages 有权
标题翻译：具有多个阈值电压的复合半导体器件
公开(公告)号：US09165918B1
公开(公告)日：2015-10-20
申请号：US14272027
申请日：2014-05-07
申请人： Hongning Yang , Xin Lin , Pete Rodriguez , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Pete Rodriguez , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L27/02 , H01L29/78 , H01L29/08 , H01L29/10 , H01L27/088 , H01L21/8234 , H01L21/265
CPC分类号： H01L27/0248 , H01L21/26513 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L27/0266 , H01L27/088 , H01L29/0653 , H01L29/0696 , H01L29/0865 , H01L29/0882 , H01L29/1045 , H01L29/1079 , H01L29/1095 , H01L29/66575 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures includes a non-uniform channel such that the first constituent transistor has a higher threshold voltage level than the second constituent transistor.
摘要翻译：一种器件包括半导体衬底，第一组成晶体管，其包括彼此并联连接的半导体衬底中的第一多个晶体管结构;以及第二组成晶体管，包括在半导体衬底中并联连接的第二多个晶体管结构，另一个。第一和第二组成晶体管彼此横向相邻设置并彼此并联连接。第一多个晶体管结构的每个晶体管结构包括非均匀沟道，使得第一构成晶体管具有比第二构成晶体管更高的阈值电压电平。

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