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    • 2. 发明授权
    • Semiconductor device with improved breakdown voltage
    • 具有提高击穿电压的半导体器件
    • US09385229B2
    • 2016-07-05
    • US14495508
    • 2014-09-24
    • Hongning YangXin LinZhihong ZhangJiang-Kai Zuo
    • Hongning YangXin LinZhihong ZhangJiang-Kai Zuo
    • H01L29/78H01L29/66
    • H01L29/7824H01L29/0623H01L29/063H01L29/0634H01L29/0653H01L29/1095H01L29/4175H01L29/66659H01L29/66681H01L29/7835H01L29/78624
    • Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first region of semiconductor material having a first conductivity type and a first dopant concentration, a second region of semiconductor material having a second conductivity type overlying the first region, a drift region of semiconductor material having the first conductivity type overlying the second region, and a drain region of semiconductor material having the first conductivity type. The drift region and the drain region are electrically connected, with at least a portion of the drift region residing between the drain region and the second region, and at least a portion of the second region residing between that drift region and the first region. In one or more exemplary embodiments, the first region abuts an underlying insulating layer of dielectric material.
    • 提供半导体器件结构和相关的制造方法。 示例性的半导体器件结构包括具有第一导电类型和第一掺杂剂浓度的第一半导体材料区域,具有覆盖第一区域的第二导电类型的第二半导体材料区域,具有第一导电类型的半导体材料的漂移区域 覆盖第二区域,以及具有第一导电类型的半导体材料的漏极区域。 漂移区域和漏极区域电连接,漂移区域的至少一部分位于漏极区域和第二区域之间,并且第二区域的至少一部分位于该漂移区域和第一区域之间。 在一个或多个示例性实施例中,第一区域邻接介电材料的下层绝缘层。
    • 6. 发明授权
    • Near zero channel length field drift LDMOS
    • 近零通道长度场漂移LDMOS
    • US08575692B2
    • 2013-11-05
    • US13025350
    • 2011-02-11
    • Hongning YangXin LinJiang-Kai Zuo
    • Hongning YangXin LinJiang-Kai Zuo
    • H01L29/78
    • H01L29/66681H01L21/26586H01L29/0653H01L29/086H01L29/0878H01L29/1083H01L29/1095H01L29/66689H01L29/7801H01L29/7816
    • Adverse tradeoff between BVDSS and Rdson in LDMOS devices employing a drift space (52, 152) adjacent the drain (56, 156), is avoided by providing a lightly doped region (511, 1511) of a first conductivity type (CT) separating the first CT drift space (52, 152) from an opposite CT WELL region (53, 153) in which the first CT source (57, 157) is located, and a further region (60, 160) of the opposite CT (e.g., formed by an angled implant) extending through part of the WELL region (53, 153) under an edge (591, 1591) of the gate (59, 159) located near a boundary (531, 1531) of the WELL region (53, 153) into the lightly doped region (511, 1511), and a shallow still further region (66, 166) of the first CT Ohmically coupled to the source (57, 157) and ending near the gate edge (591, 159) whereby the effective channel length (61, 161) in the further region (60, 160) is reduced to near zero. Substantial improvement in BVDSS and/or Rdson can be obtained without degrading the other or significant adverse affect on other device properties.
    • 通过提供第一导电类型(CT)的轻掺杂区域(511,1511)来避免使用邻近漏极(56,156)的漂移空间(52,152)的LDMOS器件中的BVDSS和Rdson之间的不利权衡, 从第一CT源(57,157)所在的相对的CT WELL区域(53,153)的第一CT漂移空间(52,152)和相对CT的另一区域(60,160) 由位于靠近所述WELL区域(53,153)的边界(531,1531)附近的所述门(59,159)的边缘(591,1591)下延伸穿过所述WELL区域(53,153)的一部分的一部分, 153和157)连接到所述源极(57,157)并且在所述栅极边缘(591,159)附近结束的所述第一CT的浅的另外的区域(66,166),由此 另一区域(60,160)中的有效通道长度(61,161)减小到接近零。 可以获得BVDSS和/或Rdson的显着改善,而不会降低对其他设备性能的其他影响或显着的不利影响。