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1. 发明授权

US09666671B2 Semiconductor device with composite drift region and related fabrication method 有权
公开(公告)号：US09666671B2
公开(公告)日：2017-05-30
申请号：US14279991
申请日：2014-05-16
申请人： Zhihong Zhang , Hongning Yang , Jiang-Kai Zuo
发明人： Zhihong Zhang , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/10 , H01L29/78 , H01L29/66 , H01L29/36 , H01L29/06 , H01L29/08 , H01L21/265
CPC分类号： H01L29/1045 , H01L21/26513 , H01L21/2652 , H01L29/0653 , H01L29/0847 , H01L29/36 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A device includes a semiconductor substrate, a body region in the semiconductor substrate having a first conductivity type and in which a channel is formed during operation, source and drain regions in the semiconductor substrate and having a second conductivity type, the source region being disposed on the body region, and a composite drift region in the semiconductor substrate, having the second conductivity type, and through which charge carriers from the source region drift to reach the drain region after passing through the channel. The composite drift region includes a first section adjacent the channel, a second section adjacent the drain region, and a third section disposed between the first and second sections. The first and second sections have a lower effective dopant concentration level than the third section.

2. 发明授权

US09496333B2 Resurf high voltage diode 有权
公开(公告)号：US09496333B2
公开(公告)日：2016-11-15
申请号：US14622068
申请日：2015-02-13
申请人： Xin Lin , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
发明人： Xin Lin , Daniel J. Blomberg , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L29/06 , H01L29/739 , H01L29/861
CPC分类号： H01L29/063 , H01L29/0649 , H01L29/0692 , H01L29/66356 , H01L29/7391 , H01L29/861
摘要： A trench-isolated RESURF diode structure (100) is provided which includes a substrate (150) in which is formed anode (130, 132) and cathode (131) contact regions separated from one another by a shallow trench isolation region (114, 115), along with a buried cathode extension region (104) formed under a RESURF anode extension region (106, 107) such that the cathode extension region (104) extends beyond the cathode contact (131) to be sandwiched between upper and lower regions (103, 106, 107) of opposite conductivity type.

3. 发明授权

US09478456B2 Semiconductor device with composite drift region 有权
标题翻译：具有复合漂移区的半导体器件
公开(公告)号：US09478456B2
公开(公告)日：2016-10-25
申请号：US13413440
申请日：2012-03-06
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L21/762 , H01L29/66 , H01L29/08 , H01L29/06
CPC分类号： H01L21/76224 , H01L29/0653 , H01L29/0847 , H01L29/66659 , H01L29/7835
摘要： A device includes a semiconductor substrate, a channel region in the semiconductor substrate having a first conductivity type, and a composite drift region in the semiconductor substrate, having a second conductivity type. The composite drift region includes a first drift region and a second drift region spaced from the channel region by the first drift region. The device further includes a drain region in the semiconductor substrate, spaced from the channel region by the composite drain region, and having the second conductivity type. The first drift region has a dopant concentration profile with a first concentration level where adjacent the channel region and a second concentration level where adjacent the second drift region, the first concentration level being higher than the second concentration level. In some embodiments, the first and second drift regions are stacked vertically, with the first drift region being shallower than the second drift region.
摘要翻译：一种器件包括半导体衬底，具有第一导电类型的半导体衬底中的沟道区域和具有第二导电类型的半导体衬底中的复合漂移区域。复合漂移区域包括第一漂移区域和第一漂移区域与沟道区域间隔开的第二漂移区域。该器件还包括在半导体衬底中的漏极区域，通过复合漏极区域与沟道区域间隔开并具有第二导电类型。第一漂移区域具有第一浓度水平的掺杂剂浓度分布，其中邻近通道区域的第一浓度水平和与第二漂移区域相邻的第二浓度水平，第一浓度水平高于第二浓度水平。在一些实施例中，第一漂移区域和第二漂移区域垂直堆叠，其中第一漂移区域比第二漂移区域浅。

4. 发明授权

US09385229B2 Semiconductor device with improved breakdown voltage 有权
标题翻译：具有提高击穿电压的半导体器件
公开(公告)号：US09385229B2
公开(公告)日：2016-07-05
申请号：US14495508
申请日：2014-09-24
申请人： Hongning Yang , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7824 , H01L29/0623 , H01L29/063 , H01L29/0634 , H01L29/0653 , H01L29/1095 , H01L29/4175 , H01L29/66659 , H01L29/66681 , H01L29/7835 , H01L29/78624
摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first region of semiconductor material having a first conductivity type and a first dopant concentration, a second region of semiconductor material having a second conductivity type overlying the first region, a drift region of semiconductor material having the first conductivity type overlying the second region, and a drain region of semiconductor material having the first conductivity type. The drift region and the drain region are electrically connected, with at least a portion of the drift region residing between the drain region and the second region, and at least a portion of the second region residing between that drift region and the first region. In one or more exemplary embodiments, the first region abuts an underlying insulating layer of dielectric material.
摘要翻译：提供半导体器件结构和相关的制造方法。示例性的半导体器件结构包括具有第一导电类型和第一掺杂剂浓度的第一半导体材料区域，具有覆盖第一区域的第二导电类型的第二半导体材料区域，具有第一导电类型的半导体材料的漂移区域覆盖第二区域，以及具有第一导电类型的半导体材料的漏极区域。漂移区域和漏极区域电连接，漂移区域的至少一部分位于漏极区域和第二区域之间，并且第二区域的至少一部分位于该漂移区域和第一区域之间。在一个或多个示例性实施例中，第一区域邻接介电材料的下层绝缘层。

5. 发明申请

US20160087096A1 SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS 有权
标题翻译：半导体器件及相关制造方法
公开(公告)号：US20160087096A1
公开(公告)日：2016-03-24
申请号：US14495508
申请日：2014-09-24
申请人： HONGNING YANG , XIN LIN , ZHIHONG ZHANG , JIANG-KAI ZUO
发明人： HONGNING YANG , XIN LIN , ZHIHONG ZHANG , JIANG-KAI ZUO
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7824 , H01L29/0623 , H01L29/063 , H01L29/0634 , H01L29/0653 , H01L29/1095 , H01L29/4175 , H01L29/66659 , H01L29/66681 , H01L29/7835 , H01L29/78624
摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure includes a first region of semiconductor material having a first conductivity type and a first dopant concentration, a second region of semiconductor material having a second conductivity type overlying the first region, a drift region of semiconductor material having the first conductivity type overlying the second region, and a drain region of semiconductor material having the first conductivity type. The drift region and the drain region are electrically connected, with at least a portion of the drift region residing between the drain region and the second region, and at least a portion of the second region residing between that drift region and the first region. In one or more exemplary embodiments, the first region abuts an underlying insulating layer of dielectric material.
摘要翻译：提供半导体器件结构和相关的制造方法。示例性的半导体器件结构包括具有第一导电类型和第一掺杂剂浓度的第一半导体材料区域，具有覆盖第一区域的第二导电类型的第二半导体材料区域，具有第一导电类型的半导体材料的漂移区域覆盖第二区域，以及具有第一导电类型的半导体材料的漏极区域。漂移区域和漏极区域电连接，漂移区域的至少一部分位于漏极区域和第二区域之间，并且第二区域的至少一部分位于该漂移区域和第一区域之间。在一个或多个示例性实施例中，第一区域邻接介电材料的下层绝缘层。

6. 发明授权

US09281375B2 Methods of producing bipolar transistors having emitter-base junctions of varying depths and/or doping concentrations 有权
标题翻译：制造具有不同深度和/或掺杂浓度的发射极 - 基结的双极型晶体管的方法
公开(公告)号：US09281375B2
公开(公告)日：2016-03-08
申请号：US14313114
申请日：2014-06-24
申请人： Xin Lin , Bernhard H. Grote , Jiang-Kai Zuo
发明人： Xin Lin , Bernhard H. Grote , Jiang-Kai Zuo
IPC分类号： H01L21/331 , H01L29/73 , H01L29/66 , H01L21/8222 , H01L21/8249 , H01L29/735 , H01L29/70
CPC分类号： H01L29/6625 , H01L21/8222 , H01L21/8249 , H01L29/705 , H01L29/7317 , H01L29/735
摘要： Methods for producing bipolar transistors are provided. In one embodiment, the method includes producing a bipolar transistor including first and second connected emitter-base (EB) junctions of varying different depths. A buried layer (BL) collector is further produced to have a third depth greater than the depths of the EB junctions. The emitters and bases corresponding to the different EB junctions are provided during a chain implant. An isolation region may overlie the second EB junction location. The BL collector is laterally spaced from the first EB junction by a variable amount to facilitate adjustment of the transistor properties. The BL collector may or may not underlie at least a portion of the second EB junction. Regions of opposite conductivity type overlie and underlie the BL collector to preserve breakdown voltage. The transistor can be readily “tuned” by mask adjustments alone to meet various device requirements.
摘要翻译：提供了制造双极晶体管的方法。在一个实施例中，该方法包括产生包括变化不同深度的第一和第二连接的发射极基极（EB）结的双极晶体管。进一步制造掩埋层（BL）集电体以具有大于EB结的深度的第三深度。在链植入期间提供对应于不同EB结的发射器和基座。隔离区域可以覆盖第二EB结点位置。 BL收集器与第一EB结横向间隔可变量以便于调整晶体管特性。 BL收集器可以或可以不位于第二EB结的至少一部分的下面。相反导电类型的区域叠加在BL集电极之下，以保持击穿电压。晶体管可以通过单独的掩模调节容易地“调谐”以满足各种器件要求。

7. 发明授权

US09231083B2 High breakdown voltage LDMOS device 有权
标题翻译：高击穿电压LDMOS器件
公开(公告)号：US09231083B2
公开(公告)日：2016-01-05
申请号：US13537619
申请日：2012-06-29
申请人： Hongning Yang , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66 , H01L29/10 , H01L29/06
CPC分类号： H01L29/66689 , H01L21/76229 , H01L21/76264 , H01L29/0653 , H01L29/1083 , H01L29/66484 , H01L29/66772 , H01L29/7824
摘要： A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep-trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).
摘要翻译：多区域（81,83）横向扩散金属氧化物半导体（LDMOS）器件（40）具有绝缘体上半导体（SOI）支撑结构（21），其上形成有基本上对称的横向内部的第一LDMOS区域（81）和基本不对称的横向边缘邻近的第二LDMOS区域（83）。深沟槽隔离（DTI）壁（60）基本上横向地终止横向边缘邻近的第二LDMOS区域（83）。通过在SOI中提供掺杂的SC掩埋层区域（86）来避免由与DTI壁（60）相关联的横向边缘邻近的第二LDMOS区域（83）表现出的电场增强和较低的源极 - 漏极击穿电压（BVDSS）靠近DTI壁（60）的支撑结构（21），位于横向边缘邻近的第二LDMOS区域（83）的一部分下方并且具有与横向边缘邻近的第二LDMOS区域的漏极区域（31）相反的导电类型 83）。

8. 发明授权

US09165918B1 Composite semiconductor device with multiple threshold voltages 有权
标题翻译：具有多个阈值电压的复合半导体器件
公开(公告)号：US09165918B1
公开(公告)日：2015-10-20
申请号：US14272027
申请日：2014-05-07
申请人： Hongning Yang , Xin Lin , Pete Rodriguez , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Pete Rodriguez , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L27/02 , H01L29/78 , H01L29/08 , H01L29/10 , H01L27/088 , H01L21/8234 , H01L21/265
CPC分类号： H01L27/0248 , H01L21/26513 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L27/0266 , H01L27/088 , H01L29/0653 , H01L29/0696 , H01L29/0865 , H01L29/0882 , H01L29/1045 , H01L29/1079 , H01L29/1095 , H01L29/66575 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures includes a non-uniform channel such that the first constituent transistor has a higher threshold voltage level than the second constituent transistor.
摘要翻译：一种器件包括半导体衬底，第一组成晶体管，其包括彼此并联连接的半导体衬底中的第一多个晶体管结构;以及第二组成晶体管，包括在半导体衬底中并联连接的第二多个晶体管结构，另一个。第一和第二组成晶体管彼此横向相邻设置并彼此并联连接。第一多个晶体管结构的每个晶体管结构包括非均匀沟道，使得第一构成晶体管具有比第二构成晶体管更高的阈值电压电平。

9. 发明授权

US09136327B1 Deep trench isolation structures and systems and methods including the same 有权
标题翻译：深沟槽隔离结构及其系统和方法包括相同
公开(公告)号：US09136327B1
公开(公告)日：2015-09-15
申请号：US14464901
申请日：2014-08-21
申请人： Xu Cheng , Daniel J. Blomberg , Jiang-Kai Zuo
发明人： Xu Cheng , Daniel J. Blomberg , Jiang-Kai Zuo
IPC分类号： H01L21/336 , H01L29/06 , H01L29/36 , H01L21/762 , H01L21/8234 , H01L27/02
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/823481 , H01L27/0203 , H01L27/0207 , H01L29/36
摘要： Deep trench isolation structures and systems and methods including the same are disclosed herein. The systems include a semiconductor device. The semiconductor device includes a semiconductor body, a device region, and the deep trench isolation structure. The deep trench isolation structure is configured to electrically isolate the device region from other device regions that extend within the semiconductor body. The deep trench isolation structure includes an isolation trench, a dielectric material that extends within the isolation trench, a first semiconducting region, and a second semiconducting region. The methods include methods of manufacturing a semiconductor device that includes the disclosed deep trench isolation structures. The methods also include methods of operating an integrated circuit device that includes a plurality of semiconductor devices that include the disclosed deep trench isolation structures.
摘要翻译：深沟槽隔离结构及其系统和方法在此公开。该系统包括半导体器件。半导体器件包括半导体本体，器件区域和深沟槽隔离结构。深沟槽隔离结构被配置为将器件区域与在半导体本体内延伸的其它器件区域电隔离。深沟槽隔离结构包括隔离沟槽，在隔离沟槽内延伸的介电材料，第一半导体区域和第二半导体区域。该方法包括制造包括所公开的深沟槽隔离结构的半导体器件的方法。所述方法还包括操作集成电路器件的方法，所述集成电路器件包括包括所公开的深沟槽隔离结构的多个半导体器件。

10. 发明授权

US09136323B2 Drain-end drift diminution in semiconductor devices 有权
标题翻译：半导体器件的漏极漂移减少
公开(公告)号：US09136323B2
公开(公告)日：2015-09-15
申请号：US14486104
申请日：2014-09-15
申请人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/06 , H01L29/66 , H01L29/78 , H01L29/08 , H01L29/10
CPC分类号： H01L29/063 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.
摘要翻译：制造晶体管的方法包括在衬底中形成场隔离区域。在形成场隔离区之后，将掺杂剂注入到用于形成漂移区的衬底的第一区域中。漏极区形成在衬底的第二区域中。第一和第二区域横向重叠以限定晶体管的导电路径。第一区域不横向跨越第二区域延伸。

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