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21. 发明申请

US20130144815A1 MAKING PREDICTIONS REGARDING EVALUATION OF FUNCTIONS FOR A DATABASE ENVIRONMENT 有权
标题翻译：制定数据库环境功能评估的预测
公开(公告)号：US20130144815A1
公开(公告)日：2013-06-06
申请号：US13310996
申请日：2011-12-05
申请人： Congnan Luo , Heng Yuan , Michael Reed
发明人： Congnan Luo , Heng Yuan , Michael Reed
IPC分类号： G06F15/18
CPC分类号： G06N99/005 , G06N5/04
摘要： A prediction regarding one or more functions can be made for a database environment. In particular, a predication can be made with respect to values stored in at least one column of at least one table in a database, based on the evaluation of one or more functions for a subset of possible column values (i.e., resultant values derived from the evaluation of a subset of possible column values) without the need to calculate the function(s) for all of the actual entries in the column of the table(s). In effect, a functional predicate can be transformed (or translated) to a predicate that is dependent on the column values instead of the evaluation of one or more functions for the column values.
摘要翻译：可以针对数据库环境进行关于一个或多个功能的预测。特别地，可以基于对可能的列值的子集的一个或多个函数的评估（即，从...得到的结果值）来估计存储在数据库中的至少一个表的至少一列中的值评估可能的列值的子集），而不需要计算表的列中所有实际条目的函数。实际上，功能谓词可以被转换（或翻译）到依赖于列值而不是对列值的一个或多个函数的评估的谓词。

22. 发明申请

US20130051119A1 RESISTIVE MEMORY AND PROGRAM VERIFICATION METHOD THEREOF 有权
标题翻译：电阻记忆和程序验证方法
公开(公告)号：US20130051119A1
公开(公告)日：2013-02-28
申请号：US13340467
申请日：2011-12-29
申请人： Heng-Yuan LEE , Yu-Sheng Chen
发明人： Heng-Yuan LEE , Yu-Sheng Chen
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2213/79
摘要： A resistive memory including a transistor and a variable resistor is disclosed. The transistor includes a gate, a source and a drain. The variable resistor is coupled between the drain and a node. During a setting period, the gate receives a first gate voltage, the source receives a first source voltage, the node receives a first drain voltage, and the first source voltage is equal to a grounding voltage. After the setting period, if a resistance value of the variable resistor is not less than a first pre-determined value, a first verification operation is performed. When the first verification operation is being performed, the gate receives a second gate voltage, the node receives a second drain voltage less than the first drain voltage, and the source receives a second source voltage equal to the grounding voltage.
摘要翻译：公开了一种包括晶体管和可变电阻器的电阻存储器。晶体管包括栅极，源极和漏极。可变电阻耦合在漏极和节点之间。在设定期间，栅极接收第一栅极电压，源极接收第一源电压，节点接收第一漏极电压，第一源极电压等于接地电压。在设定期间后，如果可变电阻器的电阻值不小于第一预定值，则执行第一验证操作。当执行第一验证操作时，门接收第二栅极电压，节点接收小于第一漏极电压的第二漏极电压，并且源接收等于接地电压的第二源极电压。

23. 发明申请

US20090038207A1 Mosquito-killing LED lamp 审中-公开
标题翻译：杀蚊灯LED灯
公开(公告)号：US20090038207A1
公开(公告)日：2009-02-12
申请号：US11882860
申请日：2007-08-06
申请人： Heng-Yuan Lin
发明人： Heng-Yuan Lin
IPC分类号： A01M1/04 , A01M1/22
CPC分类号： A01M1/04 , A01M1/223 , A01M2200/012
摘要： A mosquito-killing LED lamp also serving as a lighting fixture includes an LED light source, one or a plurality of light board comprised of multiple UV LEDs and multiple visible light LED arranged in array; a power supply combined in modular with the LED light source to output power to drive those UV and visible light LEDs; and a casing containing the light board, one or a plurality of electric shock mesh holding against the light board, and one or a plurality of barrier on a surface of the casing; the power supply being electrically connected to one or a plurality of high voltage transformer, which in turn being electrically connected to the electric shock mesh to seduce and killing mosquitoes.
摘要翻译：作为照明灯具的杀虫LED灯具包括LED光源，由多个UV LED组成的一个或多个灯板和排列成阵列的多个可见光LED; 与LED光源组合的电源，输出功率以驱动这些UV和可见光LED; 以及容纳所述灯板的壳体，保持在所述灯板上的一个或多个电击网，以及在所述壳体的表面上的一个或多个屏障; 所述电源电连接到一个或多个高压变压器，所述高压变压器又电连接到所述电击网以引诱和杀死蚊子。

24. 发明申请

US20070161185A1 Method of manufacturing charge storage device 失效
标题翻译：制造电荷存储装置的方法
公开(公告)号：US20070161185A1
公开(公告)日：2007-07-12
申请号：US11407440
申请日：2006-04-19
申请人： Chieh-Shuo Liang , Pei-Jer Tzeng , Heng-Yuan Lee , Lurng-Shehng Lee
发明人： Chieh-Shuo Liang , Pei-Jer Tzeng , Heng-Yuan Lee , Lurng-Shehng Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/02148 , H01L21/02159 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02274 , H01L21/0228 , H01L21/31111 , H01L21/3142 , H01L21/31625 , H01L27/10852 , H01L28/84
摘要： A method of manufacturing a charge storage device is provided. Utilizing the capacity for a precise control of the thickness and the silicon content of a deposited film in an atomic layer deposition process, a stacked gradual material layer such as a hafnium silicon oxide (HfxSiyOz) layer is formed. The silicon content is gradually changed throughout the duration of the HfxSiyOz deposition process. The etching rate for the HfxSiyOz layer in dilute hydrogen fluoride solution is dependent on the silicon content y in the HfxSiyOz layer. The sidewalls of the stacked gradual material layer are etched to form an uneven profile. The lower electrode, the capacitor dielectric layer and the upper electrode are formed on the uneven sidewalls of the stacked gradual material layers, the area between the lower electrode and the upper electrode is increased to improve the capacitance of the charge storage device.
摘要翻译：提供一种制造电荷存储装置的方法。利用在原子层沉积工艺中精确控制沉积膜的厚度和硅含量的能力，可以使用叠层的梯度材料层，例如氧化铪铪（Hf x Si x Si 形成层）。在整个沉积过程的整个持续时间内，硅含量逐渐变化。稀氟化氢溶液中的Hf x Si 3 O z O z层的蚀刻速率取决于Hf x _{Si O z层。层叠的逐层材料层的侧壁被蚀刻以形成不均匀的轮廓。下部电极，电容器电介质层和上部电极形成在层叠的逐层材料层的不均匀侧壁上，增加了下部电极和上部电极之间的面积，以提高电荷存储装置的电容。}

25. 发明授权

US08750016B2 Resistive memory and program verification method thereof 有权
标题翻译：电阻记忆及其程序验证方法
公开(公告)号：US08750016B2
公开(公告)日：2014-06-10
申请号：US13340467
申请日：2011-12-29
申请人： Heng-Yuan Lee , Yu-Sheng Chen
发明人： Heng-Yuan Lee , Yu-Sheng Chen
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2213/79
摘要： A resistive memory including a transistor and a variable resistor is disclosed. The transistor includes a gate, a source and a drain. The variable resistor is coupled between the drain and a node. During a setting period, the gate receives a first gate voltage, the source receives a first source voltage, the node receives a first drain voltage, and the first source voltage is equal to a grounding voltage. After the setting period, if a resistance value of the variable resistor is not less than a first pre-determined value, a first verification operation is performed. When the first verification operation is being performed, the gate receives a second gate voltage, the node receives a second drain voltage less than the first drain voltage, and the source receives a second source voltage equal to the grounding voltage.
摘要翻译：公开了一种包括晶体管和可变电阻器的电阻存储器。晶体管包括栅极，源极和漏极。可变电阻耦合在漏极和节点之间。在设定期间，栅极接收第一栅极电压，源极接收第一源电压，节点接收第一漏极电压，第一源极电压等于接地电压。在设定期间后，如果可变电阻器的电阻值不小于第一预定值，则执行第一验证操作。当正在执行第一验证操作时，门接收第二栅极电压，节点接收小于第一漏极电压的第二漏极电压，并且源接收等于接地电压的第二源极电压。

26. 发明申请

US20120243346A1 Control Method for Memory Cell 有权
标题翻译：存储单元控制方法
公开(公告)号：US20120243346A1
公开(公告)日：2012-09-27
申请号：US13488937
申请日：2012-06-05
申请人： Yu-Sheng CHEN , Heng-Yuan LEE , Yen-Ya HSU , Pang-Shiu CHEN , Ching-Chih HSU , Frederick T. CHEN
发明人： Yu-Sheng CHEN , Heng-Yuan LEE , Yen-Ya HSU , Pang-Shiu CHEN , Ching-Chih HSU , Frederick T. CHEN
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0064 , G11C2013/0071 , G11C2013/0073 , G11C2213/79
摘要： A control method for at least one memory cell. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state.
摘要翻译：一种用于至少一个存储单元的控制方法。存储单元包括晶体管和电阻器。电阻器在第一节点和第二节点之间串联连接到晶体管。在编程模式下，存储单元被编程。当确定存储器单元已被成功编程时，存储器单元的阻抗处于第一状态。当确定存储器单元未被成功编程时，执行特定动作来重置存储器单元。在步骤重置存储单元之后，存储单元的阻抗处于第二状态。第二状态下的存储单元的阻抗高于第一状态下的存储单元的阻抗。

27. 发明授权

US07851843B2 DRAM cylindrical capacitor 有权
标题翻译： DRAM圆柱形电容器
公开(公告)号：US07851843B2
公开(公告)日：2010-12-14
申请号：US12248041
申请日：2008-10-08
申请人： Heng-Yuan Lee , Chieh-Shuo Liang , Lurng-Shehng Lee
发明人： Heng-Yuan Lee , Chieh-Shuo Liang , Lurng-Shehng Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10852 , H01L28/82
摘要： A structure of a DRAM cylindrical capacitor includes a substrate, a dielectric layer, an amorphous silicon spacer, a polysilicon plug, a HSG layer, a conductive layer and a capacitor dielectric layer. The dielectric layer is disposed on the substrate and includes an opening. The amorphous silicon spacer is disposed on the sidewall of the opening, wherein the polysilicon plug is exposed by the opening. The polysilicon plug includes a notch, and the internal surface of the notch is at the same plane as the internal surface of the amorphous silicon spacer. The HSG layer is disposed on the surface of the amorphous silicon spacer. Furthermore, the conductive layer is disposed on the HSG layer and the capacitor dielectric layer is disposed between the HSG layer and the conductive layer.
摘要翻译： DRAM圆柱形电容器的结构包括基板，电介质层，非晶硅间隔物，多晶硅插塞，HSG层，导电层和电容器电介质层。电介质层设置在基板上并且包括开口。非晶硅间隔件设置在开口的侧壁上，其中多晶硅插塞由开口暴露。多晶硅插塞包括凹口，并且凹口的内表面处于与非晶硅间隔物的内表面相同的平面。 HSG层设置在非晶硅间隔物的表面上。此外，导电层设置在HSG层上，电容器介电层设置在HSG层和导电层之间。

28. 发明申请

US20090026518A1 DRAM CYLINDRICAL CAPACITOR 有权
标题翻译： DRAM圆柱电容器
公开(公告)号：US20090026518A1
公开(公告)日：2009-01-29
申请号：US12248041
申请日：2008-10-08
申请人： Heng-Yuan Lee , Chieh-Shuo Liang , Lurng-Shehng Lee
发明人： Heng-Yuan Lee , Chieh-Shuo Liang , Lurng-Shehng Lee
IPC分类号： H01L27/108 , H01L29/92
CPC分类号： H01L27/10852 , H01L28/82
摘要： A structure of a DRAM cylindrical capacitor includes a substrate, a dielectric layer, an amorphous silicon spacer, a polysilicon plug, a HSG layer, a conductive layer and a capacitor dielectric layer. The dielectric layer is disposed on the substrate and includes an opening. The amorphous silicon spacer is disposed on the sidewall of the opening, wherein the polysilicon plug is exposed by the opening. The polysilicon plug includes a notch, and the internal surface of the notch is at the same plane as the internal surface of the amorphous silicon spacer. The HSG layer is disposed on the surface of the amorphous silicon spacer. Furthermore, the conductive layer is disposed on the HSG layer and the capacitor dielectric layer is disposed between the HSG layer and the conductive layer.
摘要翻译： DRAM圆柱形电容器的结构包括基板，电介质层，非晶硅间隔物，多晶硅插塞，HSG层，导电层和电容器电介质层。电介质层设置在基板上并且包括开口。非晶硅间隔件设置在开口的侧壁上，其中多晶硅插塞由开口暴露。多晶硅插塞包括凹口，并且凹口的内表面处于与非晶硅间隔物的内表面相同的平面。 HSG层设置在非晶硅间隔物的表面上。此外，导电层设置在HSG层上，电容器介电层设置在HSG层和导电层之间。

29. 发明申请

US20080094776A1 CYLINDRICAL CAPACITOR 审中-公开
标题翻译：圆柱电容器
公开(公告)号：US20080094776A1
公开(公告)日：2008-04-24
申请号：US11960726
申请日：2007-12-20
申请人： Heng-Yuan Lee , Ching-Yuan Ho , Lurng-Shehng Lee , Chieh-Shuo Liang
发明人： Heng-Yuan Lee , Ching-Yuan Ho , Lurng-Shehng Lee , Chieh-Shuo Liang
IPC分类号： H01G4/00
CPC分类号： H01L28/40
摘要： A cylindrical capacitor comprising at least a substrate, a cylindrical bottom electrode, a structure layer, a top electrode and a capacitor dielectric layer is provided. The substrate has several plugs. The cylindrical bottom electrodes are disposed on the substrate and electrically connected to the respective plugs. The structure layer surrounds the periphery of each cylindrical bottom electrode. The structure layers that surround the two opposing cylindrical bottom electrodes have no mutual contact while the structure layers that surround two neighboring cylindrical bottom electrodes contact each other. Furthermore, the top electrodes cover the respective cylindrical bottom electrodes and the capacitor dielectric layer is disposed between each top electrode and corresponding cylindrical bottom electrode. Due to the structure layers, the mechanical strength of the whole cylindrical capacitor is improved and the density of the capacitor can be increased.
摘要翻译：提供了至少包括基板，圆柱形底电极，结构层，顶电极和电容器介电层的圆柱形电容器。基板有几个插头。圆柱形底部电极设置在基板上并电连接到相应的插头。结构层围绕每个圆柱形底部电极的周边。围绕两个相对的圆柱形底部电极的结构层不会相互接触，而围绕两个相邻的圆柱形底部电极的结构层彼此接触。此外，顶部电极覆盖相应的圆柱形底部电极，并且电容器介电层设置在每个顶部电极和相应的圆柱形底部电极之间。由于结构层，提高了整个圆柱形电容器的机械强度，并且可以增加电容器的密度。

30. 外观设计

USD544566S1 Insect-catcher 有权
标题翻译：捕虫器
公开(公告)号：USD544566S1
公开(公告)日：2007-06-12
申请号：US29265844
申请日：2006-09-11
申请人： Heng-Yuan Lin
设计人： Heng-Yuan Lin

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