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1. 发明申请

US20130001494A1 Memory Cell 有权
标题翻译：内存单元
公开(公告)号：US20130001494A1
公开(公告)日：2013-01-03
申请号：US13173945
申请日：2011-06-30
申请人： Frederick T. Chen , Heng-Yuan Lee , Yu-Sheng Chen
发明人： Frederick T. Chen , Heng-Yuan Lee , Yu-Sheng Chen
IPC分类号： H01L45/00
CPC分类号： G11C13/0007 , G11C13/003 , G11C2213/15 , G11C2213/32 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/2418 , H01L27/2427 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/146
摘要： A memory cell includes a memory element, a current-limiting element electrically coupled to the memory element, and a high-selection-ratio element electrically coupled to the current-limiting element. The memory element is configured to store data as a resistance state. The current-limiting element is a voltage-controlled resistor (VCR) having a resistance that decreases when a voltage applied thereto increases. The high-selection-ratio element has a first resistance that is small when a voltage applied to the memory cell is approximately equal to a selection voltage of the memory cell, and has a second resistance that is substantially larger than the first resistance when the voltage applied to the memory cell is approximately equal to one-half of the selection voltage.
摘要翻译：存储单元包括存储元件，电耦合到存储元件的限流元件，以及电耦合到限流元件的高选择比元件。存储元件被配置为将数据存储为电阻状态。限流元件是具有当施加的电压增加时电阻降低的压控电阻器（VCR）。高选择比元件在施加到存储单元的电压近似等于存储单元的选择电压时具有小的第一电阻，并且具有比电压的第一电阻显着大于第一电阻的第二电阻施加到存储单元大约等于选择电压的一半。

2. 发明申请

US20130051119A1 RESISTIVE MEMORY AND PROGRAM VERIFICATION METHOD THEREOF 有权
标题翻译：电阻记忆和程序验证方法
公开(公告)号：US20130051119A1
公开(公告)日：2013-02-28
申请号：US13340467
申请日：2011-12-29
申请人： Heng-Yuan LEE , Yu-Sheng Chen
发明人： Heng-Yuan LEE , Yu-Sheng Chen
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2213/79
摘要： A resistive memory including a transistor and a variable resistor is disclosed. The transistor includes a gate, a source and a drain. The variable resistor is coupled between the drain and a node. During a setting period, the gate receives a first gate voltage, the source receives a first source voltage, the node receives a first drain voltage, and the first source voltage is equal to a grounding voltage. After the setting period, if a resistance value of the variable resistor is not less than a first pre-determined value, a first verification operation is performed. When the first verification operation is being performed, the gate receives a second gate voltage, the node receives a second drain voltage less than the first drain voltage, and the source receives a second source voltage equal to the grounding voltage.
摘要翻译：公开了一种包括晶体管和可变电阻器的电阻存储器。晶体管包括栅极，源极和漏极。可变电阻耦合在漏极和节点之间。在设定期间，栅极接收第一栅极电压，源极接收第一源电压，节点接收第一漏极电压，第一源极电压等于接地电压。在设定期间后，如果可变电阻器的电阻值不小于第一预定值，则执行第一验证操作。当执行第一验证操作时，门接收第二栅极电压，节点接收小于第一漏极电压的第二漏极电压，并且源接收等于接地电压的第二源极电压。

3. 发明授权

US08750016B2 Resistive memory and program verification method thereof 有权
标题翻译：电阻记忆及其程序验证方法
公开(公告)号：US08750016B2
公开(公告)日：2014-06-10
申请号：US13340467
申请日：2011-12-29
申请人： Heng-Yuan Lee , Yu-Sheng Chen
发明人： Heng-Yuan Lee , Yu-Sheng Chen
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2213/79
摘要： A resistive memory including a transistor and a variable resistor is disclosed. The transistor includes a gate, a source and a drain. The variable resistor is coupled between the drain and a node. During a setting period, the gate receives a first gate voltage, the source receives a first source voltage, the node receives a first drain voltage, and the first source voltage is equal to a grounding voltage. After the setting period, if a resistance value of the variable resistor is not less than a first pre-determined value, a first verification operation is performed. When the first verification operation is being performed, the gate receives a second gate voltage, the node receives a second drain voltage less than the first drain voltage, and the source receives a second source voltage equal to the grounding voltage.
摘要翻译：公开了一种包括晶体管和可变电阻器的电阻存储器。晶体管包括栅极，源极和漏极。可变电阻耦合在漏极和节点之间。在设定期间，栅极接收第一栅极电压，源极接收第一源电压，节点接收第一漏极电压，第一源极电压等于接地电压。在设定期间后，如果可变电阻器的电阻值不小于第一预定值，则执行第一验证操作。当正在执行第一验证操作时，门接收第二栅极电压，节点接收小于第一漏极电压的第二漏极电压，并且源接收等于接地电压的第二源极电压。

4. 发明授权

US08711601B2 Resistive random access memory cell and resistive random access memory module 有权
标题翻译：电阻随机存取存储单元和电阻随机存取存储器模块
公开(公告)号：US08711601B2
公开(公告)日：2014-04-29
申请号：US13338264
申请日：2011-12-28
申请人： Frederick T. Chen , Heng-Yuan Lee , Yu-Sheng Chen
发明人： Frederick T. Chen , Heng-Yuan Lee , Yu-Sheng Chen
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0071 , G11C2213/51 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： A resistive random access memory (RRAM) cell including a first electrode, a second electrode, and a plurality of repeated sets of layers is provided. Each of the sets of layers includes a resistance-changing layer, a barrier layer, and an ionic exchange layer between the resistance-changing layer and the barrier layer, wherein a thickness of each of the resistance-changing layer, the barrier layer and the ionic exchange layer exceeds a Fermi wavelength, and the thickness each of the resistance-changing layer and ionic exchange layer are less than an electron mean free path. Further, a RRAM module including the aforesaid RRAM cell and a switch is also provided.
摘要翻译：提供了包括第一电极，第二电极和多个重复的层的电阻随机存取存储器（RRAM）单元。电阻变化层和阻挡层中的每个层包括电阻变化层，阻挡层和电阻变化层与阻挡层之间的离子交换层，其中电阻变化层，阻挡层和阻挡层离子交换层超过费米波长，电阻变化层和离子交换层的厚度均小于电子平均自由程。此外，还提供了包括上述RRAM单元和开关的RRAM模块。

5. 发明申请

US20140077149A1 RESISTANCE MEMORY CELL, RESISTANCE MEMORY ARRAY AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：电阻记忆体，电阻记忆阵列及其形成方法
公开(公告)号：US20140077149A1
公开(公告)日：2014-03-20
申请号：US13615683
申请日：2012-09-14
申请人： Frederick T. Chen , Heng-Yuan Lee , Yu-Sheng Chen , Wei-Su Chen , Tai-Yuan Wu , Pang-Hsu Chen
发明人： Frederick T. Chen , Heng-Yuan Lee , Yu-Sheng Chen , Wei-Su Chen , Tai-Yuan Wu , Pang-Hsu Chen
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： G11C13/0007 , G11C2213/15 , G11C2213/56 , H01L27/2436 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146
摘要： A resistance memory cell including a variable resistance layer is provided. The variable resistance layer includes at least one dominant resistance layer and at least one auxiliary resistance layer. The dominant resistance layer(s) and the auxiliary resistance layer(s) in totality form a closed ion exchange system, the exchanged ions are comparably mobile in each of the dominant resistance layer(s) and the auxiliary resistance layer(s), and the maximum resistance of the at least one dominant resistance layer is higher than that of the at least one auxiliary resistance layer.
摘要翻译：提供了包括可变电阻层的电阻存储单元。可变电阻层包括至少一个显性电阻层和至少一个辅助电阻层。主要电阻层和辅助电阻层总体上形成封闭的离子交换系统，交换的离子在每个主要电阻层和辅助电阻层中是可比较的，以及至少一个主要电阻层的最大电阻高于至少一个辅助电阻层的最大电阻。

6. 发明授权

US08642985B2 Memory Cell 有权
标题翻译：内存单元
公开(公告)号：US08642985B2
公开(公告)日：2014-02-04
申请号：US13173945
申请日：2011-06-30
申请人： Frederick T. Chen , Heng-Yuan Lee , Yu-Sheng Chen
发明人： Frederick T. Chen , Heng-Yuan Lee , Yu-Sheng Chen
IPC分类号： H01L45/00
CPC分类号： G11C13/0007 , G11C13/003 , G11C2213/15 , G11C2213/32 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/2418 , H01L27/2427 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/146
摘要： A memory cell includes a memory element, a current-limiting element electrically coupled to the memory element, and a high-selection-ratio element electrically coupled to the current-limiting element. The memory element is configured to store data as a resistance state. The current-limiting element is a voltage-controlled resistor (VCR) having a resistance that decreases when a voltage applied thereto increases. The high-selection-ratio element has a first resistance that is small when a voltage applied to the memory cell is approximately equal to a selection voltage of the memory cell, and has a second resistance that is substantially larger than the first resistance when the voltage applied to the memory cell is approximately equal to one-half of the selection voltage.
摘要翻译：存储单元包括存储元件，电耦合到存储元件的限流元件，以及电耦合到限流元件的高选择比元件。存储元件被配置为将数据存储为电阻状态。限流元件是具有当施加的电压增加时电阻降低的压控电阻器（VCR）。高选择比元件在施加到存储单元的电压近似等于存储单元的选择电压时具有小的第一电阻，并且具有比电压的第一电阻显着大于第一电阻的第二电阻施加到存储单元大约等于选择电压的一半。

7. 发明授权

US08223528B2 Control method for memory cell 有权
标题翻译：存储单元的控制方法
公开(公告)号：US08223528B2
公开(公告)日：2012-07-17
申请号：US12649286
申请日：2009-12-29
申请人： Yu-Sheng Chen , Heng-Yuan Lee , Yen-Ya Hsu , Pang-Shiu Chen , Ching-Chih Hsu
发明人： Yu-Sheng Chen , Heng-Yuan Lee , Yen-Ya Hsu , Pang-Shiu Chen , Ching-Chih Hsu
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0064 , G11C2013/0071 , G11C2013/0073 , G11C2213/79
摘要： A control method for at least one memory cell is disclosed. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor between a first node and a second node. In a programming mode, the memory cell is programmed. The step of programming the memory cell includes providing a first controlling voltage to a gate of the transistor, providing a first setting voltage to the first node, and providing a second setting voltage to the second node. When it is determined that the memory cell has been successfully programmed, a specific action is executed.
摘要翻译：公开了至少一个存储单元的控制方法。存储单元包括晶体管和电阻器。电阻器连接到第一节点和第二节点之间的晶体管。在编程模式下，存储单元被编程。编程存储单元的步骤包括向晶体管的栅极提供第一控制电压，向第一节点提供第一设定电压，并向第二节点提供第二设定电压。当确定存储器单元已被成功编程时，执行特定动作。

8. 发明授权

US08817521B2 Control method for memory cell 有权
标题翻译：存储单元的控制方法
公开(公告)号：US08817521B2
公开(公告)日：2014-08-26
申请号：US13488937
申请日：2012-06-05
申请人： Yu-Sheng Chen , Heng-Yuan Lee , Yen-Ya Hsu , Pang-Shiu Chen , Ching-Chih Hsu , Frederick T. Chen
发明人： Yu-Sheng Chen , Heng-Yuan Lee , Yen-Ya Hsu , Pang-Shiu Chen , Ching-Chih Hsu , Frederick T. Chen
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0064 , G11C2013/0071 , G11C2013/0073 , G11C2213/79
摘要： A control method for at least one memory cell is disclosed. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state.
摘要翻译：公开了至少一个存储单元的控制方法。存储单元包括晶体管和电阻器。电阻器在第一节点和第二节点之间串联连接到晶体管。在编程模式下，存储单元被编程。当确定存储器单元已被成功编程时，存储器单元的阻抗处于第一状态。当确定存储器单元未成功编程时，执行特定动作来重置存储器单元。在步骤重置存储单元之后，存储单元的阻抗处于第二状态。第二状态下的存储单元的阻抗高于第一状态下的存储单元的阻抗。

9. 发明申请

US20130170278A1 RESISTIVE RANDOM ACCESS MEMORY CELL AND RESISTIVE RANDOM ACCESS MEMORY MODULE 有权
标题翻译：电阻随机访问存储器单元和电阻随机访问存储器模块
公开(公告)号：US20130170278A1
公开(公告)日：2013-07-04
申请号：US13338264
申请日：2011-12-28
申请人： Frederick T. Chen , Heng-Yuan Lee , Yu-Sheng Chen
发明人： Frederick T. Chen , Heng-Yuan Lee , Yu-Sheng Chen
IPC分类号： G11C11/21 , H01L45/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0071 , G11C2213/51 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： A resistive random access memory (RRAM) cell including a first electrode, a second electrode, and a plurality of repeated sets of layers is provided. Each of the sets of layers includes a resistance-changing layer, a barrier layer, and an ionic exchange layer between the resistance-changing layer and the barrier layer, wherein a thickness of each of the resistance-changing layer, the barrier layer and the ionic exchange layer exceeds a Fermi wavelength, and the thickness each of the resistance-changing layer and ionic exchange layer are less than an electron mean free path. Further, a RRAM module including the aforesaid RRAM cell and a switch is also provided.
摘要翻译：提供了包括第一电极，第二电极和多个重复的层的电阻随机存取存储器（RRAM）单元。电阻变化层和阻挡层中的每个层包括电阻变化层，阻挡层和电阻变化层与阻挡层之间的离子交换层，其中电阻变化层，阻挡层和阻挡层离子交换层超过费米波长，电阻变化层和离子交换层的厚度均小于电子平均自由程。此外，还提供了包括上述RRAM单元和开关的RRAM模块。

10. 发明授权

US07855571B2 Testing circuit board for preventing tested chip positions from being wrongly positioned 有权
标题翻译：测试电路板，用于防止测试芯片位置错误定位
公开(公告)号：US07855571B2
公开(公告)日：2010-12-21
申请号：US12100189
申请日：2008-04-09
申请人： Cheng-Yung Teng , Shao-Tien Kan , Yu-Sheng Chen
发明人： Cheng-Yung Teng , Shao-Tien Kan , Yu-Sheng Chen
IPC分类号： G01R31/28
CPC分类号： G01R31/2889
摘要： A testing circuit board used in a testing system with a tester and a handler is disclosed. The testing circuit board is used for transmitting a plurality of testing signals provided by the tester to test at least two devices under test located on the handler. The testing circuit board includes a connecting board, a load board and at least two connecting interfaces. The connecting board coupled to the handler has at least two connecting sockets for respectively connecting to the devices under testing. The load board coupled to the tester has two joining sockets located corresponding to the connecting sockets. The at least two connecting interfaces are coupled between the connecting sockets and the joining sockets for transmitting the testing signals for testing the devices under testing.
摘要翻译：公开了一种用于具有测试器和处理器的测试系统中的测试电路板。测试电路板用于发送由测试仪提供的多个测试信号，以测试处理器上的至少两个被测设备。测试电路板包括连接板，负载板和至少两个连接接口。耦合到处理器的连接板具有至少两个用于分别连接到被测设备的连接插座。耦合到测试器的负载板具有对应于连接插座定位的两个连接插座。所述至少两个连接接口连接在所述连接插座和所述连接插座之间，用于传送用于测试被测设备的测试信号。

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