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1. 发明申请

US20120243346A1 Control Method for Memory Cell 有权
标题翻译：存储单元控制方法
公开(公告)号：US20120243346A1
公开(公告)日：2012-09-27
申请号：US13488937
申请日：2012-06-05
申请人： Yu-Sheng CHEN , Heng-Yuan LEE , Yen-Ya HSU , Pang-Shiu CHEN , Ching-Chih HSU , Frederick T. CHEN
发明人： Yu-Sheng CHEN , Heng-Yuan LEE , Yen-Ya HSU , Pang-Shiu CHEN , Ching-Chih HSU , Frederick T. CHEN
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0064 , G11C2013/0071 , G11C2013/0073 , G11C2213/79
摘要： A control method for at least one memory cell. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state.
摘要翻译：一种用于至少一个存储单元的控制方法。存储单元包括晶体管和电阻器。电阻器在第一节点和第二节点之间串联连接到晶体管。在编程模式下，存储单元被编程。当确定存储器单元已被成功编程时，存储器单元的阻抗处于第一状态。当确定存储器单元未被成功编程时，执行特定动作来重置存储器单元。在步骤重置存储单元之后，存储单元的阻抗处于第二状态。第二状态下的存储单元的阻抗高于第一状态下的存储单元的阻抗。

2. 发明申请

US20110122714A1 Control Method For Memory Cell 有权
标题翻译：存储单元控制方法
公开(公告)号：US20110122714A1
公开(公告)日：2011-05-26
申请号：US12649286
申请日：2009-12-29
申请人： Yu-Sheng CHEN , Heng-Yuan LEE , Yen-Ya HSU , Pang-Shiu CHEN , Ching-Chih HSU
发明人： Yu-Sheng CHEN , Heng-Yuan LEE , Yen-Ya HSU , Pang-Shiu CHEN , Ching-Chih HSU
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C13/0064 , G11C2013/0071 , G11C2013/0073 , G11C2213/79
摘要： A control method for at least one memory cell is disclosed. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor between a first node and a second node. In a programming mode, the memory cell is programmed. The step of programming the memory cell includes providing a first controlling voltage to a gate of the transistor, providing a first setting voltage to the first node, and providing a second setting voltage to the second node. When it is determined that the memory cell has been successfully programmed, a specific action is executed.
摘要翻译：公开了至少一个存储单元的控制方法。存储单元包括晶体管和电阻器。电阻器连接到第一节点和第二节点之间的晶体管。在编程模式下，存储单元被编程。编程存储单元的步骤包括向晶体管的栅极提供第一控制电压，向第一节点提供第一设定电压，并向第二节点提供第二设定电压。当确定存储器单元已被成功编程时，执行特定动作。

3. 发明申请

US20130051119A1 RESISTIVE MEMORY AND PROGRAM VERIFICATION METHOD THEREOF 有权
标题翻译：电阻记忆和程序验证方法
公开(公告)号：US20130051119A1
公开(公告)日：2013-02-28
申请号：US13340467
申请日：2011-12-29
申请人： Heng-Yuan LEE , Yu-Sheng Chen
发明人： Heng-Yuan LEE , Yu-Sheng Chen
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0071 , G11C2213/79
摘要： A resistive memory including a transistor and a variable resistor is disclosed. The transistor includes a gate, a source and a drain. The variable resistor is coupled between the drain and a node. During a setting period, the gate receives a first gate voltage, the source receives a first source voltage, the node receives a first drain voltage, and the first source voltage is equal to a grounding voltage. After the setting period, if a resistance value of the variable resistor is not less than a first pre-determined value, a first verification operation is performed. When the first verification operation is being performed, the gate receives a second gate voltage, the node receives a second drain voltage less than the first drain voltage, and the source receives a second source voltage equal to the grounding voltage.
摘要翻译：公开了一种包括晶体管和可变电阻器的电阻存储器。晶体管包括栅极，源极和漏极。可变电阻耦合在漏极和节点之间。在设定期间，栅极接收第一栅极电压，源极接收第一源电压，节点接收第一漏极电压，第一源极电压等于接地电压。在设定期间后，如果可变电阻器的电阻值不小于第一预定值，则执行第一验证操作。当执行第一验证操作时，门接收第二栅极电压，节点接收小于第一漏极电压的第二漏极电压，并且源接收等于接地电压的第二源极电压。

4. 发明申请

US20090191685A1 METHOD FOR FORMING CAPACITOR IN DYNAMIC RANDOM ACCESS MEMORY 有权
标题翻译：在动态随机存取存储器中形成电容器的方法
公开(公告)号：US20090191685A1
公开(公告)日：2009-07-30
申请号：US12179996
申请日：2008-07-25
申请人： Heng-Yuan LEE , Ching-Chiun WANG , Tai-Yuan WU
发明人： Heng-Yuan LEE , Ching-Chiun WANG , Tai-Yuan WU
IPC分类号： H01L21/334
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L27/10855
摘要： A method for forming a capacitor in a dynamic random access memory, comprising steps of: providing a semiconductor substrate having at least a transistor, whereon an interlayer dielectric layer having at least a first plug is formed so that the first plug is connected to the drain of the transistor; depositing an etching stop layer on the first plug and the interlayer dielectric layer; depositing a first insulating layer on the etching stop layer; forming at least a second plug on the first insulating layer and the etching stop layer so that the second plug is connected to the first plug; depositing a second insulating layer on the first insulating layer and the second plug; forming at least a mold cavity in the second insulating layer so that the aperture of the mold cavity is larger than the diameter of the second plug and there is a deviation between the mold cavity and the second plug; removing the first insulating layer in the mold cavity until the etching stop layer; depositing a first electrode layer to cover the second insulating layer, a sidewall portion of the mold cavity, the second plug and the etching stop layer; removing the second insulating layer so that the first electrode layer forms a single open-ended cavity; and depositing a dielectric layer and a second electrode layer.
摘要翻译：一种用于在动态随机存取存储器中形成电容器的方法，包括以下步骤：提供至少具有晶体管的半导体衬底，其中形成至少具有第一插塞的层间介电层，使得第一插头连接到漏极的晶体管; 在所述第一插塞和所述层间电介质层上沉积蚀刻停止层; 在所述蚀刻停止层上沉积第一绝缘层; 在所述第一绝缘层和所述蚀刻停止层上形成至少第二插头，使得所述第二插头连接到所述第一插头; 在第一绝缘层和第二插塞上沉积第二绝缘层; 在所述第二绝缘层中至少形成模腔，使得所述模腔的孔径大于所述第二插塞的直径，并且所述模腔和所述第二插塞之间存在偏差; 去除模腔中的第一绝缘层直到蚀刻停止层; 沉积第一电极层以覆盖第二绝缘层，模腔的侧壁部分，第二插塞和蚀刻停止层; 去除第二绝缘层，使得第一电极层形成单个开口腔; 以及沉积介电层和第二电极层。

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