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21. 发明授权

US06974334B2 Semiconductor package with connector 有权
标题翻译：半导体封装带连接器
公开(公告)号：US06974334B2
公开(公告)日：2005-12-13
申请号：US10680209
申请日：2003-10-08
申请人： Chih-Pin Hung
发明人： Chih-Pin Hung
IPC分类号： H01R12/16 , H05K1/18 , H01R12/00
CPC分类号： H05K1/181 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2924/00014 , H01L2924/15311 , H01R12/7076 , H01R12/714 , H01R12/716 , H05K2201/10492 , H05K2201/10734 , Y02P70/611 , Y10S439/945 , H01L2924/00 , H01L2224/0401
摘要： A package for being electrically connected to an external printed wiring board and an external electronic device comprises a substrate, a semiconductor chip, a mold compound, and a connector. The substrate is electrically connected to the external printed wiring board. The semiconductor chip is disposed on and electrically connected to the substrate. The molding compound is used for encapsulating the semiconductor chip. The connector is disposed on the substrate for electrically connecting the semiconductor chip to the external electronic device.
摘要翻译：用于电连接到外部印刷线路板和外部电子装置的封装包括基板，半导体芯片，模具复合体和连接器。基板电连接到外部印刷电路板。半导体芯片设置在基板上并电连接到基板。模塑料用于封装半导体芯片。连接器设置在基板上，用于将半导体芯片电连接到外部电子设备。

22. 发明授权

US06844617B2 Packaging mold with electrostatic discharge protection 有权
标题翻译：包装模具具有静电放电保护功能
公开(公告)号：US06844617B2
公开(公告)日：2005-01-18
申请号：US10292303
申请日：2002-11-12
申请人： Chih-Pin Hung , Juang-Sheng Chiang
发明人： Chih-Pin Hung , Juang-Sheng Chiang
IPC分类号： H01L21/56 , H01L23/552 , H01L23/48 , H01R13/02
CPC分类号： H01L21/565 , H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a packaging mold with electrostatic discharge protection, comprising at least one recess for receiving at least one packaging substrate, the packaging substrate comprising an outer wall with a first height, the recess comprising an inner wall with a second height and the inner wall electrically connecting the outer wall of the packaging substrate, wherein the second height is larger than the first height. When separating the packaging substrate and the packaging mold, the duration of the outer wall connecting to the inner wall is extended, so that static electric charges generated when separating are conducted via the packaging mold preventing the dice to be packaged from damage due to electrostatic discharge to raise the yield rate of semiconductor package products thereby.
摘要翻译：本发明涉及一种具有静电放电保护的包装模具，包括至少一个用于容纳至少一个包装衬底的凹部，所述包装衬底包括具有第一高度的外壁，所述凹部包括具有第二高度的内壁，所述内壁电连接所述包装基板的外壁，其中所述第二高度大于所述第一高度。当分离包装基材和包装模具时，连接到内壁的外壁的持续时间延长，使得当分离时产生的静电荷通过包装模具进行，防止骰子被包装以免由静电放电造成的损坏从而提高半导体封装产品的产率。

23. 发明申请

US20100207259A1 SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING 有权
标题翻译：具有电磁干扰屏蔽的半导体器件封装
公开(公告)号：US20100207259A1
公开(公告)日：2010-08-19
申请号：US12770645
申请日：2010-04-29
申请人： Kuo-Hsien Liao , Jian-Cheng Chen , Chen-Chuan Fan , Chi-Tsung Chiu , Chih-Pin Hung
发明人： Kuo-Hsien Liao , Jian-Cheng Chen , Chen-Chuan Fan , Chi-Tsung Chiu , Chih-Pin Hung
IPC分类号： H01L23/552 , H01L21/78
CPC分类号： H01L23/552 , H01L21/6835 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2221/68331 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/07802 , H01L2924/15311 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2224/0401
摘要： Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a grounding element disposed adjacent to a periphery of a substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit. The grounding element includes an indented portion that is disposed adjacent to a lateral surface of the substrate unit. The semiconductor device package also includes an EMI shield that is electrically connected to the grounding element and is inwardly recessed adjacent to the indented portion of the grounding element.
摘要翻译：这里描述的是具有EMI屏蔽和相关方法的半导体器件封装。在一个实施例中，半导体器件封装包括邻近衬底单元的周边设置并至少部分地在衬底单元的上表面和下表面之间延伸的接地元件。接地元件包括与衬底单元的侧表面相邻设置的凹入部分。半导体器件封装还包括EMI屏蔽，其电连接到接地元件并且与接地元件的凹入部分相邻地向内凹陷。

24. 发明申请

US20090194852A1 SEMICONDUCTOR DEVICE PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING 有权
标题翻译：具有电磁干扰屏蔽的半导体器件封装
公开(公告)号：US20090194852A1
公开(公告)日：2009-08-06
申请号：US12336407
申请日：2008-12-16
申请人： Chi-Tsung Chiu , Chih-Pin Hung , Jui-Cheng Huang
发明人： Chi-Tsung Chiu , Chih-Pin Hung , Jui-Cheng Huang
IPC分类号： H01L23/552 , H01L21/50
CPC分类号： H01L24/97 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/49805 , H01L23/552 , H01L24/16 , H01L24/48 , H01L24/49 , H01L2221/68331 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/16152 , H01L2924/166 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H01L2224/85 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) a grounding element disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface; (4) a package body disposed adjacent to the upper surface and covering the semiconductor device and the grounding element; and (5) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a lateral surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The grounding element corresponds to a remnant of a conductive bump, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.
摘要翻译：这里描述的是具有EMI屏蔽和相关方法的半导体器件封装。在一个实施例中，半导体器件封装包括：（1）衬底单元; （2）接地元件，其设置在所述基板单元的周边附近并从所述基板单元的上表面向上延伸; （3）邻近上表面设置的半导体器件; （4）与所述上表面相邻并且覆盖所述半导体器件和所述接地元件的封装体; 和（5）邻近封装体的外表面设置并电连接到接地元件的侧表面的EMI屏蔽。封装主体的侧表面基本上与衬底单元的侧表面对准。接地元件对应于导电凸块的残余物，并且提供了入射到EMI屏蔽上的接地电磁辐射的电路径。

25. 发明申请

US20080145589A1 ELECTRONIC PACKAGE 有权
标题翻译：电子包装
公开(公告)号：US20080145589A1
公开(公告)日：2008-06-19
申请号：US11870620
申请日：2007-10-11
申请人： Chih Pin Hung , Chi Tsung Chiu , In De Ou , Yung Hui Wang
发明人： Chih Pin Hung , Chi Tsung Chiu , In De Ou , Yung Hui Wang
IPC分类号： B32B1/02
CPC分类号： H05K1/144 , H01L24/16 , H01L24/45 , H01L24/48 , H01L25/162 , H01L2224/16 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/19107 , H05K2201/042 , H05K2201/10977 , H05K2203/049 , Y10T428/23 , H01L2224/0401 , H01L2924/00012
摘要： An electronic package is provided. The electronic package includes a first substrate, an electronic component, a first sealant, a second substrate, a plurality of bonding wires and a second sealant, wherein the first substrate has opposing upper and lower surfaces and a plurality of bonding pads is disposed on the upper surface of the first substrate. The electronic component is positioned on the upper surface of the first substrate and electrically connected to the bonding pads. The first sealant is formed on the upper surface of the first substrate to encapsulate the electronic component. The lower surface of the second substrate is attached to the first sealant. The upper surface of the second substrate includes a central protrusion and a rim portion which surrounds and is lower than the central protrusion. A plurality of bonding wires is used to electrically connect the rim portion to the first substrate. The second sealant is formed on the upper surface of the first substrate and on the rim portion of the second substrate to encapsulate the bonding wires, the first sealant and the rim portion.
摘要翻译：提供电子包装。电子封装包括第一基板，电子部件，第一密封剂，第二基板，多个接合线和第二密封剂，其中第一基板具有相对的上表面和下表面，并且多个接合焊盘设置在第一基板的上表面。电子部件位于第一基板的上表面上并电连接到接合焊盘。第一密封剂形成在第一基板的上表面上以封装电子部件。第二基板的下表面附接到第一密封剂。第二基板的上表面包括中心突起和围绕中心突起的边缘部分。使用多个接合线将边缘部分电连接到第一基板。第二密封剂形成在第一基板的上表面和第二基板的边缘部分上，以封装接合线，第一密封剂和边缘部分。

26. 发明授权

US07060595B2 Circuit substrate and fabrication method thereof 有权
标题翻译：电路基板及其制造方法
公开(公告)号：US07060595B2
公开(公告)日：2006-06-13
申请号：US10627609
申请日：2003-07-28
申请人： In-De Ou , Chih-Pin Hung , Chia-Shang Chen , Kuang-Hua Lin , Shin-Hua Chao
发明人： In-De Ou , Chih-Pin Hung , Chia-Shang Chen , Kuang-Hua Lin , Shin-Hua Chao
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L23/49827 , H01L2924/0002 , H05K1/115 , H05K3/043 , H05K3/403 , H05K3/429 , H05K2201/09509 , H05K2201/09536 , H05K2201/0959 , H05K2201/09645 , H01L2924/00
摘要： A circuit substrate includes a board, a plurality of metal layers and an insulator. The board has a plurality of conductive traces layers and a via formed therein. The metal layers are formed on the inner wall of the via and each of the metal layers is electrically connected to its corresponding conductive traces layer. The via is filled with the insulator so that each of the metal layers is electrically isolated from each other. In addition, this invention also provides a fabrication method of the circuit substrate.
摘要翻译：电路基板包括板，多个金属层和绝缘体。该板具有多个导电迹线层和形成在其中的通孔。金属层形成在通孔的内壁上，并且每个金属层电连接到其对应的导电迹线层。通孔填充有绝缘体，使得每个金属层彼此电隔离。此外，本发明还提供了电路基板的制造方法。

27. 发明申请

US20050248037A1 Flip-chip package substrate with a high-density layout 审中-公开
标题翻译：具有高密度布局的倒装芯片封装衬底
公开(公告)号：US20050248037A1
公开(公告)日：2005-11-10
申请号：US11123204
申请日：2005-05-06
申请人： Chih-Pin Hung , Pao-Nan Li , Hsueh-Te Wang , Yun-Hsiang Tien
发明人： Chih-Pin Hung , Pao-Nan Li , Hsueh-Te Wang , Yun-Hsiang Tien
IPC分类号： H01L21/48 , H01L23/28 , H01L23/498 , H01L23/52
CPC分类号： H01L23/49838 , H01L23/49816 , H01L2224/81385 , H01L2924/0002 , H01L2924/00
摘要： A flip-chip package substrate with a high-density layout. A number of pads and a number of traces are formed on an upper surface of the substrate. At least a pad has a short axis and a vertical long axis which are perpendicular to each other. The distance between the elongated pad and the pad adjacent thereto is not smaller than two thirds of the length of the short axis, so that at least two of the traces can pass between the elongated pad and the pad adjacent thereto.
摘要翻译：具有高密度布局的倒装芯片封装基板。在基板的上表面上形成有多个焊盘和多个迹线。至少垫具有彼此垂直的短轴和垂直长轴。细长垫和与其相邻的垫之间的距离不小于短轴长度的三分之二，使得至少两条迹线可以在细长垫和与其相邻的垫之间通过。

28. 发明授权

US06927480B2 Multi-chip package with electrical interconnection 有权
标题翻译：多芯片封装带电互连
公开(公告)号：US06927480B2
公开(公告)日：2005-08-09
申请号：US10838351
申请日：2004-05-05
申请人： Bau-Nan Lee , Cheng-Fen Chen , Chih-Wei Tsai , Chih-Pin Hung
发明人： Bau-Nan Lee , Cheng-Fen Chen , Chih-Wei Tsai , Chih-Pin Hung
IPC分类号： H01L21/56 , H01L21/68 , H01L23/31 , H01L23/495
CPC分类号： H01L21/568 , H01L23/3107 , H01L23/49541 , H01L23/49558 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48247 , H01L2224/49171 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01039 , H01L2924/181 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A multi-chip package with electrical interconnection comprises a leadframe, at least a relay conductor, at least a first chip, at least a second chip, a plurality of bonding wires and a molding compound. A dielectric carrier is attached to the leadframe for fixing the relay conductor. The relay conductor has a top surface for interconnection of the bonding wires and a bottom surface attached to the dielectric carrier to electrically isolated from the leadframe. The bonding wires electrically connect the bonding pads of the first chip and second chip to the common lead of the leadframe through the relay conductor so as to achieve electrical interconnection of the plurality of chips and the leadframe inside the molding compound with lower cost.
摘要翻译：具有电互连的多芯片封装包括引线框架，至少一个继电器导体，至少第一芯片，至少第二芯片，多个键合线和模塑料。电介质载体附着到引线框架上，用于固定继电器导体。继电器导体具有用于互连接合线的顶表面和附接到电介质载体的底表面，以与引线框架电隔离。接合线通过继电器导体将第一芯片和第二芯片的焊盘电连接到引线框架的公共引线，以便以更低的成本实现模制化合物内的多个芯片和引线框架的电互连。

29. 发明申请

US20050082580A1 STRUCTURE OF WAFER LEVEL PACKAGE WITH AREA BUMP 审中-公开
标题翻译： WAFER LEVEL PACKAGE WITH AREA BUMP的结构
公开(公告)号：US20050082580A1
公开(公告)日：2005-04-21
申请号：US10904320
申请日：2004-11-03
申请人： Chih-Pin Hung
发明人： Chih-Pin Hung
IPC分类号： H01L23/367 , H01L23/498 , H01L23/50 , H05K1/02 , H05K1/11 , H05K3/28 , H05K3/34 , H01L29/768
CPC分类号： H01L24/73 , H01L23/3677 , H01L23/49816 , H01L23/49838 , H01L23/50 , H01L24/14 , H01L24/17 , H01L2224/05001 , H01L2224/05024 , H01L2224/05026 , H01L2224/05548 , H01L2224/05568 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/00014 , H01L2924/01033 , H05K1/0203 , H05K1/0263 , H05K1/111 , H05K3/284 , H05K3/3436 , H05K2201/094 , H05K2201/10977 , Y02P70/613 , H01L2924/00 , H01L2224/05599 , H01L2224/05099
摘要： A package structure with an area bump has at least a chip (also known as a die), a substrate, a plurality of first bumps (normal bumps) and at least a second bump (area bump), wherein the first bumps are electrically and mechanically connected to one of first bonding pads and the corresponding one of first contact pads. The second bump is electrically and mechanically connected to a second bonding pad and the corresponding second contact pad of the substrate, wherein the size of the second bump is larger than one of the first bumps. Because the size of the second bump is larger than one of the first bumps, the structure has much better electrical performance and performance of heat dissipation.
摘要翻译：具有区域凸块的封装结构至少具有芯片（也称为芯片），基板，多个第一凸块（正常凸块）和至少第二凸块（区域凸块），其中第一凸块电气和机械地连接到第一接合焊盘和第一接触焊盘中的相应一个之一。第二凸块电连接和机械地连接到第二焊盘和衬底的对应的第二接触焊盘，其中第二凸块的尺寸大于第一凸起之一。由于第二凸块的尺寸大于第一凸块中的一个，所以结构具有更好的电气性能和散热性能。

30. 发明申请

US20050062171A1 BRIDGE CONNECTION TYPE OF CHIP PACKAGE AND FABRICATING METHOD THEREOF 有权
标题翻译：桥接连接型芯片包装及其制作方法
公开(公告)号：US20050062171A1
公开(公告)日：2005-03-24
申请号：US10904423
申请日：2004-11-10
申请人： Chih-Pin Hung
发明人： Chih-Pin Hung
IPC分类号： H01L21/60 , H01L23/498 , H01L23/538 , H01L21/48 , H01L29/40
CPC分类号： H01L23/5389 , H01L23/49816 , H01L24/24 , H01L24/48 , H01L24/73 , H01L24/82 , H01L2224/24227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/00015 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599 , H01L2224/85399 , H01L2224/45015 , H01L2924/207
摘要： A chip package having at least a substrate, a chip and a conductive trace is provided. The substrate has a first surface, a second surface, a cavity and at least one substrate contact all positioned on the first surface of the substrate. The chip has an active surface with at least one chip contact thereon. The chip is accommodated inside the cavity with at least one sidewall having contact with one of the sidewalls of the cavity. The active surface of the chip and the first surface of the substrate are coplanar. The conductive trace runs from the active surface of the chip to the first surface of the substrate so that the chip contact and the substrate contact are electrically connected.
摘要翻译：提供了至少具有基板，芯片和导电迹线的芯片封装。衬底具有全部位于衬底的第一表面上的第一表面，第二表面，空腔和至少一个衬底接触。该芯片具有在其上具有至少一个芯片接触的有源表面。芯片容纳在腔内，具有与空腔的一个侧壁接触的至少一个侧壁。芯片的有源表面和基板的第一表面是共面的。导电迹线从芯片的有源表面延伸到基板的第一表面，使得芯片触点和基板触点电连接。

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