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11. 发明授权

US09084379B2 Process for fabricating wiring board 有权
标题翻译：制造布线板的工艺
公开(公告)号：US09084379B2
公开(公告)日：2015-07-14
申请号：US13423578
申请日：2012-03-19
申请人： Tsung-Yuan Chen , Chun-Chien Chen , Cheng-Po Yu
发明人： Tsung-Yuan Chen , Chun-Chien Chen , Cheng-Po Yu
IPC分类号： H01K3/10 , H05K3/00 , H05K3/36 , H05K1/00 , H05K1/14 , H05K3/42 , H05K3/20
CPC分类号： H05K3/428 , H05K3/0032 , H05K3/0035 , H05K3/0038 , H05K3/20 , H05K3/205 , H05K2201/09509 , H05K2201/09563 , H05K2201/0969 , H05K2203/0369 , H05K2203/0376 , H05K2203/0384 , H05K2203/0554 , H05K2203/108 , H05K2203/1476 , Y10T29/49124 , Y10T29/49126
摘要： A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.
摘要翻译：提供一种制造布线板的工艺。在该过程中，形成包括携带衬底和布线层的布线承载衬底。接下来，在布线承载基板中形成至少一个盲孔。接下来，通过绝缘层将布线承载基板层叠到另一布线承载基板。绝缘层设置在布线基板的布线层之间，并且完全填充盲孔。接下来，去除部分搬运基板以露出盲孔中的绝缘层。接下来，形成连接在布线层之间的导电柱。接下来，其余的携带衬底被去除。

12. 发明申请

US20150179594A1 PACKAGE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：封装基板及其制造方法
公开(公告)号：US20150179594A1
公开(公告)日：2015-06-25
申请号：US14219740
申请日：2014-03-19
申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.
发明人： Jun-Oh HWANG , Myung-Sam KANG , Young-Kwan LEE , Seung-Yeop KOOK , Seung-Eun LEE , Se-Rang IM
IPC分类号： H01L23/00
CPC分类号： H05K3/108 , H01L21/4853 , H01L23/49811 , H01L24/48 , H01L2224/48227 , H01L2224/85439 , H01L2924/00014 , H05K3/007 , H05K3/243 , H05K2201/09909 , H05K2203/0156 , H05K2203/0384 , H01L2224/45099
摘要： A package substrate and a method for manufacturing the same are disclosed. The method for manufacturing a package substrate in accordance with an aspect of the present invention includes: forming a first open hole corresponding to a shape of a bonding pad in a first photo resist; laminating a second photo resist on the first photo resist and forming a second open hole corresponding to shapes of a soldering pad, a circuit pattern layer and the bonding pad in the second photo resist; and forming a pattern plating layer up to a predetermined height in the first open hole and the second open hole.
摘要翻译：公开了封装基板及其制造方法。根据本发明的一个方面的用于制造封装衬底的方法包括：在第一光致抗蚀剂中形成与焊盘的形状相对应的第一裸露孔; 在第一光致抗蚀剂上层叠第二光致抗蚀剂，并形成与第二光刻胶中的焊盘，电路图案层和接合焊盘的形状对应的第二开孔; 以及在所述第一开孔和所述第二开孔中形成直至预定高度的图案镀层。

13. 发明授权

US08409922B2 Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect 有权
标题翻译：在半导体管芯上形成引线框架插入件的半导体器件和方法以及用于垂直电互连的TSV衬底
公开(公告)号：US08409922B2
公开(公告)日：2013-04-02
申请号：US12882110
申请日：2010-09-14
申请人： Zigmund R. Camacho , Dioscoro A. Merilo , Henry D. Bathan , Emmanuel A. Espiritu
发明人： Zigmund R. Camacho , Dioscoro A. Merilo , Henry D. Bathan , Emmanuel A. Espiritu
IPC分类号： H01L21/00 , H01L23/495
CPC分类号： H01L23/495 , H01L21/4832 , H01L21/4853 , H01L21/56 , H01L21/563 , H01L23/3107 , H01L23/3128 , H01L23/3135 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04042 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06131 , H01L2224/16225 , H01L2224/29144 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48105 , H01L2224/48157 , H01L2224/48175 , H01L2224/48227 , H01L2224/48228 , H01L2224/48247 , H01L2224/49113 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81411 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/831 , H01L2225/06517 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/01079 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/157 , H01L2924/1579 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H05K2203/0384 , H01L2924/01014 , H01L2924/0665 , H01L2924/00 , H01L2924/00012 , H01L2224/81805 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads.
摘要翻译：半导体器件具有衬底，其具有通过衬底形成的多个导电通孔和形成在衬底上的第一导电层。第一半导体管芯安装在衬底上。第二半导体管芯可以安装在第一半导体管芯上。引线框架插入件具有基板和从基板延伸的多个基底引线。在与基极相对的基板的表面上形成耐蚀刻导电层。引线框架安装在第一半导体管芯上的衬底上。密封剂沉积在衬底和第一半导体管芯上。去除基板，同时保持耐蚀刻导电层，并且基板的与基底引线相对的部分电绝缘基极。在与基极相对的基板的表面上形成互连结构。

14. 发明授权

US08365401B2 Circuit board and manufacturing method thereof 有权
标题翻译：电路板及其制造方法
公开(公告)号：US08365401B2
公开(公告)日：2013-02-05
申请号：US12732512
申请日：2010-03-26
申请人： Tzyy-Jang Tseng , Shu-Sheng Chiang , Tsung-Yuan Chen
发明人： Tzyy-Jang Tseng , Shu-Sheng Chiang , Tsung-Yuan Chen
IPC分类号： H05K3/02 , H05K3/10
CPC分类号： H05K3/465 , H05K3/0038 , H05K3/06 , H05K2203/0384 , H05K2203/0723 , Y10T29/49155
摘要： A circuit board includes a circuit substrate, a dielectric layer disposed on the circuit substrate and a patterned circuit structure. The dielectric layer covers a first surface and at least a first circuit of the circuit substrate. The dielectric layer has a second surface, at least a blind via, a second intaglio pattern and a third intaglio pattern connected to the blind via. The patterned circuit structure includes at least a second circuit disposed in the second intaglio pattern and third circuits disposed in the third intaglio pattern and the blind via. Each third circuit has a first conductive layer and a second conductive layer. The materials of the first conductive layer and the second circuit are the same. The line width of the second circuit is shorter than that of each third circuit. At least a third circuit is electrically connected to the first circuit of the circuit substrate.
摘要翻译：电路板包括电路基板，设置在电路基板上的电介质层和图案化电路结构。电介质层覆盖电路基板的第一表面和至少第一电路。电介质层具有连接到盲孔的第二表面，至少一盲孔，第二凹版图案和第三凹版图案。图案化电路结构包括至少设置在第二凹版图案中的第二电路和设置在第三凹版图案和盲孔中的第三电路。每个第三电路具有第一导电层和第二导电层。第一导电层和第二电路的材料相同。第二电路的线宽比每个第三电路的线宽短。至少第三电路电连接到电路基板的第一电路。

15. 发明申请

US20120312588A1 CIRCUIT BOARD 审中-公开
标题翻译：电路板
公开(公告)号：US20120312588A1
公开(公告)日：2012-12-13
申请号：US13588882
申请日：2012-08-17
申请人： TZYY-JANG TSENG , Shu-Sheng Chiang , Tsung-Yuan Chen
发明人： TZYY-JANG TSENG , Shu-Sheng Chiang , Tsung-Yuan Chen
IPC分类号： H05K1/11 , H05K1/09 , H05K1/02
CPC分类号： H05K3/465 , H05K3/0038 , H05K3/06 , H05K2203/0384 , H05K2203/0723 , Y10T29/49155
摘要： A circuit board includes a circuit substrate, a dielectric layer disposed on the circuit substrate and a patterned circuit structure. The dielectric layer covers a first surface and at least a first circuit of the circuit substrate. The dielectric layer has a second surface, at least a blind via, a second intaglio pattern and a third intaglio pattern connected to the blind via. The patterned circuit structure includes at least a second circuit disposed in the second intaglio pattern and third circuits disposed in the third intaglio pattern and the blind via. Each third circuit has a first conductive layer and a second conductive layer. The materials of the first conductive layer and the second circuit are the same. The line width of the second circuit is shorter than that of each third circuit. At least a third circuit is electrically connected to the first circuit of the circuit substrate.
摘要翻译：电路板包括电路基板，设置在电路基板上的电介质层和图案化电路结构。电介质层覆盖电路基板的第一表面和至少第一电路。电介质层具有连接到盲孔的第二表面，至少一盲孔，第二凹版图案和第三凹版图案。图案化电路结构包括至少设置在第二凹版图案中的第二电路和设置在第三凹版图案和盲孔中的第三电路。每个第三电路具有第一导电层和第二导电层。第一导电层和第二电路的材料相同。第二电路的线宽比每个第三电路的线宽短。至少第三电路电连接到电路基板的第一电路。

16. 发明授权

US08296929B2 Method for manufacturing an integrated lead suspension 有权
标题翻译：一体化铅悬浮液的制造方法
公开(公告)号：US08296929B2
公开(公告)日：2012-10-30
申请号：US13051258
申请日：2011-03-18
申请人： Reed T. Hentges , Kurt C. Swanson , Peter F. Ladwig , Lance Nevala
发明人： Reed T. Hentges , Kurt C. Swanson , Peter F. Ladwig , Lance Nevala
IPC分类号： G11B5/127 , H04R31/00
CPC分类号： G11B5/127 , B33Y80/00 , G11B5/48 , G11B5/484 , H05K1/0224 , H05K1/0253 , H05K1/056 , H05K3/06 , H05K3/44 , H05K2203/0323 , H05K2203/0384 , Y10T29/49025 , Y10T29/49027 , Y10T29/4903 , Y10T29/49032 , Y10T29/49156
摘要： Multi-layer ground plane structures and methods of manufacture for integrated lead suspension flexures. A flexure in accordance with one embodiment of the invention includes an insulating layer, a plurality of traces on the insulating layer and a stainless steel base layer on the side of the insulating layer opposite the traces. The stainless steel base layer includes one or more void portions with voids in the base layer opposite the insulating layer from the traces and one or more backed portions with the base layer backing the traces. A plurality of patterned and transversely-spaced first conductive ground planes are located opposite the insulating layer from the traces at the void portions and backed portions of the stainless steel base layer. A continuous gold second conductive ground plane is located opposite the insulating layer and the first ground planes from the side of the insulating layer adjacent to the traces at the void portions and backed portions of the stainless steel base layer. The gold ground plane can be used as an etch stop during formation of the voids in the base layer.
摘要翻译：多层地面平面结构和集成铅悬浮挠曲的制造方法。根据本发明的一个实施例的弯曲部包括绝缘层，绝缘层上的多个迹线和与迹线相对的绝缘层一侧的不锈钢基底层。不锈钢基层包括一个或多个空隙部分，其在与绝缘层相对的基底层中具有空隙，并且具有基底层背衬迹线的一个或多个背衬部分。多个图案化且横向间隔开的第一导电接地平面位于不锈钢基层的空隙部分和背部的绝缘层与迹线相对的位置。连续的金第二导电接地平面位于绝缘层相对的绝缘层的相对侧的第一接地层和与不锈钢基层的空隙部分和背部的迹线相邻的第一接地层。金基底层可以在基层形成空隙期间用作蚀刻停止。

17. 发明申请

US20120155038A1 FLEXIBLE CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：柔性电路板及其制造方法
公开(公告)号：US20120155038A1
公开(公告)日：2012-06-21
申请号：US13392247
申请日：2010-07-28
申请人： Yasumori Fukushima , Masaki Fujiwara , Steven Roy Droes
发明人： Yasumori Fukushima , Masaki Fujiwara , Steven Roy Droes
IPC分类号： H05K1/02 , H05K3/20 , H05K3/00 , H05K1/18
CPC分类号： H05K1/185 , H01L21/4846 , H01L23/4985 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L2224/73267 , H01L2224/82031 , H01L2924/14 , H01L2924/15788 , H01L2924/351 , H01L2924/3511 , H05K1/189 , H05K3/08 , H05K2201/0175 , H05K2203/016 , H05K2203/0384 , H05K2203/095 , H05K2203/1469 , Y10T29/49128 , H01L2924/00
摘要： The present invention provides a high-performance flexible circuit board having excellent flexibility, a fine wiring pattern, and fine electric contacts, and a manufacturing method thereof. In a flexible circuit board (20), a second insulating layer (24) made of an inorganic material is positioned between a wiring layer (25) and a first insulating layer (23) made of an inorganic material.
摘要翻译：本发明提供一种具有优异的柔性，精细布线图案和精细电触点的高性能柔性电路板及其制造方法。在柔性电路板（20）中，由无机材料制成的第二绝缘层（24）位于布线层（25）和由无机材料制成的第一绝缘层（23）之间。

18. 发明申请

US20120088334A1 METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE 失效
标题翻译：制造半导体封装的方法
公开(公告)号：US20120088334A1
公开(公告)日：2012-04-12
申请号：US13007444
申请日：2011-01-14
申请人： Mi Sun HWANG , Keung Jin SOHN , Eung Suek LEE , Myung Sam KANG
发明人： Mi Sun HWANG , Keung Jin SOHN , Eung Suek LEE , Myung Sam KANG
IPC分类号： H01L21/60
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/49816 , H01L23/49894 , H01L24/16 , H01L24/48 , H01L24/81 , H01L2224/16237 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/81192 , H01L2224/81385 , H01L2224/81815 , H01L2924/00014 , H01L2924/01087 , H01L2924/15311 , H05K3/06 , H05K3/4038 , H05K3/4647 , H05K2203/0384 , H01L2924/00015 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Disclosed herein is a method for manufacturing a semiconductor package which uses a base member 120 in which a first metal layer 113, a barrier layer 115, and a second metal layer 117 are stacked on both surface thereof in sequence based on an adhesive member 111 to simultaneously manufacture two printed circuit boards through a single sheet process, thereby making it possible to improve manufacturing efficiency; electrically connects a semiconductor chip 300 to a printed circuit board through a solder bump 250, thereby making it possible to implement a high-density package substrate; and forms a metal post 140 instead of a through hole to required in an interlayer circuit connection, thereby making it possible to reduce costs required in the processing/plating of the through hole.
摘要翻译：本发明公开了一种半导体封装件的制造方法，该半导体封装件使用基片120，其中第一金属层113，阻挡层115和第二金属层117依次以两个表面层叠在第一金属层113，阻挡层115和第二金属层117上，同时通过单片工艺制造两个印刷电路板，从而可以提高制造效率; 通过焊料凸块250将半导体芯片300电连接到印刷电路板，从而可以实现高密度封装基板; 并且形成金属柱140而不是层间电路连接所需的通孔，从而可以降低通孔的加工/电镀所需的成本。

19. 发明申请

US20110252637A1 STRUCTURE AND METHOD OF MAKING INTERCONNECT ELEMENT, AND MULTILAYER WIRING BOARD INCLUDING THE INTERCONNECT ELEMENT 有权
标题翻译：制造互连元件的结构和方法，以及包括互连元件的多层布线板
公开(公告)号：US20110252637A1
公开(公告)日：2011-10-20
申请号：US13085126
申请日：2011-04-12
申请人： Kimitaka Endo , Norihito Masuda , Tomokazu Shimada
发明人： Kimitaka Endo , Norihito Masuda , Tomokazu Shimada
IPC分类号： H05K3/00
CPC分类号： H05K3/4617 , H01L21/4857 , H01L23/49822 , H01L23/5383 , H01L2924/0002 , H05K3/064 , H05K3/205 , H05K3/423 , H05K3/4647 , H05K2203/0384 , H05K2203/0542 , H05K2203/0733 , Y10S438/931 , Y10T29/49124 , H01L2924/00
摘要： A method of fabricating an interconnect element may include fabricating a metal layer that overlies a carrier layer and that includes a plurality of metal traces; providing a dielectric element to overlie the metal layer and the carrier layer; providing a plurality of metal posts; and removing the carrier layer to expose the first major surface of the dielectric element and the outer surfaces of the plurality of metal traces.
摘要翻译：制造互连元件的方法可以包括制造覆盖载体层并且包括多个金属迹线的金属层; 提供介电元件以覆盖金属层和载体层; 提供多个金属柱; 以及去除载体层以暴露介质元件的第一主表面和多个金属迹线的外表面。

20. 发明授权

US08028402B2 Connection board, and multi-layer wiring board, substrate for semiconductor package and semiconductor package using connection board, and manufacturing method thereof 有权
标题翻译：连接板和多层布线板，半导体封装用基板和使用连接板的半导体封装及其制造方法
公开(公告)号：US08028402B2
公开(公告)日：2011-10-04
申请号：US11775294
申请日：2007-07-10
申请人： Hidehiro Nakamura , Akishi Nakaso , Shigeharu Arike , Fumio Inoue , Tetsuya Enomoto , Norio Moriike , Kousuke Hiroki
发明人： Hidehiro Nakamura , Akishi Nakaso , Shigeharu Arike , Fumio Inoue , Tetsuya Enomoto , Norio Moriike , Kousuke Hiroki
IPC分类号： H05K3/36 , H01R9/00 , H01K3/10
CPC分类号： H05K3/4617 , H01L21/4857 , H01L21/486 , H01L23/3128 , H01L23/49822 , H01L23/49827 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/92247 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H05K3/0097 , H05K3/06 , H05K3/244 , H05K3/4038 , H05K3/4623 , H05K3/4632 , H05K3/4647 , H05K2201/0141 , H05K2201/0195 , H05K2201/0355 , H05K2201/0361 , H05K2201/096 , H05K2201/10378 , H05K2203/0152 , H05K2203/0156 , H05K2203/0384 , H05K2203/0733 , H05K2203/1536 , Y10T29/49126 , Y10T29/4913 , Y10T29/49147 , Y10T29/49165 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Disclosed is a manufacturing method of a multi-layer wiring board, which method includes: preparing connection boards, the connection boards having respectively an insulating resin composition layer, a connection conductor formed so as to pass through the insulating resin composition layer and a conductor circuit formed on the insulating resin composition layer and connected to the connection conductor; aligning the connection boards; and laminating the aligned connection boards by heating and pressing, so that the connection conductors, or the connection conductor and the conductor circuit, are conductively connected with each other, and the connection boards are mechanically connected with each other by the insulating resin composition layer. The connection boards are formed by specified processing, including use of a three-layer composite metallic layer.
摘要翻译：公开了一种多层布线板的制造方法，该方法包括：准备连接板，连接板分别具有绝缘树脂组合物层，形成为穿过绝缘树脂组合物层的连接导体和导体电路形成在绝缘树脂组合物层上并连接到连接导体; 对准连接板; 并且通过加热和压制层叠对准的连接板，使得连接导体或连接导体和导体电路彼此导电连接，并且连接板通过绝缘树脂组合物层彼此机械连接。连接板通过特定的加工形成，包括使用三层复合金属层。

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