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1. 发明申请

US20180255649A1 Sacrificial Structure With Dummy Core and Two Sections of Separate Material Thereon for Manufacturing Component Carriers 审中-公开
公开(公告)号：US20180255649A1
公开(公告)日：2018-09-06
申请号：US15760487
申请日：2016-09-16
申请人： AT&S (China) Co. Ltd.
发明人： Annie Tay , Nikolaus Bauer-Oeppinger , Giordano DiGregorio , Philips DAI
IPC分类号： H05K3/46 , H05K3/00 , H05K3/32 , H05K3/40 , H05K3/10 , H05K3/02
CPC分类号： H05K3/4682 , H05K1/0269 , H05K1/0271 , H05K3/0097 , H05K3/022 , H05K3/108 , H05K3/32 , H05K3/4007 , H05K3/4638 , H05K2201/068 , H05K2201/09918 , H05K2201/09936 , H05K2203/0156 , H05K2203/0264 , H05K2203/1536
摘要： A semifinished product with a sacrificial structure and two component carriers releasably formed on opposing main surfaces of the sacrificial structure. The sacrificial structure includes a central structure and releasing layers on or over both opposing main surfaces of the central structure The central structure includes a dummy core being covered, in particular fully, on or over both main surfaces thereof with a respective one of two spatially separated sections of separate material, in particular separate dielectric material.

2. 发明授权

US09872393B2 Method for making a circuit board 有权
公开(公告)号：US09872393B2
公开(公告)日：2018-01-16
申请号：US14886581
申请日：2015-10-19
申请人： Avary Holding (Shenzhen) Co., Limited , HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd. , GARUDA TECHNOLOGY CO., LTD.
发明人： Tzu-Chien Yeh
IPC分类号： H01K3/10 , H05K1/18 , H05K1/11 , H05K1/02 , H05K1/09 , H05K1/03 , H05K3/18 , H05K3/46 , H05K3/40
CPC分类号： H05K1/184 , H05K1/0298 , H05K1/0313 , H05K1/092 , H05K1/111 , H05K1/115 , H05K1/187 , H05K3/0097 , H05K3/188 , H05K3/4038 , H05K3/4602 , H05K3/4644 , H05K3/4697 , H05K2201/0203 , H05K2201/0391 , H05K2201/09545 , H05K2203/0278 , H05K2203/122 , H05K2203/1536 , Y10T29/49165
摘要： A circuit board includes a core layer, at least one passive component, a first and a second conductive wire layers, at least one contact pad, and a resin packing layer. The core layer defines at least one through hole to receive the passive component. The first and the second conductive wire layers are connected to two opposite surfaces of the core layer. Each contact pad is positioned between and connected to one passive component and the first conductive wire layer. The resin packing layer is filled among the core layer, each passive component, each contact pad, the first and the second conductive wire layers. The resin packing layer can connect the first and the second conductive wire layers to the core layer, and connect the core layer, each passive component, and each contact pads to each other.

3. 发明授权

US09691727B2 Pad-less interconnect for electrical coreless substrate 有权
公开(公告)号：US09691727B2
公开(公告)日：2017-06-27
申请号：US14686210
申请日：2015-04-14
申请人： Intel Corporation
发明人： Javier Soto Gonzalez , Charavana K. Gurumurthy , Robert M. Nickerson , Debendra Mallik
IPC分类号： H05K3/46 , H05K3/40 , H05K3/34 , H05K3/28 , H05K3/24 , H05K3/20 , H05K3/00 , H05K1/11 , H01L23/498 , H01L23/31 , H01L23/00 , H01L21/48
CPC分类号： H01L24/17 , H01L21/4857 , H01L21/486 , H01L23/3128 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L2224/05571 , H01L2224/05573 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2924/00014 , H01L2924/12042 , H01L2924/14 , H01L2924/1433 , H01L2924/2064 , H01L2924/20642 , H01L2924/20643 , H01L2924/20644 , H05K1/113 , H05K3/0035 , H05K3/007 , H05K3/20 , H05K3/244 , H05K3/28 , H05K3/3457 , H05K3/4007 , H05K3/4682 , H05K2201/0367 , H05K2201/096 , H05K2203/0152 , H05K2203/1536 , Y10T29/49147 , H01L2924/00 , H01L2224/05599
摘要： A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.

4. 发明授权

US09491871B2 Carrier substrate 有权
标题翻译：载体基片
公开(公告)号：US09491871B2
公开(公告)日：2016-11-08
申请号：US14977669
申请日：2015-12-22
申请人： Unimicron Technology Corp.
发明人： Ying-Chih Chan , Chun-Ting Lin
IPC分类号： H05K1/00 , H05K3/40 , H05K3/00 , H05K3/46
CPC分类号： H05K3/4015 , H05K3/0097 , H05K3/4644 , H05K2201/09509 , H05K2201/09827 , H05K2203/041 , H05K2203/1536
摘要： A carrier substrate includes a dielectric layer, a first circuit layer, an insulation layer, conductive blocks, and a first conductive structure. The dielectric layer has a first surface, a second surface, and blind vias. The first circuit layer is embedded in the first surface and the blind vias extend from the second surface to the first circuit layer. The insulation layer is disposed on the first surface and has a third surface, a fourth surface, and first openings exposing the first circuit layer. The conductive blocks fill the first openings and connect with the first circuit layer. A top surface of each of the conductive blocks is higher than the third surface of the insulation layer. The first conductive structure includes conductive vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.
摘要翻译：载体基板包括电介质层，第一电路层，绝缘层，导电块和第一导电结构。电介质层具有第一表面，第二表面和盲孔。第一电路层嵌入在第一表面中，盲孔从第二表面延伸到第一电路层。绝缘层设置在第一表面上，并且具有第三表面，第四表面和暴露第一电路层的第一开口。导电块填充第一开口并与第一电路层连接。每个导电块的顶表面高于绝缘层的第三表面。第一导电结构包括填充盲通孔的导电通孔和设置在第二表面的一部分上的第二电路层。

5. 发明申请

US20160190027A1 METHODS OF FORMING PANEL EMBEDDED DIE STRUCTURES 审中-公开
标题翻译：面板嵌入式结构的形成方法
公开(公告)号：US20160190027A1
公开(公告)日：2016-06-30
申请号：US15065533
申请日：2016-03-09
申请人： Intel Corporation
发明人： Rahul N. Manepalli , Hamid R. Azimi , John S. Guzek
IPC分类号： H01L23/31 , H01L23/29 , H01L23/50 , H01L23/00 , H01L23/528
CPC分类号： H01L23/3121 , H01L21/561 , H01L21/568 , H01L23/293 , H01L23/3114 , H01L23/50 , H01L23/528 , H01L24/03 , H01L24/11 , H01L24/14 , H01L24/19 , H01L24/96 , H01L2224/02379 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/12105 , H01L2224/13023 , H01L2224/131 , H01L2224/16237 , H01L2224/96 , H01L2924/0665 , H01L2924/12042 , H01L2924/1432 , H01L2924/1436 , H01L2924/181 , H01L2924/186 , H01L2924/3511 , H05K3/0097 , H05K3/4679 , H05K3/4682 , H05K2201/09918 , H05K2203/1536 , H01L2924/00 , H01L2224/11 , H01L2224/03 , H01L2924/014
摘要： Methods of forming molded panel coreless package structures are described. Those methods and structures may include fabrication of embedded die packages using large panel format and use of molding to improve rigidity of the panel, as well as to embed the die in a non-sacrificial mold material. The methods and structures described include methods for manufacturing thin, coreless substrate architectures which possess low warpage.
摘要翻译：描述形成模制板无芯封装结构的方法。这些方法和结构可以包括使用大面板格式制造嵌入式模具封装并使用模制来提高面板的刚度，以及将模具嵌入非牺牲模具材料中。所描述的方法和结构包括制造具有低翘曲的薄的无芯基板结构的方法。

6. 发明授权

US09247654B2 Carrier substrate and manufacturing method thereof 有权
标题翻译：载体基板及其制造方法
公开(公告)号：US09247654B2
公开(公告)日：2016-01-26
申请号：US13966295
申请日：2013-08-14
申请人： Unimicron Technology Corp.
发明人： Chun-Ting Lin
IPC分类号： H05K1/11 , H05K3/46 , H05K3/40 , H05K3/00
CPC分类号： H05K3/4015 , H05K3/0097 , H05K3/4644 , H05K2201/09827 , H05K2203/041 , H05K2203/1536
摘要： A carrier substrate includes a dielectric layer, a first circuit layer, an insulation layer, conductive blocks, and a first conductive structure. The dielectric layer has a first surface, a second surface, and blind vias. The first circuit layer is embedded in the first surface and the blind vias extend from the second surface to the first circuit layer. The insulation layer is disposed on the first surface and has a third surface, a fourth surface, and first openings. The first openings expose the first circuit layer and an aperture of each first opening is increased gradually from the third surface to the fourth surface. The conductive blocks fill the first openings and connect with the first circuit layer. The first conductive structure includes conductive vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.
摘要翻译：载体基板包括电介质层，第一电路层，绝缘层，导电块和第一导电结构。电介质层具有第一表面，第二表面和盲孔。第一电路层嵌入在第一表面中，盲孔从第二表面延伸到第一电路层。绝缘层设置在第一表面上并且具有第三表面，第四表面和第一开口。第一开口露出第一电路层，并且每个第一开口的开口从第三表面逐渐增加到第四表面。导电块填充第一开口并与第一电路层连接。第一导电结构包括填充盲通孔的导电通孔和设置在第二表面的一部分上的第二电路层。

7. 发明申请

US20160021736A1 PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：印刷电路板及其制造方法
公开(公告)号：US20160021736A1
公开(公告)日：2016-01-21
申请号：US14804442
申请日：2015-07-21
申请人： Samsung Electro-Mechanics Co., Ltd.
发明人： Gi Ho HAN , Gun Woo KIM , Sung Won JEONG , Ki Hwan KIM , Da Hee KIM , Yong Yoon CHO
IPC分类号： H05K1/02 , H05K3/46 , H05K3/40 , H05K1/11 , H05K3/00
CPC分类号： H05K3/4682 , H05K1/113 , H05K3/0097 , H05K3/429 , H05K2201/09536 , H05K2201/096 , H05K2203/1536
摘要： There are provided a printed circuit board and a method of manufacturing the same. The printed circuit board according to an exemplary embodiment of the present disclosure includes: a first insulating layer; a second insulating layer formed below the first insulating layer; a via pad formed on an upper surface of the second insulating layer and formed so as to be buried in the second insulating layer; a double via formed on an upper surface of the via pad, formed so as to penetrate through the first insulating layer, and including an auxiliary via and a first via; and a second via formed on a lower surface of the via pad and formed so as to penetrate through the second insulating layer.
摘要翻译：提供了一种印刷电路板及其制造方法。根据本公开的示例性实施例的印刷电路板包括：第一绝缘层; 形成在所述第一绝缘层下面的第二绝缘层; 通孔焊盘，形成在所述第二绝缘层的上表面上，并被形成为埋在所述第二绝缘层中; 形成在所述通孔焊盘的上表面上的双通孔，形成为穿过所述第一绝缘层，并且包括辅助通孔和第一通孔; 以及形成在所述通孔焊盘的下表面上并形成为穿过所述第二绝缘层的第二通孔。

8. 发明授权

US09230895B2 Package substrate and fabrication method thereof 有权
标题翻译：封装基板及其制造方法
公开(公告)号：US09230895B2
公开(公告)日：2016-01-05
申请号：US13191807
申请日：2011-07-27
申请人： Pao-Hung Chou , Hsien-Min Chang
发明人： Pao-Hung Chou , Hsien-Min Chang
IPC分类号： H01L23/498 , H05K3/00 , H05K3/10 , C25D5/02 , C25D7/12 , H01L21/48 , H01L23/00 , H01L23/31 , H05K1/11 , H05K3/28
CPC分类号： H01L23/49811 , C25D5/02 , C25D7/12 , H01L21/4853 , H01L23/3128 , H01L24/48 , H01L2224/48091 , H01L2224/48105 , H01L2224/48245 , H01L2224/48247 , H01L2924/00014 , H01L2924/181 , H05K1/111 , H05K3/0097 , H05K3/107 , H05K3/282 , H05K2201/0376 , H05K2203/1536 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A package substrate includes: a dielectric layer having two opposite surfaces; a wiring layer embedded in the dielectric layer and exposed from the two opposite surfaces of the dielectric layer, wherein the wiring layer has solder pads, conductive pads and circuit wires electrically connecting the solder pads and the conductive pads; and a first insulating protection layer disposed on one of the two opposite surfaces of the dielectric layer to cover the dielectric layer and the wiring layer and having a plurality of openings for exposing the conductive pads, respectively. The package substrate, by directly using the dielectric layer as a base, provides a package substrate having reduced thickness and lower fabrication costs compared to the prior art.
摘要翻译：封装基板包括：具有两个相对表面的电介质层; 介于所述电介质层中并且从所述电介质层的两个相对表面露出的布线层，其中所述布线层具有焊接焊盘，导电焊盘和电连接所述焊盘和所述导电焊盘的电路线; 以及第一绝缘保护层，其设置在电介质层的两个相对表面之一上以覆盖电介质层和布线层，并且具有多个用于暴露导电焊盘的开口。通过直接使用电介质层作为基底，封装衬底提供了与现有技术相比具有减小的厚度和较低制造成本的封装衬底。

9. 发明申请

US20150351231A1 CIRCUIT BOARD AND METHOD OF MANUFACTURING CIRCUIT BOARD 审中-公开
标题翻译：电路板和制造电路板的方法
公开(公告)号：US20150351231A1
公开(公告)日：2015-12-03
申请号：US14722066
申请日：2015-05-26
申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.
发明人： Young Kwan LEE , Myung Sam KANG , Seung Yeop KOOK , Kwang Hee KWON , Seung Eun LEE , Ki Jung SUNG
IPC分类号： H05K1/02 , H05K3/30 , H05K3/00 , H05K3/40 , H05K1/11 , H05K1/09
CPC分类号： H05K1/0271 , H01L24/13 , H01L24/16 , H01L24/48 , H01L2224/04042 , H01L2224/131 , H01L2224/16111 , H01L2224/16237 , H01L2224/48237 , H05K1/0209 , H05K3/0097 , H05K2201/068 , H05K2201/09472 , H05K2201/10553 , H05K2203/0369 , H05K2203/1536 , Y10T29/49131 , Y10T29/49149 , H01L2924/014
摘要： Disclosed herein is a circuit board in which a metal plate is provided on a surface coupled to a device, and a connection pad is exposed through an opening part of the metal plate to be electrically connected to the device. The circuit board may have the device mounted thereon and a connection terminal of the device and a connection pad of the circuit board may be connected to each other by a wire, or the like.
摘要翻译：这里公开了一种电路板，其中金属板设置在耦合到器件的表面上，并且连接焊盘通过金属板的开口部分暴露以与该器件电连接。电路板可以具有安装在其上的装置，并且该装置的连接端子和电路板的连接焊盘可以通过导线等相互连接。

10. 发明申请

US20150282314A1 METHOD FOR MANUFACTURING PRINTED WIRING BOARD WITH CONDUCTIVE POST AND PRINTED WIRING BOARD WITH CONDUCTIVE POST 有权
标题翻译：带导电插头的印刷线路板和印刷电路板与导电柱的制造方法
公开(公告)号：US20150282314A1
公开(公告)日：2015-10-01
申请号：US14674301
申请日：2015-03-31
申请人： IBIDEN CO., LTD.
发明人： Toru FURUTA , Takeshi FURUSAWA , Tomoya TERAKURA
IPC分类号： H05K1/11 , H05K3/42 , H05K3/40 , H05K1/09 , H05K3/06
CPC分类号： H05K3/4007 , H05K1/0271 , H05K1/111 , H05K3/0097 , H05K3/282 , H05K3/3436 , H05K2201/0355 , H05K2201/0376 , H05K2201/09745 , H05K2201/09772 , H05K2203/0369 , H05K2203/1536 , Y02P70/611 , Y10T29/49165
摘要： A method for manufacturing a printed wiring board with conductive posts includes forming on a first foil provided on carrier a first conductive layer including mounting pattern to connect electronic component via conductive posts, forming on the first foil a laminate including an insulating layer and a second foil to form the laminate on the first conductive layer, removing the carrier, forming a metal film on the laminate and first film, forming resist on the metal film to have pattern exposing portion of the metal film corresponding to the mounting pattern and portion of the second foil for a second conductive layer, forming an electroplating layer on the portion of the metal film not covered by the resist, removing the resist, and applying etching to remove the first and second foils below the metal film exposed by the removing the resist and to form the posts on the mounting pattern.
摘要翻译：一种用于制造具有导电柱的印刷线路板的方法，包括在载体上形成第一导电层，第一导电层包括安装图案，以经由导电柱连接电子部件，在第一箔上形成包括绝缘层和第二箔在第一导电层上形成层压体，去除载体，在层压体上形成金属膜和第一膜，在金属膜上形成抗蚀剂，使金属膜的图案曝光部分对应于安装图案和第二导电层的部分箔片用于第二导电层，在未被抗蚀剂覆盖的金属膜的部分上形成电镀层，去除抗蚀剂，并施加蚀刻以除去通过除去抗蚀剂暴露的金属膜下面的第一和第二箔，并且形成安装模式上的柱。

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