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11. 发明申请

US20120311365A1 PROGRAMMABLE LOGIC DEVICE 有权
标题翻译：可编程逻辑器件
公开(公告)号：US20120311365A1
公开(公告)日：2012-12-06
申请号：US13477192
申请日：2012-05-22
申请人： Seiichi Yoneda , Jun Koyama , Yutaka Shionoiri , Masami Endo , Hiroki Dembo , Tatsuji Nishijima , Hidetomo Kobayashi , Kazuaki Ohshima
发明人： Seiichi Yoneda , Jun Koyama , Yutaka Shionoiri , Masami Endo , Hiroki Dembo , Tatsuji Nishijima , Hidetomo Kobayashi , Kazuaki Ohshima
IPC分类号： G06F1/32
CPC分类号： H03K19/173 , G06F1/3243 , G06F3/0679 , H03K19/17772 , Y02D10/152
摘要： An object is to provide a programmable logic device configured to keep a connection state of logic circuits even while power supply voltage is stopped. The programmable logic device includes arithmetic circuits each of whose logic state can be changed; a configuration changing circuit changing the logic states of the arithmetic circuits; a power supply control circuit controlling supply of power supply voltage to the arithmetic circuits; a state memory circuit storing data on the logic states and data on states of the power supply voltage of the arithmetic circuits; and an arithmetic state control circuit controlling the configuration changing circuit and the power supply control circuit in accordance with the data stored in the state memory circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the configuration changing circuit and each of the arithmetic circuits.
摘要翻译：目的是提供一种可编程逻辑器件，其被配置为即使在电源电压停止时仍保持逻辑电路的连接状态。可编程逻辑器件包括可以改变其逻辑状态的运算电路; 配置改变电路改变运算电路的逻辑状态; 电源控制电路，控制对所述运算电路的电源电压供给; 存储关于逻辑状态的数据的状态存储电路和关于运算电路的电源电压的状态的数据; 以及算术状态控制电路，根据存储在状态存储电路中的数据控制配置改变电路和电源控制电路。在配置改变电路和每个运算电路之间设置有在氧化物半导体层中形成沟道形成区的晶体管。

12. 发明申请

US20120292616A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120292616A1
公开(公告)日：2012-11-22
申请号：US13473014
申请日：2012-05-16
申请人： Kazuaki OHSHIMA
发明人： Kazuaki OHSHIMA
IPC分类号： H01L27/06
CPC分类号： H01L27/105 , H01L27/0605 , H01L27/0688 , H01L27/092 , H01L27/108 , H01L27/1203 , H03K19/0013 , H03K19/1776 , H03K19/17772
摘要： A semiconductor device having a novel structure is provided. The semiconductor device includes a first p-type transistor, a second n-type transistor, a third transistor, and a fourth transistor. One of a source and a drain of the third transistor is connected to a wiring supplying first potential, and the other is connected to one of a source and a drain of the first transistor. One of a source and a drain of the second transistor is connected to the other of the source and the drain of the first transistor, and the other is connected to one of a source and a drain of the fourth transistor. The other of the source and the drain of the fourth transistor is connected to a wiring supplying second potential lower than the first potential. An oxide semiconductor material is used in channel formation regions of the third transistor and the fourth transistor.
摘要翻译：提供具有新颖结构的半导体器件。半导体器件包括第一p型晶体管，第二n型晶体管，第三晶体管和第四晶体管。第三晶体管的源极和漏极之一连接到提供第一电位的布线，另一个连接到第一晶体管的源极和漏极之一。第二晶体管的源极和漏极之一连接到第一晶体管的源极和漏极中的另一个，另一个连接到第四晶体管的源极和漏极之一。第四晶体管的源极和漏极中的另一个连接到提供低于第一电位的第二电位的布线。在第三晶体管和第四晶体管的沟道形成区域中使用氧化物半导体材料。

13. 发明申请

US20110175646A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110175646A1
公开(公告)日：2011-07-21
申请号：US13005557
申请日：2011-01-13
申请人： Yasuhiko TAKEMURA , Shunpei YAMAZAKI
发明人： Yasuhiko TAKEMURA , Shunpei YAMAZAKI
IPC分类号： H03K19/177
CPC分类号： H03K19/0013 , H01L27/0629 , H01L29/7869 , H01L2924/0002 , H03K17/161 , H03K19/173 , H03K19/17724 , H03K19/17736 , H03K19/1776 , H03K19/17772 , H03K19/17784 , H01L2924/00
摘要： It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current.
摘要翻译：本发明的目的是提供能够降低功耗的半导体装置。另一个目的是提供使用诸如可编程逻辑器件（PLD）之类的编程单元的高度可靠的半导体器件。根据基本块之间的连接配置的变化，改变基本块的供电电压。也就是说，当基本块之间的连接结构使得基本块不对电路有贡献时，停止向该基本块提供电源电压。此外，使用使用使用氧化物半导体形成沟道形成区域的场效应晶体管形成的编程单元来控制对基本块的电源电压的供给，场效应晶体管具有极低的截止电流或极低漏电流。

14. 发明授权

US07902868B2 Field programmable gate arrays using resistivity sensitive memories 有权
标题翻译：使用电阻率敏感存储器的现场可编程门阵列
公开(公告)号：US07902868B2
公开(公告)日：2011-03-08
申请号：US12657678
申请日：2010-01-25
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , H03K19/1776 , H03K19/17772 , H03K19/1778
摘要： Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane.
摘要翻译：描述了使用电阻率敏感存储器的现场可编程门阵列，包括包括可配置逻辑的可编程单元，连接到可配置逻辑以提供可配置逻辑的功能的存储器，存储器包括非易失性可重写存储元件，敏感存储器元件，连接到可配置逻辑的输入/输出逻辑和与其他单元通信的存储器。存储器元件可以是在没有电力的情况下存储数据的两端电阻率敏感存储器元件。两端存储器元件可以将数据存储为可以通过在存储器元件的端子上施加读取电压而被非破坏性地读取的多个导电率分布，并且可以通过施加写入电压将数据写入到两端存储器元件跨越终端。存储器可以垂直配置在一个或多个垂直堆叠在一起的并且位于逻辑平面之上的存储器平面中。

15. 发明申请

US20100134144A1 Field programmable gate arrays using resistivity sensitive memories 有权
公开(公告)号：US20100134144A1
公开(公告)日：2010-06-03
申请号：US12657678
申请日：2010-01-25
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , H03K19/1776 , H03K19/17772 , H03K19/1778
摘要： Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane.

16. 发明申请

US20100023736A1 RECONFIGURABLE CIRCUIT, RESET METHOD, AND CONFIGURATION INFORMATION GENERATION DEVICE 审中-公开
标题翻译：可重构电路，复位方法和配置信息生成装置
公开(公告)号：US20100023736A1
公开(公告)日：2010-01-28
申请号：US12520909
申请日：2008-10-30
申请人： Takashi Morimoto , Shinichiro Nishioka , Koji Asai
发明人： Takashi Morimoto , Shinichiro Nishioka , Koji Asai
IPC分类号： G06F9/00 , G06F9/30 , G06F9/45
CPC分类号： H03K19/17772 , G06F1/24 , H03K19/17756 , H03K19/1776
摘要： The present invention provides a reconfigurable circuit that comprises a plurality of reconfiguration cells and changes a configuration of a computation processing unit included in each of the reconfiguration cells. Here, each of the reconfiguration cells further includes: a computation storage unit operable to store a result of a computation performed by the computation processing unit; a flag holding unit operable to hold an initialization flag indicating whether an initialization of the computation storage unit is required; and an initialization control unit operable to, during the configuration change of the computation processing unit, control the initialization of the computation storage unit based on the initialization flag held by the flag holding unit.
摘要翻译：本发明提供一种可重构电路，其包括多个重新配置单元，并且改变每个重新配置单元中包括的计算处理单元的配置。这里，每个重新配置单元还包括：计算存储单元，用于存储由计算处理单元执行的计算结果; 标记保持单元，用于保持指示是否需要计算存储单元的初始化的初始化标志; 以及初始化控制单元，其可操作以在所述计算处理单元的配置改变期间，基于由所述标志保持单元保持的初始化标志来控制所述计算存储单元的初始化。

17. 发明授权

US07652502B2 Field programmable gate arrays using resistivity sensitive memories 有权
标题翻译：使用电阻率敏感存储器的现场可编程门阵列
公开(公告)号：US07652502B2
公开(公告)日：2010-01-26
申请号：US12006006
申请日：2007-12-29
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , H03K19/1776 , H03K19/17772 , H03K19/1778
摘要： Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane.
摘要翻译：描述了使用电阻率敏感存储器的现场可编程门阵列，包括包括可配置逻辑的可编程单元，连接到可配置逻辑以提供可配置逻辑的功能的存储器，存储器包括非易失性可重写存储元件，敏感存储器元件，连接到可配置逻辑的输入/输出逻辑和与其他单元通信的存储器。存储器元件可以是在没有电力的情况下存储数据的两端电阻率敏感存储器元件。两端存储器元件可以将数据存储为可以通过在存储器元件的端子上施加读取电压而被非破坏性地读取的多个导电率分布，并且可以通过施加写入电压将数据写入到两端存储器元件跨越终端。存储器可以垂直配置在一个或多个垂直堆叠在一起的并且位于逻辑平面之上的存储器平面中。

18. 发明授权

US07652500B1 Reconfiguration of programmable logic devices 有权
标题翻译：可编程逻辑器件的重新配置
公开(公告)号：US07652500B1
公开(公告)日：2010-01-26
申请号：US12044842
申请日：2008-03-07
申请人： Howard Tang , Ju Shen , San-Ta Kow
发明人： Howard Tang , Ju Shen , San-Ta Kow
IPC分类号： H03K19/173
CPC分类号： H03K19/17772 , H03K19/17744 , H03K19/17764
摘要： Improved reconfiguration techniques are provided for programmable logic devices (PLDs). For example, in accordance with an embodiment of the present invention, a programmable logic device includes logic blocks, input/output blocks and corresponding input/output pins, and configuration memory. The PLD also includes registers adapted to capture output signal values of the input/output pins before a reconfiguration of the programmable logic device and to provide the captured values on the input/output pins during the reconfiguration of the PLD.
摘要翻译：为可编程逻辑器件（PLD）提供了改进的重新配置技术。例如，根据本发明的实施例，可编程逻辑器件包括逻辑块，输入/输出块和相应的输入/输出引脚和配置存储器。 PLD还包括适用于在可编程逻辑器件重新配置之前捕获输入/输出引脚的输出信号值并在PLD重新配置期间在输入/输出引脚上提供捕获值的寄存器。

19. 发明授权

US07550994B1 Programmable logic device with on-chip nonvolatile user memory 有权
标题翻译：具有片上非易失性用户存储器的可编程逻辑器件
公开(公告)号：US07550994B1
公开(公告)日：2009-06-23
申请号：US11668325
申请日：2007-01-29
申请人： Rafael C. Camarota , Thomas H. White
发明人： Rafael C. Camarota , Thomas H. White
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H03K19/17772 , G11C7/20 , H03K19/1776
摘要： A programmable logic integrated circuit has user-accessible nonvolatile memory for use by the programmable logic. In a specific embodiment, the programmable logic integrated circuit has a programmable logic array portion and a nonvolatile memory array portion. The nonvolatile memory array portion is segregated into a boot data part and a user data partition. The boot data partition holds data for configuring the programmable logic portion on power up, and the user data partition is for use by the programmable logic. A user can store and retrieve data from the user data partition. A built-in oscillator can be programmably connected from the nonvolatile memory portion to the PLD portion.
摘要翻译：可编程逻辑集成电路具有由可编程逻辑使用的用户可访问的非易失性存储器。在具体实施例中，可编程逻辑集成电路具有可编程逻辑阵列部分和非易失性存储器阵列部分。非易失性存储器阵列部分被分离成引导数据部分和用户数据分区。引导数据分区保存用于在上电时配置可编程逻辑部分的数据，并且用户数据分区由可编程逻辑使用。用户可以从用户数据分区存储和检索数据。内置振荡器可以从非易失性存储器部分可编程地连接到PLD部分。

20. 发明授权

US07463058B2 Programmable array logic circuit employing non-volatile ferromagnetic memory cells 失效
标题翻译：采用非易失性铁磁存储单元的可编程阵列逻辑电路
公开(公告)号：US07463058B2
公开(公告)日：2008-12-09
申请号：US11889908
申请日：2007-08-17
申请人： Richard M. Lienau
发明人： Richard M. Lienau
IPC分类号： H03K19/177
CPC分类号： G11C11/18 , G11C7/22 , G11C11/15 , G11C2207/2227 , H03K17/6871 , H03K19/177 , H03K19/17736 , H03K19/1776 , H03K19/17772 , H03K19/1778 , H03K19/17784
摘要： A programmable array logic circuit whose temporary memory circuitry employs single bit non-volatile ferromagnetic memory cells. The ferromagnetic memory cells or bits store data even when there is no power provided to the circuitry, thus saving power during operation of the programmable logic circuitry, and ensuring that there is no loss of the data should there be a temporary power shut down. Additionally, the ferromagnetic cells provide for indefinite number of switching actions on the data without degradation to the capacity to store data therein. The invention provides an integrated circuit, comprising a programmable logic circuit array having product lines and input lines therein, and a storage register circuit. The storage register circuit has a ferromagnetic bit and sensor coupled to store a remnant control signal and an output transistor, coupled to be responsive to the remnant control signal on its gate, and coupled between an input and product line. Additionally, the integrated circuit may further include a logical AND array and a logical OR array.
摘要翻译：一种可编程阵列逻辑电路，其临时存储器电路采用单位非易失性铁磁存储器单元。铁磁存储器单元或位存储数据，即使没有电力提供给电路，从而在可编程逻辑电路的操作期间节省功率，并且确保在暂时停电时不会丢失数据。此外，铁磁单元提供对数据的不确定数量的切换动作，而不降低存储数据的能力。本发明提供一种集成电路，包括其中具有产品线和输入线的可编程逻辑电路阵列和存储寄存器电路。存储寄存器电路具有铁磁位和传感器，其耦合以存储剩余控制信号和输出晶体管，耦合以响应于其栅极上的剩余控制信号，并耦合在输入和产品线之间。此外，集成电路还可以包括逻辑AND阵列和逻辑OR阵列。

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