专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08779799B2 Logic circuit 有权
标题翻译：逻辑电路
公开(公告)号：US08779799B2
公开(公告)日：2014-07-15
申请号：US13467500
申请日：2012-05-09
申请人： Yoshiya Takewaki
发明人： Yoshiya Takewaki
IPC分类号： H03K19/20 , G11C11/34
CPC分类号： H03K19/017581 , H03K19/0948 , H03K19/1776 , H03K19/17772
摘要： A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile.
摘要翻译：提供一种逻辑电路，即使在未提供电源电位时也能够保持逻辑电路的开关状态，在供电之后逻辑块的启动时间短，可以以低功耗工作，并且可以容易地在NAND电路和NOR电路之间切换。在NAND电路和NOR电路之间的切换是通过包括氧化物半导体的晶体管切换节点处的电荷保持状态来实现的。通过使用作为晶体管的宽带隙半导体的氧化物半导体材料，可以充分降低晶体管的截止电流; 因此，在节点处保持的电荷状态可以是非易失性的。

12. 发明申请

US20140140397A1 LOGIC DEVICES, DIGITAL FILTERS AND VIDEO CODECS INCLUDING LOGIC DEVICES, AND METHODS OF CONTROLLING LOGIC DEVICES 审中-公开
标题翻译：逻辑设备，数字滤波器和包括逻辑设备的视频编码器以及控制逻辑设备的方法
公开(公告)号：US20140140397A1
公开(公告)日：2014-05-22
申请号：US13963015
申请日：2013-08-09
申请人： Samsung Electronics Co., Ltd.
发明人： Ho-jung KIM , U-in CHUNG , Hyun-sik CHOI
IPC分类号： H04N19/593 , H03K19/177
CPC分类号： H04N19/17 , G11C11/41 , G11C14/009 , G11C29/028 , H03K19/17748 , H03K19/17772 , H03K19/17776
摘要： A logic device includes: a function block and a configuration block. The function block is configurable to perform operations associated with a plurality of operation modes. The configuration block is configured to configure the function block to perform an operation associated with any one of the plurality of operation modes. The logic device also includes a controller configured to control the configuration block so that the function block is configured to perform the operation.
摘要翻译：逻辑器件包括：功能块和配置块。功能块可配置为执行与多种操作模式相关联的操作。配置块被配置为配置功能块以执行与多个操作模式中的任何一个相关联的操作。逻辑设备还包括控制器，其被配置为控制配置块，使得功能块被配置为执行操作。

13. 发明申请

US20130321025A1 PROGRAMMABLE LOGIC DEVICE 有权
公开(公告)号：US20130321025A1
公开(公告)日：2013-12-05
申请号：US13901644
申请日：2013-05-24
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yoshiyuki Kurokawa , Takayuki Ikeda
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/0944 , H03K19/1737 , H03K19/177 , H03K19/17772 , H03K19/17776
摘要： A PLD in which a configuration memory is formed using a nonvolatile memory with a small number of transistors and in which the area of a region where the configuration memory is disposed is reduced is provided. Further, a PLD that is easily capable of dynamic reconfiguration and has a short startup time is provided. A programmable logic device including a memory element, a selector, and an output portion is provided. The memory element includes a transistor in which a channel is formed in an oxide semiconductor film, and a storage capacitor and an inverter which are connected to one of a source and a drain of the transistor. The inverter is connected to the selector. The selector is connected to the output portion.

14. 发明授权

US08415977B1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08415977B1
公开(公告)日：2013-04-09
申请号：US13469930
申请日：2012-05-11
申请人： Masato Oda , Shinichi Yasuda
发明人： Masato Oda , Shinichi Yasuda
IPC分类号： H03K19/177
CPC分类号： H03K19/17784 , H03K19/17772
摘要： A semiconductor integrated circuit in an embodiment includes a first circuit group that includes at least one first logic block and a second circuit group that includes second logic blocks. The number of the second logic blocks is greater than the number of the first logic blocks. The first circuit group includes a first switching block and a first power control circuit. The first power control circuit commonly controls a start of power supply and a stop of the power supply for the first logic block and the first switching block. The second circuit group includes second switching blocks and a second power control circuit. The second power control circuit commonly controls a start of power supply and a stop of the power supply for the second logic blocks and the second switching blocks.
摘要翻译：实施例中的半导体集成电路包括包括至少一个第一逻辑块的第一电路组和包括第二逻辑块的第二电路组。第二逻辑块的数量大于第一逻辑块的数量。第一电路组包括第一开关块和第一功率控制电路。第一功率控制电路通常控制第一逻辑块和第一切换块的电源的开始和电源的停止。第二电路组包括第二开关块和第二功率控制电路。第二功率控制电路通常控制第二逻辑块和第二切换块的电源的开始和电源的停止。

15. 发明申请

US20120311365A1 PROGRAMMABLE LOGIC DEVICE 有权
标题翻译：可编程逻辑器件
公开(公告)号：US20120311365A1
公开(公告)日：2012-12-06
申请号：US13477192
申请日：2012-05-22
申请人： Seiichi Yoneda , Jun Koyama , Yutaka Shionoiri , Masami Endo , Hiroki Dembo , Tatsuji Nishijima , Hidetomo Kobayashi , Kazuaki Ohshima
发明人： Seiichi Yoneda , Jun Koyama , Yutaka Shionoiri , Masami Endo , Hiroki Dembo , Tatsuji Nishijima , Hidetomo Kobayashi , Kazuaki Ohshima
IPC分类号： G06F1/32
CPC分类号： H03K19/173 , G06F1/3243 , G06F3/0679 , H03K19/17772 , Y02D10/152
摘要： An object is to provide a programmable logic device configured to keep a connection state of logic circuits even while power supply voltage is stopped. The programmable logic device includes arithmetic circuits each of whose logic state can be changed; a configuration changing circuit changing the logic states of the arithmetic circuits; a power supply control circuit controlling supply of power supply voltage to the arithmetic circuits; a state memory circuit storing data on the logic states and data on states of the power supply voltage of the arithmetic circuits; and an arithmetic state control circuit controlling the configuration changing circuit and the power supply control circuit in accordance with the data stored in the state memory circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the configuration changing circuit and each of the arithmetic circuits.
摘要翻译：目的是提供一种可编程逻辑器件，其被配置为即使在电源电压停止时仍保持逻辑电路的连接状态。可编程逻辑器件包括可以改变其逻辑状态的运算电路; 配置改变电路改变运算电路的逻辑状态; 电源控制电路，控制对所述运算电路的电源电压供给; 存储关于逻辑状态的数据的状态存储电路和关于运算电路的电源电压的状态的数据; 以及算术状态控制电路，根据存储在状态存储电路中的数据控制配置改变电路和电源控制电路。在配置改变电路和每个运算电路之间设置有在氧化物半导体层中形成沟道形成区的晶体管。

16. 发明申请

US20120292616A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120292616A1
公开(公告)日：2012-11-22
申请号：US13473014
申请日：2012-05-16
申请人： Kazuaki OHSHIMA
发明人： Kazuaki OHSHIMA
IPC分类号： H01L27/06
CPC分类号： H01L27/105 , H01L27/0605 , H01L27/0688 , H01L27/092 , H01L27/108 , H01L27/1203 , H03K19/0013 , H03K19/1776 , H03K19/17772
摘要： A semiconductor device having a novel structure is provided. The semiconductor device includes a first p-type transistor, a second n-type transistor, a third transistor, and a fourth transistor. One of a source and a drain of the third transistor is connected to a wiring supplying first potential, and the other is connected to one of a source and a drain of the first transistor. One of a source and a drain of the second transistor is connected to the other of the source and the drain of the first transistor, and the other is connected to one of a source and a drain of the fourth transistor. The other of the source and the drain of the fourth transistor is connected to a wiring supplying second potential lower than the first potential. An oxide semiconductor material is used in channel formation regions of the third transistor and the fourth transistor.
摘要翻译：提供具有新颖结构的半导体器件。半导体器件包括第一p型晶体管，第二n型晶体管，第三晶体管和第四晶体管。第三晶体管的源极和漏极之一连接到提供第一电位的布线，另一个连接到第一晶体管的源极和漏极之一。第二晶体管的源极和漏极之一连接到第一晶体管的源极和漏极中的另一个，另一个连接到第四晶体管的源极和漏极之一。第四晶体管的源极和漏极中的另一个连接到提供低于第一电位的第二电位的布线。在第三晶体管和第四晶体管的沟道形成区域中使用氧化物半导体材料。

17. 发明申请

US20110175646A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110175646A1
公开(公告)日：2011-07-21
申请号：US13005557
申请日：2011-01-13
申请人： Yasuhiko TAKEMURA , Shunpei YAMAZAKI
发明人： Yasuhiko TAKEMURA , Shunpei YAMAZAKI
IPC分类号： H03K19/177
CPC分类号： H03K19/0013 , H01L27/0629 , H01L29/7869 , H01L2924/0002 , H03K17/161 , H03K19/173 , H03K19/17724 , H03K19/17736 , H03K19/1776 , H03K19/17772 , H03K19/17784 , H01L2924/00
摘要： It is an object to provide a semiconductor device in which power consumption can be reduced. It is another object to provide a highly reliable semiconductor device using a programming cell, such as a programmable logic device (PLD). In accordance with a change in a configuration of connections between basic blocks, power supply voltage furnishing to the basic blocks is changed. That is, when the structure of connections between the basic blocks is such that a basic block does not contribute to a circuit, the supply of the power supply voltage to this basic block is stopped. Further, the supply of the power supply voltage to the basic blocks is controlled using a programming cell formed using a field effect transistor whose channel formation region is formed using an oxide semiconductor, the field effect transistor having extremely low off-state current or extremely low leakage current.
摘要翻译：本发明的目的是提供能够降低功耗的半导体装置。另一个目的是提供使用诸如可编程逻辑器件（PLD）之类的编程单元的高度可靠的半导体器件。根据基本块之间的连接配置的变化，改变基本块的供电电压。也就是说，当基本块之间的连接结构使得基本块不对电路有贡献时，停止向该基本块提供电源电压。此外，使用使用使用氧化物半导体形成沟道形成区域的场效应晶体管形成的编程单元来控制对基本块的电源电压的供给，场效应晶体管具有极低的截止电流或极低漏电流。

18. 发明授权

US07902868B2 Field programmable gate arrays using resistivity sensitive memories 有权
标题翻译：使用电阻率敏感存储器的现场可编程门阵列
公开(公告)号：US07902868B2
公开(公告)日：2011-03-08
申请号：US12657678
申请日：2010-01-25
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , H03K19/1776 , H03K19/17772 , H03K19/1778
摘要： Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane.
摘要翻译：描述了使用电阻率敏感存储器的现场可编程门阵列，包括包括可配置逻辑的可编程单元，连接到可配置逻辑以提供可配置逻辑的功能的存储器，存储器包括非易失性可重写存储元件，敏感存储器元件，连接到可配置逻辑的输入/输出逻辑和与其他单元通信的存储器。存储器元件可以是在没有电力的情况下存储数据的两端电阻率敏感存储器元件。两端存储器元件可以将数据存储为可以通过在存储器元件的端子上施加读取电压而被非破坏性地读取的多个导电率分布，并且可以通过施加写入电压将数据写入到两端存储器元件跨越终端。存储器可以垂直配置在一个或多个垂直堆叠在一起的并且位于逻辑平面之上的存储器平面中。

19. 发明申请

US20100134144A1 Field programmable gate arrays using resistivity sensitive memories 有权
公开(公告)号：US20100134144A1
公开(公告)日：2010-06-03
申请号：US12657678
申请日：2010-01-25
申请人： Robert Norman
发明人： Robert Norman
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , H03K19/1776 , H03K19/17772 , H03K19/1778
摘要： Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane.

20. 发明申请

US20100023736A1 RECONFIGURABLE CIRCUIT, RESET METHOD, AND CONFIGURATION INFORMATION GENERATION DEVICE 审中-公开
标题翻译：可重构电路，复位方法和配置信息生成装置
公开(公告)号：US20100023736A1
公开(公告)日：2010-01-28
申请号：US12520909
申请日：2008-10-30
申请人： Takashi Morimoto , Shinichiro Nishioka , Koji Asai
发明人： Takashi Morimoto , Shinichiro Nishioka , Koji Asai
IPC分类号： G06F9/00 , G06F9/30 , G06F9/45
CPC分类号： H03K19/17772 , G06F1/24 , H03K19/17756 , H03K19/1776
摘要： The present invention provides a reconfigurable circuit that comprises a plurality of reconfiguration cells and changes a configuration of a computation processing unit included in each of the reconfiguration cells. Here, each of the reconfiguration cells further includes: a computation storage unit operable to store a result of a computation performed by the computation processing unit; a flag holding unit operable to hold an initialization flag indicating whether an initialization of the computation storage unit is required; and an initialization control unit operable to, during the configuration change of the computation processing unit, control the initialization of the computation storage unit based on the initialization flag held by the flag holding unit.
摘要翻译：本发明提供一种可重构电路，其包括多个重新配置单元，并且改变每个重新配置单元中包括的计算处理单元的配置。这里，每个重新配置单元还包括：计算存储单元，用于存储由计算处理单元执行的计算结果; 标记保持单元，用于保持指示是否需要计算存储单元的初始化的初始化标志; 以及初始化控制单元，其可操作以在所述计算处理单元的配置改变期间，基于由所述标志保持单元保持的初始化标志来控制所述计算存储单元的初始化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式