专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100023736A1 RECONFIGURABLE CIRCUIT, RESET METHOD, AND CONFIGURATION INFORMATION GENERATION DEVICE 审中-公开
标题翻译：可重构电路，复位方法和配置信息生成装置
公开(公告)号：US20100023736A1
公开(公告)日：2010-01-28
申请号：US12520909
申请日：2008-10-30
申请人： Takashi Morimoto , Shinichiro Nishioka , Koji Asai
发明人： Takashi Morimoto , Shinichiro Nishioka , Koji Asai
IPC分类号： G06F9/00 , G06F9/30 , G06F9/45
CPC分类号： H03K19/17772 , G06F1/24 , H03K19/17756 , H03K19/1776
摘要： The present invention provides a reconfigurable circuit that comprises a plurality of reconfiguration cells and changes a configuration of a computation processing unit included in each of the reconfiguration cells. Here, each of the reconfiguration cells further includes: a computation storage unit operable to store a result of a computation performed by the computation processing unit; a flag holding unit operable to hold an initialization flag indicating whether an initialization of the computation storage unit is required; and an initialization control unit operable to, during the configuration change of the computation processing unit, control the initialization of the computation storage unit based on the initialization flag held by the flag holding unit.
摘要翻译：本发明提供一种可重构电路，其包括多个重新配置单元，并且改变每个重新配置单元中包括的计算处理单元的配置。这里，每个重新配置单元还包括：计算存储单元，用于存储由计算处理单元执行的计算结果; 标记保持单元，用于保持指示是否需要计算存储单元的初始化的初始化标志; 以及初始化控制单元，其可操作以在所述计算处理单元的配置改变期间，基于由所述标志保持单元保持的初始化标志来控制所述计算存储单元的初始化。

2. 发明授权

US09319275B2 Communication device, communication method, and communication program 有权
标题翻译：通信设备，通信方式和通信程序
公开(公告)号：US09319275B2
公开(公告)日：2016-04-19
申请号：US14122507
申请日：2012-04-27
申请人： Satoshi Senga , Yuusaku Ohta , Shinichiro Nishioka
发明人： Satoshi Senga , Yuusaku Ohta , Shinichiro Nishioka
IPC分类号： G06F15/177 , H04L12/24 , H04L29/08 , H04W84/20 , H04W12/08 , H04W4/00
CPC分类号： H04L41/0866 , H04L67/141 , H04W4/80 , H04W12/08 , H04W84/20
摘要： An objective of the present invention is to determine a function of each communication apparatus with few steps. A first communication apparatus (100) is capable of carrying out at least one of a function of an apparatus which receives an access thereto from a second communication apparatus (200), and a function of a host which accesses the second communication apparatus (200). The first communication apparatus (100) comprises: an access request issuing unit (140) which issues a request which denotes the function thereof to the second communication apparatus (200); and a conflict assessment unit (150) which, either when the request and a request which the second communication apparatus (200) has issued conflict or when the request is rejected, makes the access request issuing unit (140) reissue a request to the second communication apparatus (200) which denotes another function.
摘要翻译：本发明的目的是以几步来确定每个通信装置的功能。第一通信装置（100）能够执行从第二通信装置（200）接收对其的装置的功能和访问第二通信装置（200）的主机的功能中的至少一个，。第一通信装置（100）包括：向第二通信装置（200）发出表示其功能的请求的接入请求发布单元（140）; 以及冲突评估单元（150），当所述请求和所述第二通信装置（200）发出冲突的请求或所述请求被拒绝时，使所述访问请求发布单元（140）向所述第二通信装置重新发出请求通信装置（200），其表示另一功能。

3. 发明申请

US20100148820A1 PROGRAMMABLE DEVICE, CONTROL METHOD OF DEVICE AND INFORMATION PROCESSING SYSTEM 有权
标题翻译：可编程器件，器件控制方法和信息处理系统
公开(公告)号：US20100148820A1
公开(公告)日：2010-06-17
申请号：US12598099
申请日：2008-09-18
申请人： Shinichiro Nishioka
发明人： Shinichiro Nishioka
IPC分类号： H03K19/177
CPC分类号： H03K19/17772 , H03K19/17784
摘要： A programmable device can operate at high speed while reducing power consumption. The programmable device (2) includes a plurality of processing tiles (11) each including a configuration memory (21) and a core logic (22), a configuration control unit (13) for programming them, and a power control unit (12) for cutting off a power supply depending on the operating state thereof. Power supply of the core logic (22) is cut off after saving the internal state of the core logic (22) to the configuration memory (21), and power is supplied again to the core logic (22) before the internal state is restored from the configuration memory (21) to the core logic (22), thus saving power while maintaining the internal state.
摘要翻译：可编程器件可以高速运行，同时降低功耗。可编程装置（2）包括多个处理瓦片（11），每个处理瓦片包括配置存储器（21）和核心逻辑（22），用于对它们进行编程的配置控制单元（13）以及功率控制单元（12）用于根据其工作状态切断电源。在将内核逻辑（22）的内部状态保存到配置存储器（21）之后，核心逻辑（22）的电源被切断，并且在内部状态恢复之前再次向核心逻辑（22）供电。从配置存储器（21）到核心逻辑（22），从而在保持内部状态的同时节省功率。

4. 发明授权

US08660125B2 Node device, integrated circuit and control method in ring transmission system 有权
标题翻译：环形传输系统中的节点设备，集成电路和控制方法
公开(公告)号：US08660125B2
公开(公告)日：2014-02-25
申请号：US13386756
申请日：2011-05-24
申请人： Shinichiro Nishioka
发明人： Shinichiro Nishioka
IPC分类号： H04L12/56 , H04L12/427
CPC分类号： H04L12/437 , H04L12/40013
摘要： A node device in a ring transmission system in which a plurality of node devices are connected as a ring via serial links has a PHY transitioning between a normal mode and a loopback mode with timing that maintains symbol lock between an idle frame transmitted to a later serial link in the normal mode according a transmission instruction, and an idle frame from an earlier node device looped back for output to a later serial link during the loopback mode, thus performing relay processing on non-locally addressed data packets during the loopback mode.
摘要翻译：通过串行链路将多个节点设备作为环路连接的环形传输系统中的节点设备具有正常模式和环回模式之间的PHY转换，其中定时保持发送到后续串行的空闲帧之间的符号锁定在回送模式期间，根据传输指令以及来自较早节点设备的空闲帧循环输出到稍后的串行链路，从而在环回模式期间对非本地寻址的数据分组执行中继处理。

5. 发明授权

US08576704B2 Communication system, communication device, integrated circuit, and communication method 有权
标题翻译：通信系统，通信设备，集成电路和通信方式
公开(公告)号：US08576704B2
公开(公告)日：2013-11-05
申请号：US13059263
申请日：2010-03-17
申请人： Shinichiro Nishioka
发明人： Shinichiro Nishioka
IPC分类号： G01R31/08
CPC分类号： H04L12/42 , H04L12/12 , Y02D50/20 , Y02D50/40
摘要： A communication system includes communication devices that are connected with one another in a ring via a serial link. In the communication system, one communication device issues a standby packet for causing each communication device connected to a part of the link that is not involved with data transfer to switch to standby mode. Each communication device connected to this part of the link relays the standby packet from an immediately preceding communication device in the link to an immediately succeeding communication device in the link, and after relaying the standby packet, causes the own device to switch to standby mode. Further, a communication device that performs communication with said one communication device issues a loopback packet for causing each communication device connected to a part of the link that is involved with data transfer to switch to loopback mode. Each communication device connected to this part of the link relays the loopback packet from an immediately preceding communication device in the link to an immediately succeeding communication device in the link, and after relaying the loopback packet, causes the own device to switch to loopback mode.
摘要翻译：通信系统包括通过串行链路在环中彼此连接的通信设备。在通信系统中，一个通信设备发出备用分组，使得连接到不涉及数据传输的链路的一部分的每个通信设备切换到待机模式。连接到链路的这一部分的每个通信设备将链路中的紧接在前的通信设备的备用分组中继到链路中紧接着的通信设备，并且在中继备用分组之后，使得自己的设备切换到待机模式。此外，与所述一个通信设备进行通信的通信设备发出环回分组，使得连接到涉及数据传输的链路的一部分的每个通信设备切换到环回模式。与链路的这一部分连接的每个通信装置将链路中的紧急通信装置的环回分组中继到链路中的紧随其后的通信装置，并且在中继环回分组之后，使得本装置切换到环回模式。

6. 发明授权

US08520563B2 Interface device, communications system, non-volatile storage device, communication mode switching method and integrated circuit 有权
标题翻译：接口设备，通信系统，非易失性存储设备，通信模式切换方法和集成电路
公开(公告)号：US08520563B2
公开(公告)日：2013-08-27
申请号：US12995558
申请日：2009-05-29
申请人： Tadashi Ono , Isao Kato , Hideyuki Yamada , Shinichiro Nishioka , Hiroshi Suenaga , Tsutomu Sekibe
发明人： Tadashi Ono , Isao Kato , Hideyuki Yamada , Shinichiro Nishioka , Hiroshi Suenaga , Tsutomu Sekibe
IPC分类号： H04B1/44
CPC分类号： H04L5/16 , H04L5/18 , H04L25/14
摘要： A host device and a slave device are set to a full-duplex mode by temporarily switching the communication direction of a first transmission channel or a second transmission channel after completing transmission and reception of a predetermined number of data packets in the half-duplex mode. The host device or the slave device can thus transmit an interrupt request, such as a request associated with a wait status or a busy status, to its communication target using the temporary full-duplex mode. This enables the host device or the slave device to process such an interrupt request during high-speed data transfer performed in the half-duplex mode.
摘要翻译：在半双工模式下完成预定数量的数据分组的发送和接收之后，通过临时切换第一传输信道或第二传输信道的通信方向，将主机设备和从设备设置为全双工模式。因此主机设备或从设备可以使用临时全双工模式向其通信目标传送诸如与等待状态或忙状态相关联的请求的中断请求。这使得主机设备或从设备在半双工模式下执行的高速数据传输期间处理这样的中断请求。

7. 发明申请

US20110276748A1 NON-VOLATILE STORAGE DEVICE, HOST DEVICE, STORAGE SYSTEM, DATA COMMUNICATION METHOD AND PROGRAM 有权
标题翻译：非易失存储设备，主机设备，存储系统，数据通信方法和程序
公开(公告)号：US20110276748A1
公开(公告)日：2011-11-10
申请号：US13144594
申请日：2010-12-01
申请人： Masayuki Toyama , Tadashi Ono , Shinichiro Nishioka
发明人： Masayuki Toyama , Tadashi Ono , Shinichiro Nishioka
IPC分类号： G06F12/02
CPC分类号： G06F9/4403
摘要： In a memory system including a host device and one or more nonvolatile memory devices, the host device reads, from a nonvolatile memory device connected in the system, a boot code used to operate a CPU of the host device before the CPU is activated. The boot code reading process is required to be performed with a simple method. A host device (2) transmits a first symbol including a synchronous code to a nonvolatile memory device (1). The nonvolatile memory device (1) receives the first symbol from the host device (2), and transmits a first symbol that is identical to the received first symbol to the host device (2), and then transmits a boot code to the host device (2). In this manner, the host device (2) reads a boot code from the nonvolatile memory device 1 with a simple method.
摘要翻译：在包括主机设备和一个或多个非易失性存储设备的存储器系统中，主机设备从连接在系统中的非易失性存储设备中读取用于在CPU被激活之前操作主机设备的CPU的引导代码。引导代码读取过程需要以简单的方法执行。主机设备（2）将包括同步码的第一符号发送到非易失性存储设备（1）。非易失性存储器件（1）从主机（2）接收第一符号，并将与接收到的第一符号相同的第一符号发送到主机（2），然后将引导代码发送到主机（2）。以这种方式，主机设备（2）以简单的方法从非易失性存储设备1读取引导代码。

8. 发明授权

US09379974B2 Transfer control device, integrated circuit thereof, transfer control method, and transfer control system 有权
标题翻译：转移控制装置，集成电路，转移控制方法和转移控制系统
公开(公告)号：US09379974B2
公开(公告)日：2016-06-28
申请号：US13984928
申请日：2012-01-27
申请人： Yuusaku Ohta , Shinichiro Nishioka
发明人： Yuusaku Ohta , Shinichiro Nishioka
IPC分类号： H04L12/741 , H04L12/46 , H04L12/64 , H04L29/12
CPC分类号： H04L45/74 , H04L12/4625 , H04L12/6418 , H04L61/2038
摘要： To achieve efficient data transfer between a first network and a second network, and, in particular, to reduce processing load pertaining to address conversion, a transfer control device in the first network acquires an address of a transfer target device in the second network, and assigns the acquired address to a transfer device in the first network. When data transmitted through the first network is to be transferred to the transfer target device via the transfer device, there is no need to perform address conversion as the transfer device and the transfer target device are assigned the same address.
摘要翻译：为了实现第一网络和第二网络之间的有效数据传输，并且特别地，为了减少与地址转换相关的处理负担，第一网络中的传输控制设备获取第二网络中的传送目标设备的地址，以及将所获取的地址分配给第一网络中的传送设备。当通过第一网络发送的数据将经由传送装置传送到转移目标装置时，不需要执行地址转换作为传送装置，并且传送目标装置被分配相同的地址。

9. 发明授权

US08464020B2 Non-volatile storage device, host device, storage system, data communication method and program 有权
标题翻译：非易失性存储设备，主机设备，存储系统，数据通信方式和程序
公开(公告)号：US08464020B2
公开(公告)日：2013-06-11
申请号：US13144594
申请日：2010-12-01
申请人： Masayuki Toyama , Tadashi Ono , Shinichiro Nishioka
发明人： Masayuki Toyama , Tadashi Ono , Shinichiro Nishioka
IPC分类号： G06F13/00
CPC分类号： G06F9/4403
摘要： In a memory system including a host device and one or more nonvolatile memory devices, the host device reads, from a nonvolatile memory device connected in the system, a boot code used to operate a CPU of the host device before the CPU is activated. The boot code reading process is required to be performed with a simple method. A host device (2) transmits a first symbol including a synchronous code to a nonvolatile memory device (1). The nonvolatile memory device (1) receives the first symbol from the host device (2), and transmits a first symbol that is identical to the received first symbol to the host device (2), and then transmits a boot code to the host device (2). In this manner, the host device (2) reads a boot code from the nonvolatile memory device 1 with a simple method.
摘要翻译：在包括主机设备和一个或多个非易失性存储设备的存储器系统中，主机设备从连接在系统中的非易失性存储设备中读取用于在CPU被激活之前操作主机设备的CPU的引导代码。引导代码读取过程需要以简单的方法执行。主机设备（2）将包括同步码的第一符号发送到非易失性存储设备（1）。非易失性存储器件（1）从主机（2）接收第一符号，并将与接收到的第一符号相同的第一符号发送到主机（2），然后将引导代码发送到主机（2）。以这种方式，主机设备（2）以简单的方法从非易失性存储设备1读取引导代码。

10. 发明申请

US20110268198A1 DRIVER CIRCUIT, RECEIVER CIRCUIT, AND METHOD OF CONTROLLING A COMMUNICATIONS SYSTEM INCLUDING THE CIRCUITS 有权
标题翻译：驱动电路，接收电路和控制包括电路的通信系统的方法
公开(公告)号：US20110268198A1
公开(公告)日：2011-11-03
申请号：US13143233
申请日：2010-11-01
申请人： Shinichiro Nishioka , Yoshihide Komatsu , Hiroshi Suenaga , Kohei Masuda
发明人： Shinichiro Nishioka , Yoshihide Komatsu , Hiroshi Suenaga , Kohei Masuda
IPC分类号： H04L25/00
CPC分类号： H04B1/1615 , H04L25/0272
摘要： In a communications system for differential signals, a driver circuit is connected to a receiver circuit by a pair of differential signal lines. When data is not being transmitted, the differential signal lines are maintained at a predetermined electric potential, and when data is to be transferred, a differential signal is output at predetermined electric potentials. The receiver circuit switches between a power-down state and a normal state when detecting states of the electric potentials of the differential signal lines.
摘要翻译：在用于差分信号的通信系统中，驱动电路通过一对差分信号线连接到接收器电路。当不发送数据时，差分信号线保持在预定电位，并且当数据要被传送时，以预定电位输出差分信号。当检测到差分信号线的电位的状态时，接收器电路在掉电状态和正常状态之间切换。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式