专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09040980B2 Transistor with an oxide semiconductor layer 有权
标题翻译：具有氧化物半导体层的晶体管
公开(公告)号：US09040980B2
公开(公告)日：2015-05-26
申请号：US13046931
申请日：2011-03-14
申请人： Masami Endo
发明人： Masami Endo
IPC分类号： H01L29/10 , H01L29/786 , H01L29/417 , H01L29/423
CPC分类号： H01L29/7869 , H01L29/41733 , H01L29/42384 , H01L29/78642
摘要： It is an object to provide a semiconductor device for high power application which has good properties. A means for solving the above-described problem is to form a transistor described below. The transistor includes a source electrode layer; an oxide semiconductor layer in contact with the source electrode layer; a drain electrode layer in contact with the oxide semiconductor layer; a gate electrode layer part of which overlaps with the source electrode layer, the drain electrode layer, and the oxide semiconductor layer; and a gate insulating layer in contact with an entire surface of the gate electrode layer.
摘要翻译：本发明的目的是提供一种具有良好性能的用于大功率应用的半导体器件。解决上述问题的手段是形成下述的晶体管。晶体管包括源电极层; 与源电极层接触的氧化物半导体层; 与所述氧化物半导体层接触的漏电极层; 其栅电极层部分与源电极层，漏电极层和氧化物半导体层重叠; 以及与栅极电极层的整个表面接触的栅极绝缘层。

2. 发明授权

US08988405B2 Display device and semiconductor device 有权
标题翻译：显示装置和半导体装置
公开(公告)号：US08988405B2
公开(公告)日：2015-03-24
申请号：US12908299
申请日：2010-10-20
申请人： Masami Endo
发明人： Masami Endo
IPC分类号： G06F3/038 , G09G5/00 , G01J1/04 , G01J1/32 , H05B33/08 , H05B37/02 , G06F3/041 , G06F3/042 , H04N1/00 , G02F1/133 , G02F1/1335 , G02F1/1362 , G02F1/137 , H01L27/32
CPC分类号： G01J1/04 , G01J1/32 , G02F1/13318 , G02F2001/13312 , G02F2001/133626 , G02F2001/136281 , G02F2001/136295 , G02F2001/13793 , G02F2201/58 , G02F2203/30 , G02F2203/68 , G06F3/0412 , G06F3/042 , G09G2360/148 , H01L27/3227 , H01L27/3269 , H04N1/00129 , H05B33/0872 , H05B37/0218 , Y02B20/46
摘要： An object is to detect reflected light from an object accurately and to improve accuracy of capturing an image in a photosensor included in a display panel. In the display panel including a photosensor, when an image of an object is captured, light is emitted from a light source to the object and reflected light enters the photosensor. In the case where the incident light is too strong with respect to sensitivity of the photosensor, luminance of the light source is lowered. In the case where the incident light is too weak with respect to sensitivity of the photosensor, the luminance of the light source is increased.
摘要翻译：目的是准确地检测来自物体的反射光，并提高在包含在显示面板中的光电传感器中拍摄图像的精度。在包括光电传感器的显示面板中，当拍摄对象的图像时，从光源发射光到物体，反射光进入光传感器。在入射光相对于光传感器的灵敏度太强的情况下，光源的亮度降低。在入射光相对于光传感器的灵敏度太弱的情况下，光源的亮度增加。

3. 发明授权

US08824192B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08824192B2
公开(公告)日：2014-09-02
申请号：US13455475
申请日：2012-04-25
申请人： Masami Endo
发明人： Masami Endo
IPC分类号： G11C11/24
CPC分类号： H01L27/1225 , H03K17/20
摘要： A semiconductor device that has a simple peripheral circuit configuration, is unlikely to deteriorate due to repetitive data writing operations, and is used as a nonvolatile switch. Even when supply of a power supply voltage is stopped, data on a conduction state is held in a data retention portion connected to a thin film transistor including an oxide semiconductor layer having a channel formation region. The data retention portion is connected to a gate of a field-effect transistor in a current amplifier circuit (in which the field-effect transistor and a bipolar transistor are connected as a Darlington pair), and thus the conduction state is controlled without leaking charge in the data retention portion.
摘要翻译：具有简单的外围电路配置的半导体器件由于重复的数据写入操作而不太可能劣化，并被用作非易失性开关。即使停止供给电源电压，导通状态的数据被保持在连接到包括具有沟道形成区域的氧化物半导体层的薄膜晶体管的数据保持部分中。数据保持部分连接到电流放大器电路中的场效应晶体管的栅极（其中场效应晶体管和双极晶体管作为达林顿对连接），因此导通状态被控制而不泄漏电荷在数据保留部分中。

4. 发明授权

US08781433B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08781433B2
公开(公告)日：2014-07-15
申请号：US13368380
申请日：2012-02-08
申请人： Yoshiyuki Kurokawa , Takayuki Ikeda , Masami Endo , Hiroki Dembo , Daisuke Kawae , Takayuki Inoue , Munehiro Kozuma
发明人： Yoshiyuki Kurokawa , Takayuki Ikeda , Masami Endo , Hiroki Dembo , Daisuke Kawae , Takayuki Inoue , Munehiro Kozuma
IPC分类号： H04B1/28
CPC分类号： G06K19/07749 , G06K7/0008 , G06K19/0716 , G06K2017/0045
摘要： A semiconductor device is provided with a power supply circuit having a function to generate a power supply voltage from a wireless signal and an A/D converter circuit having a function to detect the strength of the wireless signal by an A/D conversion of a voltage generated from the wireless signal. This enables to provide a semiconductor device which does not require replacement of batteries, has few limitations on its physical shape and mass, and has a function to detect a physical position. By formation of the semiconductor device with use of a thin film transistor formed over a plastic substrate, a lightweight semiconductor device, which has flexibility in physical shape and a function to detect a physical location, can be provided at low cost.
摘要翻译：半导体器件具有电源电路，该电源电路具有从无线信号产生电源电压的功能，以及具有通过A / D转换电压来检测无线信号的强度的功能的A / D转换电路由无线信号产生。这能够提供不需要更换电池的半导体器件，其物理形状和质量几乎没有限制，并且具有检测物理位置的功能。通过使用形成在塑料基板上的薄膜晶体管形成半导体器件，可以以低成本提供具有物理形状的灵活性和检测物理位置的功能的轻量级的半导体器件。

5. 发明授权

US08510588B2 Clock generation circuit and semiconductor device including the same 有权
标题翻译：时钟生成电路和包括其的半导体器件
公开(公告)号：US08510588B2
公开(公告)日：2013-08-13
申请号：US13353497
申请日：2012-01-19
申请人： Masami Endo , Takayuki Ikeda , Daisuke Kawae , Yoshiyuki Kurokawa
发明人： Masami Endo , Takayuki Ikeda , Daisuke Kawae , Yoshiyuki Kurokawa
IPC分类号： G06F1/04
CPC分类号： H04L7/0331 , H03L7/00
摘要： Objects of the invention are to provide a clock generation circuit and to provide a semiconductor device including the clock generation circuit. The clock generation circuit includes an edge detection circuit, a reference clock generation circuit, a reference clock counter circuit, and a frequency-divider circuit. The reference clock counter circuit is a circuit which outputs a counter value, which is obtained by counting the number of waves of a reference clock signal outputted from the reference clock generation circuit, in a period of time from when the edge detection circuit detects an edge of a signal which is externally inputted to the edge detection circuit to when the edge detection circuit detects the next edge, to the frequency-divider circuit. The frequency-divider circuit is a circuit which frequency-divides the reference clock signal based on the counter value.
摘要翻译：本发明的目的是提供一种时钟发生电路并提供包括时钟发生电路的半导体器件。时钟产生电路包括边缘检测电路，参考时钟产生电路，参考时钟计数器电路和分频器电路。参考时钟计数器电路是在从边缘检测电路检测到边缘的时间段内输出计数值的电路，该计数值是从基准时钟产生电路输出的基准时钟信号的波数来计算的将外部输入到边缘检测电路的信号当边缘检测电路检测到下一个边沿时，分配给分频器电路。分频器电路是基于计数器值对参考时钟信号进行分频的电路。

6. 发明授权

US08429634B2 Semiconductor device, memory circuit, and machine language program generation device, and method for operating semiconductor device and memory circuit 有权
标题翻译：半导体器件，存储器电路和机器语言程序生成装置，以及用于操作半导体器件和存储器电路的方法
公开(公告)号：US08429634B2
公开(公告)日：2013-04-23
申请号：US11878518
申请日：2007-07-25
申请人： Hiroki Dembo , Yoshiyuki Kurokawa , Masami Endo
发明人： Hiroki Dembo , Yoshiyuki Kurokawa , Masami Endo
IPC分类号： G06F9/45
CPC分类号： G06F8/447 , G06F9/4484
摘要： A semiconductor device has an arithmetic processing circuit provided with an arithmetic circuit and a control circuit and a memory circuit provided with a ROM and a RAM, where the arithmetic processing circuit and the memory circuit are connected to each other through an address bus and a data bus, a machine language program executed using the arithmetic processing circuit is stored in the ROM, the RAM has a plurality of banks, processing data obtained by executing the machine language program is divided into a plurality of stacks to be written to the plurality of banks, and the arithmetic processing circuit is operated in accordance with the machine language program so that, in the plurality of stacks stored in the plurality of banks, a stack of which data is not used until the machine language program is terminated is omitted and contiguous stacks are written to the same bank.
摘要翻译：一种半导体器件具有运算电路和控制电路的运算处理电路和具有ROM和RAM的存储电路，其中算术处理电路和存储电路通过地址总线和数据彼此连接总线，使用算术处理电路执行的机器语言程序被存储在ROM中，RAM具有多个存储体，通过执行机器语言程序获得的处理数据被划分为要写入多个存储体的多个堆叠并且算术处理电路根据机器语言程序进行操作，从而在多个存储体中存储的多个堆栈中省略了在机器语言程序终止之前不使用数据的堆栈，并且连续的堆栈被写入同一家银行。

7. 发明授权

US08374303B2 Clock synchronization circuit and semiconductor device provided therewith 有权
标题翻译：时钟同步电路和提供的半导体器件
公开(公告)号：US08374303B2
公开(公告)日：2013-02-12
申请号：US11820245
申请日：2007-06-19
申请人： Masami Endo , Daisuke Kawae , Yoshiyuki Kurokawa , Takayuki Ikeda
发明人： Masami Endo , Daisuke Kawae , Yoshiyuki Kurokawa , Takayuki Ikeda
IPC分类号： H04L7/00
CPC分类号： H04L7/0331
摘要： An object is to provide a clock synchronization circuit capable of stable communication even in the case where different clock signals are used in a plurality of circuits, and a semiconductor device provided therewith. Circuit for detecting a change point of received data, and outputting a reset signal; reference clock generating means for generating a clock signal; and circuit for counting the clock signals outputted from the reference clock generation means, and resetting a counter value obtained by counting the clock signals in the case where the reset signal is inputted are provided.
摘要翻译：目的在于提供即使在多个电路中使用不同的时钟信号的情况下也能够稳定通信的时钟同步电路以及与其配合的半导体装置。用于检测接收数据的变化点并输出复位信号的电路; 用于产生时钟信号的参考时钟产生装置; 以及用于对从基准时钟产生装置输出的时钟信号进行计数的电路，以及在输入复位信号的情况下复位通过对时钟信号进行计数而获得的计数器值。

8. 发明申请

US20120230138A1 MEMORY ELEMENT AND SIGNAL PROCESSING CIRCUIT 有权
标题翻译：存储元件和信号处理电路
公开(公告)号：US20120230138A1
公开(公告)日：2012-09-13
申请号：US13405422
申请日：2012-02-27
申请人： Masami Endo
发明人： Masami Endo
IPC分类号： G11C7/06 , G11C7/12
CPC分类号： G11C7/06 , G11C7/12 , G11C14/0054 , G11C16/0441 , G11C19/184 , G11C19/28
摘要： A memory element having a novel structure and a signal processing circuit including the memory element are provided. A first circuit, including a first transistor and a second transistor, and a second circuit, including a third transistor and a fourth transistor, are included. A first signal potential and a second signal potential, each corresponding to an input signal, are respectively input to a gate of the second transistor via the first transistor in an on state and to a gate of the fourth transistor via the third transistor in an on state. After that, the first transistor and the third transistor are turned off. The input signal is read out using both the states of the second transistor and the fourth transistor. A transistor including an oxide semiconductor in which a channel is formed can be used for the first transistor and the third transistor.
摘要翻译：提供具有新颖结构的存储元件和包括存储元件的信号处理电路。包括包括第一晶体管和第二晶体管的第一电路和包括第三晶体管和第四晶体管的第二电路。分别对应于输入信号的第一信号电位和第二信号电位经由导通状态的第一晶体管分别输入到第二晶体管的栅极，并经由第三晶体管的导通州。之后，第一晶体管和第三晶体管截止。使用第二晶体管和第四晶体管的状态来读出输入信号。包括其中形成沟道的氧化物半导体的晶体管可以用于第一晶体管和第三晶体管。

9. 发明授权

US08253717B2 Control circuit of display device, and display device, and display device and electronic appliance incorporating the same 有权
标题翻译：显示装置的控制电路，显示装置以及包含该装置的显示装置和电子装置
公开(公告)号：US08253717B2
公开(公告)日：2012-08-28
申请号：US13211779
申请日：2011-08-17
申请人： Masami Endo
发明人： Masami Endo
IPC分类号： G06F3/038
CPC分类号： G09G3/3275 , G09G5/399 , G09G2360/18
摘要： An object is to realize downsizing and cost reduction of a display device by efficiently using a physical region of a memory in a control circuit of the display device. A structure of a video data storage portion of the control circuit is that provided with a video data storage portion for storing video data of an n-th frame (n is a natural number), a video data storage portion for storing video data of an (n+1)th frame, and a video data storage portion for sharing video data of the n-th frame and the (n+1)th frame among received video data.
摘要翻译：目的是通过有效地使用显示装置的控制电路中的存储器的物理区域来实现显示装置的小型化和降低成本。控制电路的视频数据存储部分的结构是设置有用于存储第n帧（n是自然数）的视频数据的视频数据存储部分，用于存储第n帧的视频数据的视频数据存储部分（n + 1）帧，以及用于共享所接收的视频数据中的第n帧和第（n + 1）帧的视频数据的视频数据存储部分。

10. 发明申请

US20120170355A1 STORAGE ELEMENT, STORAGE DEVICE, AND SIGNAL PROCESSING CIRCUIT 有权
标题翻译：存储元件，存储器件和信号处理电路
公开(公告)号：US20120170355A1
公开(公告)日：2012-07-05
申请号：US13341412
申请日：2011-12-30
申请人： Takuro Ohmaru , Masami Endo
发明人： Takuro Ohmaru , Masami Endo
IPC分类号： G11C11/24
CPC分类号： H01L27/1052 , G06F1/3275 , G11C11/24 , G11C14/0009 , G11C19/184 , H01L23/5226 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10897 , H01L28/20 , H01L28/40 , H01L29/24 , H01L29/26 , H01L29/7869 , Y02D10/13 , Y02D10/14
摘要： A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.
摘要翻译：提供能够抑制功耗的信号处理电路。在不向存储元件提供电源电压的期间中，存储在与非易失性存储器相对应的第一存储电路中的数据可以由设置在第二存储电路中的第一电容器保持。通过使用在氧化物半导体层中形成沟道的晶体管，保持在第一电容器中的信号被保持很长时间。因此，存储元件也可以在停止供给电源电压的期间保持存储的内容（数据）。可以将由第一电容器保持的信号转换为与第二晶体管的状态（导通状态或截止状态）对应的信号，并从第二存储电路读取。因此，可以准确地读取原始信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式