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11. 发明授权

US09231113B2 Flash memory with P-type floating gate 有权
标题翻译：带P型浮动门的闪存
公开(公告)号：US09231113B2
公开(公告)日：2016-01-05
申请号：US14531857
申请日：2014-11-03
申请人： SANDISK TECHNOLOGIES INC.
发明人： Kenji Sato
IPC分类号： H01L29/788 , H01L21/28 , H01L27/115 , H01L29/423 , H01L29/49
CPC分类号： H01L29/788 , H01L21/28114 , H01L21/28273 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11541 , H01L29/42324 , H01L29/42376 , H01L29/4916
摘要： Methods for manufacturing non-volatile memory devices including peripheral transistors with reduced and less variable gate resistance are described. In some embodiments, a NAND-type flash memory may include floating-gate transistors and peripheral transistors (or non-floating-gate transistors). The peripheral transistors may include select gate transistors (e.g., drain-side select gates and/or source-side select gates) and/or logic transistors that reside outside of a memory array region. A floating-gate transistor may include a floating gate of a first conductivity type (e.g., n-type) and a control gate including a lower portion of a second conductivity type different from the first conductivity type (e.g., p-type). A peripheral transistor may include a gate including a first layer of the first conductivity type, a second layer of the second conductivity type, and a cutout region including one or more sidewall diffusion barriers that extends through the second layer and a portion of the first layer.
摘要翻译：描述了用于制造包括具有减小和较小的可变栅极电阻的外围晶体管的非易失性存储器件的方法。在一些实施例中，NAND型闪速存储器可以包括浮栅晶体管和外围晶体管（或非浮栅晶体管）。外围晶体管可以包括位于存储器阵列区域外的选择栅极晶体管（例如，漏极侧选择栅极和/或源极选择栅极）和/或逻辑晶体管。浮栅晶体管可以包括第一导电类型（例如，n型）的浮置栅极和包括不同于第一导电类型（例如，p型）的第二导电类型的下部的控制栅极。外围晶体管可以包括包括第一导电类型的第一层，第二导电类型的第二层的栅极和包括延伸穿过第二层的一个或多个侧壁扩散阻挡层的切口区域和第一层的一部分。

12. 发明申请

US20150340375A1 SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE 有权
标题翻译：半导体器件，相关制造方法及相关电子器件
公开(公告)号：US20150340375A1
公开(公告)日：2015-11-26
申请号：US14578937
申请日：2014-12-22
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Lujun ZOU , Yun YANG , Shaobin LI , Shengfen CHIU
IPC分类号： H01L27/115 , H01L29/49
CPC分类号： H01L27/11539 , H01L21/28273 , H01L27/11521 , H01L27/11536 , H01L29/4975
摘要： A method for manufacturing a semiconductor device may include the following steps: preparing a stacked structure; processing the stacked structure to form a first gate structure and a preliminary structure; forming a dielectric material layer that covers at least the first gate structure; forming a dielectric layer using the dielectric material layer, such that a portion of the dielectric layer is positioned between the first gate structure and the preliminary structure; performing an annealing process on at least one of the dielectric material layer and the dielectric layer; processing the preliminary structure to form a second gate structure; and after the annealing process has been performed, forming a first metal silicide member on the second gate structure and/or forming a second metal silicide member on an active region associated with the second gate structure.
摘要翻译：制造半导体器件的方法可以包括以下步骤：制备堆叠结构; 处理堆叠结构以形成第一栅极结构和初步结构; 形成至少覆盖所述第一栅极结构的介电材料层; 使用所述电介质材料层形成介电层，使得所述电介质层的一部分位于所述第一栅极结构和所述初步结构之间; 对介电材料层和电介质层中的至少一个进行退火处理; 处理初步结构形成第二门结构; 并且在已经执行退火处理之后，在第二栅极结构上形成第一金属硅化物构件和/或在与第二栅极结构相关联的有源区上形成第二金属硅化物构件。

13. 发明申请

US20150064894A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20150064894A1
公开(公告)日：2015-03-05
申请号：US14542197
申请日：2014-11-14
申请人： SK hynix Inc.
发明人： Min Gyu KOO
IPC分类号： H01L27/115
CPC分类号： H01L27/11524 , H01L21/02365 , H01L21/28273 , H01L27/11539 , H01L27/1157 , H01L29/788 , H01L29/7881
摘要： The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; at least one first contact hole passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the at least one first contact hole to contact the first conductive layer; and at least one first contact plug connected to the second conductive layer in the first active area, wherein the at least one first contact plug is offset from the at least one first contact hole to overlap the dielectric layer.
摘要翻译：半导体器件包括具有由第一隔离层限定的第一有源区的半导体衬底; 形成在半导体衬底上的栅极绝缘层; 形成在所述栅绝缘层上的第一导电层; 形成在所述第一导电层上的电介质层; 至少一个穿过介电层的第一接触孔; 形成在所述电介质层上的第二导电层，所述第二导电层填充所述至少一个第一接触孔以接触所述第一导电层; 以及至少一个第一接触插塞，其连接到所述第一有源区域中的所述第二导电层，其中所述至少一个第一接触插塞从所述至少一个第一接触孔偏移以与所述介电层重叠。

14. 发明授权

US08928092B2 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08928092B2
公开(公告)日：2015-01-06
申请号：US13940721
申请日：2013-07-12
申请人： Samsung Electronics Co., Ltd.
发明人： Hauk Han , Yong-Il Kwon , JungSuk Oh , Tae sun Ryu , Jeonggil Lee
IPC分类号： H01L27/088 , H01L29/788 , H01L23/52 , H01L21/28 , H01L27/115
CPC分类号： H01L27/11531 , H01L21/28273 , H01L23/52 , H01L27/11521 , H01L27/11526 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L29/42328 , H01L29/4238 , H01L29/4941 , H01L29/788 , H01L29/7881 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.
摘要翻译：半导体器件包括在半导体衬底上的下绝缘图案，下绝缘图案上的下栅极图案和由掺杂多晶硅层形成的残留绝缘图案，具有露出下栅极图案的顶表面的一部分的开口，剩余绝缘图案上的上栅极图案，填充开口的上栅极图案，以及与下栅极图案的顶表面的部分接触并在残留绝缘图案和上栅极图案之间延伸的扩散阻挡图案。

15. 发明申请

US20130330893A1 INTEGRATING FORMATION OF A REPLACEMENT GATE TRANSISTOR AND A NON-VOLATILE MEMORY CELL USING A HIGH-K DIELECTRIC 有权
标题翻译：使用高K电介质形成替代栅极晶体管和非易失性存储器单元
公开(公告)号：US20130330893A1
公开(公告)日：2013-12-12
申请号：US13491771
申请日：2012-06-08
申请人： Mark D. Hall , Mehul D. Shroff
发明人： Mark D. Hall , Mehul D. Shroff
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/28282 , H01L27/11534 , H01L27/11539 , H01L27/11573 , H01L29/66545 , H01L29/66833
摘要： A first dielectric layer is formed in an NVM region and a logic region. A charge storage layer is formed over the first dielectric layer and is patterned to form a dummy gate in the logic region and a charge storage structure in the NVM region. A second dielectric layer is formed in the NVM and logic regions which surrounds the charge storage structure and dummy gate. The second dielectric layer is removed from the NVM region while protecting the second dielectric layer in the logic region. The dummy gate is removed, resulting in an opening. A third dielectric layer is formed over the charge storage structure and within the opening, and a gate layer is formed over the third dielectric layer and within the opening, wherein the gate layer forms a control gate layer in the NVM region and the gate layer within the opening forms a logic gate.
摘要翻译：在NVM区域和逻辑区域中形成第一介电层。电荷存储层形成在第一电介质层之上，并被图案化以在逻辑区域中形成伪栅极，并在NVM区域中形成电荷存储结构。在NVM和围绕电荷存储结构和虚拟栅极的逻辑区域中形成第二介质层。从NVM区域去除第二介电层，同时保护逻辑区域中的第二介质层。去除虚拟门，导致开口。在电荷存储结构之上和开口内形成第三电介质层，并且栅极层形成在第三介电层之上和开口内，其中栅极层在NVM区域内形成控制栅极层，在栅极层内形成栅极层开幕式构成逻辑门。

16. 发明申请

US20100159661A1 NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20100159661A1
公开(公告)日：2010-06-24
申请号：US12718011
申请日：2010-03-05
申请人： Shunpei YAMAZAKI
发明人： Shunpei YAMAZAKI
IPC分类号： H01L21/8246 , H01L21/336
CPC分类号： H01L27/1237 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11536 , H01L27/11539 , H01L27/11546 , H01L27/1214 , H01L29/42324
摘要： An object of the present invention is to provide a nonvolatile semiconductor storage device with a superior charge holding characteristic in which highly-efficient writing is possible at low voltage, and to provide a manufacturing method thereof.The nonvolatile semiconductor storage device includes a semiconductor film having a pair of impurity regions formed apart from each other and a channel formation region provided between the impurity regions; and a first insulating film, a charge accumulating layer, a second insulating film, and a conductive film functioning as a gate electrode layer which are provided over the channel formation region. In the nonvolatile semiconductor storage device, a second barrier formed by the first insulating film against a charge of the charge accumulating layer is higher in energy than a first barrier formed by the first insulating film against a charge of the semiconductor film.
摘要翻译：本发明的目的是提供一种具有优异的电荷保持特性的非易失性半导体存储装置，其中可以在低电压下进行高效写入，并提供其制造方法。非易失性半导体存储装置包括具有彼此分开形成的一对杂质区域和设置在杂质区域之间的沟道形成区域的半导体膜; 以及设置在沟道形成区域上的用作栅电极层的第一绝缘膜，电荷累积层，第二绝缘膜和导电膜。在非易失性半导体存储装置中，由第一绝缘膜与电荷蓄积层的电荷形成的第二阻挡层的能量比由第一绝缘膜形成的抵抗半导体膜的电荷的第一势垒高。

17. 发明申请

US20090294823A1 METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT USING A SELECTIVE DISPOSAL SPACER TECHNIQUE AND SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURED THEREBY 有权
标题翻译：使用选择性处理间隔技术制造半导体集成电路的方法和制造半导体集成电路的方法
公开(公告)号：US20090294823A1
公开(公告)日：2009-12-03
申请号：US12538798
申请日：2009-08-10
申请人： Sang-Eun LEE , Yun-Heub SONG
发明人： Sang-Eun LEE , Yun-Heub SONG
IPC分类号： H01L27/105 , H01L29/94 , H01L29/78
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/76224 , H01L27/0207 , H01L27/105 , H01L27/11526 , H01L27/11539 , H01L27/11541
摘要： Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor substrate, wherein a first space and a second space wider than the first space are disposed between the gate patterns; forming a first impurity region in the semiconductor substrate under the first space and forming a second impurity region in the semiconductor substrate under the second space; forming insulation spacers on sidewalls of the gate patterns, wherein a portion of the second impurity region is exposed and the first impurity region is covered with the insulation spacers; etching the insulation spacers, wherein an opening width of the second impurity region is enlarged and wherein the etching is carried out with a wet etching process; and forming an interlayer insulating layer on the overall structure including the gate patterns.
摘要翻译：使用选择性一次性间隔器技术制造半导体集成电路的方法和由此制造的半导体集成电路。该方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极图案，其中在所述栅极图案之间设置比所述第一空间宽的第一空间和第二空间; 在所述第一空间下的所述半导体衬底中形成第一杂质区，并在所述第二空间下在所述半导体衬底中形成第二杂质区; 在所述栅极图案的侧壁上形成绝缘间隔物，其中所述第二杂质区域的一部分被暴露，并且所述第一杂质区域被所述绝缘间隔物覆盖; 蚀刻绝缘间隔物，其中第二杂质区域的开口宽度增大，并且其中蚀刻通过湿蚀刻工艺进行; 以及在包括栅极图案的整体结构上形成层间绝缘层。

18. 发明授权

US07592667B2 Semiconductor device including nonvolatile memory and method for fabricating the same 有权
标题翻译：包括非易失性存储器的半导体器件及其制造方法
公开(公告)号：US07592667B2
公开(公告)日：2009-09-22
申请号：US11865894
申请日：2007-10-02
申请人： Masataka Takebuchi , Fumitaka Arai
发明人： Masataka Takebuchi , Fumitaka Arai
IPC分类号： H01L29/788
CPC分类号： H01L21/823857 , H01L27/112 , H01L27/1122 , H01L27/11529 , H01L27/11536 , H01L27/11539 , H01L27/11546
摘要： A semiconductor device including a nonvolatile memory and the fabrication method of the same is described formed on a semiconductor substrate. According to the semiconductor device, a second gate electrode film is used for a gate electrode film of a logic circuit, and for a control gate electrode film of a nonvolatile memory. As the second gate electrode film is formed at a relatively later step in fabrication, subsequent thermal process may be avoided. The gate structure is suitable for miniaturization of the transistor in the logic circuit.
摘要翻译：描述了在半导体衬底上形成包括非易失性存储器的半导体器件及其制造方法。根据半导体器件，第二栅电极膜用于逻辑电路的栅电极膜和非易失性存储器的控制栅电极膜。由于第二栅极电极膜在相对较后的制造步骤中形成，所以可以避免随后的热处理。栅极结构适合于逻辑电路中的晶体管的小型化。

19. 发明授权

US07588979B2 Method of manufacturing a semiconductor integrated circuit using a selective disposable spacer technique and semiconductor integrated circuit manufactured thereby 有权
标题翻译：使用选择性一次性间隔物技术制造半导体集成电路的方法和由此制造的半导体集成电路
公开(公告)号：US07588979B2
公开(公告)日：2009-09-15
申请号：US11671438
申请日：2007-02-05
申请人： Sang-Eun Lee , Yun-Heub Song
发明人： Sang-Eun Lee , Yun-Heub Song
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/76224 , H01L27/0207 , H01L27/105 , H01L27/11526 , H01L27/11539 , H01L27/11541
摘要： Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor substrate, wherein a first space and a second space wider than the first space are disposed between the gate patterns; forming a first impurity region in the semiconductor substrate under the first space and forming a second impurity region in the semiconductor substrate under the second space; forming insulation spacers on sidewalls of the gate patterns, wherein a portion of the second impurity region is exposed and the first impurity region is covered with the insulation spacers; etching the insulation spacers, wherein an opening width of the second impurity region is enlarged and wherein the etching is carried out with a wet etching process; and forming an interlayer insulating layer on the overall structure including the gate patterns.
摘要翻译：使用选择性一次性间隔器技术制造半导体集成电路的方法和由此制造的半导体集成电路。该方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极图案，其中在所述栅极图案之间设置比所述第一空间宽的第一空间和第二空间; 在所述第一空间下的所述半导体衬底中形成第一杂质区，并在所述第二空间下在所述半导体衬底中形成第二杂质区; 在所述栅极图案的侧壁上形成绝缘间隔物，其中所述第二杂质区域的一部分被暴露，并且所述第一杂质区域被所述绝缘间隔物覆盖; 蚀刻绝缘间隔物，其中第二杂质区域的开口宽度增大，并且其中蚀刻通过湿蚀刻工艺进行; 以及在包括栅极图案的整体结构上形成层间绝缘层。

20. 发明申请

US20080085609A1 METHOD FOR PROTECTING HIGH-TOPOGRAPHY REGIONS DURING PATTERNING OF LOW-TOPOGRAPHY REGIONS 审中-公开
标题翻译：保护低地层地区高原地区的方法
公开(公告)号：US20080085609A1
公开(公告)日：2008-04-10
申请号：US11461033
申请日：2006-07-31
申请人： James E. Vasek , Nicole R. Ellis , Chong-Cheng Fu
发明人： James E. Vasek , Nicole R. Ellis , Chong-Cheng Fu
IPC分类号： H01L21/31
CPC分类号： H01L21/32139 , H01L27/105 , H01L27/11526 , H01L27/11539
摘要： A method for protecting at least one high-topography region on a substrate having both the at least one high-topography region and the at least one low-topography region is provided. The method comprises patterning a thick photo-resist layer having a first thickness, such that the thick photo-resist layer is formed on at least a portion of only the at least one high-topography region, wherein the high-topography region comprises a plurality of semiconductor devices of a first type. The method further comprises patterning a thin photo-resist layer having a second thickness, wherein the first thickness is greater than the second thickness, such that the patterned thin photo-resist layer is formed on at least a portion of only the at least one low-topography region. The method further comprises forming a plurality of semiconductor devices of a second type in the at least the portion of the low-topography region. The method further comprises removing both the thick photo-resist layer and the thin photo-resist layer.
摘要翻译：提供了一种用于保护具有至少一个高地形区域和至少一个低地形区域的基底上的至少一个高地形区域的方法。该方法包括图案化具有第一厚度的厚的光致抗蚀剂层，使得厚的光致抗蚀剂层形成在仅至少一个高地形区域的至少一部分上，其中高地形区域包括多个的第一类半导体器件。该方法还包括对具有第二厚度的薄的光致抗蚀剂层进行图案化，其中第一厚度大于第二厚度，使得图案化的光致抗蚀剂层形成在至少一个低至少一个的至少一部分上地形区域。该方法还包括在低地形区域的至少一部分中形成第二类型的多个半导体器件。该方法还包括去除厚的光致抗蚀剂层和薄的光致抗蚀剂层。

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